SLOS321D − MAY 2000 − REVISED JANUARY 2004 features key applications D High Performance D D D D Single-Ended To Differential Conversion − 150 MHz −3 dB Bandwidth (VCC = ±5 V) D Differential ADC Driver − 650 V/µs Slew Rate (VCC = ±15 V) D Differential Antialiasing − −89 dB Third Harmonic Distortion at D Differential Transmitter and Receiver 1 MHz D Output Level Shifter − −83 dB Total Harmonic Distortion at 1 MHz − 7.6 nV/√Hz Input-Referred Noise Differential Input/Differential Output THS4150 THS4151 D, DGN, DGK PACKAGES D, DGN, DGK PACKAGES − Balanced Outputs Reject Common-Mode (TOP VIEW) (TOP VIEW) Noise − Differential Reduced Second Harmonic VIN− VIN+ VIN− VIN+ 1 8 1 8 Distortion VOCM PD VOCM NC 2 7 2 7 Wide Power Supply Range VCC− VCC+ V V 3 6 3 6 CC− CC+ − VCC = 5 V Single Supply to ±15 V Dual VOUT+ V V VOUT− 4 5 4 5 OUT− OUT+ Supply ICC(SD) = 1 mA (VCC = ±5) in Shutdown HIGH-SPEED DIFFERENTIAL I/O FAMILY Mode (THS4150) description The THS415x is one in a family of fully differential input/differential output devices fabricated using Texas Instruments’ state-of-the-art BiComI complementary bipolar process. 100 MHz, 43 V/µs, 3.7 nV/√Hz THS413x 150 MHz, 51 V/µs, 1.3 nV/√Hz THS414x 160 MHz, 450 V/µs, 6.5 nV/√Hz typical A/D application circuit VDD 5V VIN VOCM + − AVDD DVDD AIN − + AIN AVSS Vref 1 X THS4151 1 − −40 THD − Total Harmonic Distortion − dB THS412x THS4150 SHUTDOWN THS4151 RELATED DEVICES DESCRIPTION NUMBER OF CHANNELS TOTAL HARMONIC DISTORTION vs FREQUENCY The THS415x is made of a true fully-differential signal path from input to output. This design leads to an excellent common-mode noise rejection and improved total harmonic distortion. DEVICE DEVICE DIGITAL OUTPUT −50 Gain = 1, Rf = 390 Ω, RL = 800 Ω, VO = 2 Vpp, VCC = 5 V to ±15 V −60 −70 Single Input to Differential Output −80 Differential Input to Differential Output −90 −100 100 k 1M 10 M f − Frequency − Hz −5 V 100 M Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001 − 2004, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLOS321D − MAY 2000 − REVISED JANUARY 2004 AVAILABLE OPTIONS PACKAGED DEVICES TA MSOP PowerPAD SMALL OUTLINE (D) 0°C to 70°C −40°C to 85°C EVALUATION MODULES MSOP (DGN) SYMBOL (DGK) THS4150CD THS4150CDGN AQB THS4150CDGK SYMBOL ATT THS4150EVM THS4151CD THS4151CDGN AQD THS4151CDGK ATU THS4151EVM THS4150ID THS4150IDGN AQC THS4150IDGK AST − THS4151ID THS4151IDGN AQE THS4151IDGK ASU − absolute maximum ratings over operating free–air temperature range (unless otherwise noted)† Supply voltage, VCC− to VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC Output current, IO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, TJ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum junction temperature, continuous operation, long term reliability, TJ (see Note 3) . . . . . . . . 125°C Operating free-air temperature, TA:C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C ESD ratings: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500 V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The THS415x may incorporate a PowerPad on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the PowerPad thermally enhanced package. NOTE 2: The absolute maximum temperature under any condition is limited by the constraints of the silicon process. NOTE 3: The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATING TABLE POWER RATING§ PACKAGE θJA ‡ (°C/W) θJC (°C/W) D 97.5 38.3 TA = 25°C 1.02 W TA = 85°C 410 mW DGN 58.4 4.7 1.71 W 685 mW DGK 260 54.2 385 mW 154 mW ‡ This data was taken using the JEDEC standard High−K test PCB. § Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long term reliability. recommended operating conditions MIN Dual supply Supply voltage, VCC+ to VCC− Single supply C suffix Operating free-air temperature, TA I suffix PowerPAD is a trademark of Texas Instruments. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP MAX ± 2.5 ±15 5 30 0 70 −40 85 UNIT V °C SLOS321D − MAY 2000 − REVISED JANUARY 2004 electrical characteristics, VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted)† dynamic performance PARAMETER BW Small signal bandwidth (−3 dB) TEST CONDITIONS VCC = 5 VCC = ±5 MIN SR ts Small signal bandwidth (−3 dB) Slew rate (see Notes 1) Settling time to 0.1% Settling time to 0.01% MAX UNIT 150 Gain = 1, Rf = 390 Ω 150 VCC = ±15 VCC = 5 BW TYP MHz 150 80 VCC = ±5 VCC = ±15 Gain = 2, Rf = 750 Ω VCC = ±15, Gain = 1 81 MHz 81 650 V/µs 53 Differential step voltage = 2 VPP, Gain = 1 ns 247 † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. NOTE 4: Slew rate is measured from an output level range of 25% to 75%. distortion performance PARAMETER TEST CONDITIONS VCC = 5 THD Total harmonic distortion Differential input, differential output Gain = 1, Rf = 390 Ω,, RL = 800 Ω VO = 2 VPP VCC = ±5 VCC = ±15 Spurious free dynamic range (SFDR) VO = 2 VPP VO = 0.14 VRMS MIN TYP MAX UNIT f = 1 MHz −85 f = 8 MHz −66 f = 1 MHz −83 f = 8 MHz −65 f = 1 MHz −84 f = 8 MHz −65 f = 1 MHz −87 dB -95 dBc Third intermodulation distortion Gain = 1, f = 20 MHz † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. dB noise performance PARAMETER TEST CONDITIONS Vn Input voltage noise f = 10 kHz In Input current noise f = 10 kHz † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP MAX UNIT 7.6 nV/√Hz 1.78 pA/√Hz 3 SLOS321D − MAY 2000 − REVISED JANUARY 2004 electrical characteristics, VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted) (continued)† dc performance PARAMETER TEST CONDITIONS Open loop gain Input offset voltage VOS Input offset voltage, referred to VOCM Offset drift IIB IOS MIN TA = 25°C TA = full range TYP 63 Input offset current UNIT dB 60 TA = 25°C TA = full range 1.1 TA = 25°C TA = full range 0.6 7 8.5 TA = full range µV/°C 7.3 15 250 1200 TA = full range TA = full range Shutdown delay to output † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. mV 8 7 Input bias current Offset drift MAX 67 µA nA 0.7 nA/°C 1.1 µs input characteristics PARAMETER CMRR Common-mode rejection ratio VICR ri Common-mode input voltage range Ci Input capacitance, closed loop ro Output resistance Input resistance TEST CONDITIONS TA = full range MIN −75 Measured into each input terminal Open loop/single ended ro(SD) Output resistance Shutdown † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. TYP MAX UNIT −83 dB −3.8 to 4.6 V 14.4 MΩ 3.9 pF 0.4 Ω 636 Ω output characteristics PARAMETER Output voltage swing IO Output current, RL = 7 Ω TEST CONDITIONS TYP 0.9 to 4.1 VCC = 5 V VCC = ±5 V TA = 25°C TA = full range ±3.7 VCC = ±15 V TA = 25°C TA = full range ±11.6 30 VCC = 5 V TA = 25°C TA = full range VCC = ±5 V TA = 25°C TA = full range 45 VCC = ±15 V TA = 25°C TA = full range 65 † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. 4 MIN 1.2 to 3.8 TA = 25°C TA = full range POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 1.2 to 3.8 ±3.9 ±3.6 V ±12.7 ±11 45 25 60 mA 35 50 85 SLOS321D − MAY 2000 − REVISED JANUARY 2004 electrical characteristics, VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted) (continued)† power supply PARAMETER TEST CONDITIONS MIN Single supply VCC ICC Supply voltage range Split supply Quiescent current (shutdown) (THS4150) PSRR Power supply rejection ratio (dc) MAX UNIT 5 33 ±2 ±15 ±16.5 18.5 VCC = ±5 V TA = 25°C TA = full range 15.8 VCC = ±15 V TA = 25°C TA = full range 17.5 21 1 1.3 Quiescent current (per amplifier) ICC(SD) TYP 4 21 mA 23 TA = 25°C TA = full range TA = 25°C TA = full range V mA 1.5 70 90 dB 65 † The full range temperature is 0°C to 70°C for the C suffix, and −40°C to 85°C for the I suffix. TYPICAL CHARACTERISTICS Table of Graphs FIGURE SR Small signal frequency response 1, 2 Large signal frequency response 3 Settling time 4 Slew rate Total harmonic distortion vs Temperature 5 vs Frequency 6 vs Output voltage 7 vs Frequency 8−13 vs Output voltage 14−17 Third intermodulation distortion vs Output voltage 18 Vn In Voltage noise vs Frequency 19 Current noise vs Frequency 20 VO Output voltage vs Single-ended load resistance 21 Power supply current shutdown vs Supply voltage 22 Output current range vs Supply voltage 23 VOS CMMR Single-ended output offset voltage vs Common-mode output voltage 24 Common-mode rejection ratio vs Frequency 25 z Impedance of the VOCM terminal vs Frequency 26 zo Output impedance (powered up) vs Frequency 27 zo Output impedance (shutdown) vs Frequency 28 PSRR Power supply rejection ratio vs Frequency 29 Harmonic distortion POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLOS321D − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE 50 1 VCC = ±5 V VI = 22.5 mVRMS G = 100 40 VCC = ±5 VCC = 5 0.5 0 20 G = 10 G=5 10 VCC = ±15 −0.5 G − Gain − dB G − Gain − dB 30 G=2 G=1 −1 −1.5 −2 −2.5 0 Gain = 1 Rf = 390 Ω, RL = 800 Ω, VI = 22.5 mVRMS −3 −10 −3.5 −20 100 k 1M 100 M 10 M −4 10 k 1G 100 k f − Frequency − Hz 1M Figure 2 SETTLING TIME LARGE SIGNAL FREQUENCY RESPONSE 2.3 1 VCC = 5 0.5 VCC = ±5 Rf = 390 Ω, CF = 1 pF, VCC = ±5 V, VO = 4 Vpp, Gain = 1 2.2 VCC = ±15 −0.5 G − Gain − dB VO − Output Voltage − V 0 −1 −1.5 −2 −2.5 −3.5 −4 100 k Gain = 1 Rf = 390 Ω, RL = 800 Ω, VI = 0.2 VRMS 2.1 2 1.9 1.8 Settling to 1% = 17.2 ns Settling to 0.1% = 53.3 ns Settling to 0.01% = 247.5 ns 1.7 1.6 1.5 1M 10 M 100 M 1G 0 50 100 150 200 ts − Settling Time − ns f − Frequency − Hz Figure 3 6 100 M f − Frequency − Hz Figure 1 −3 10 M Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 250 300 SLOS321D − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS SLEW RATE vs TEMPERATURE TOTAL HARMONIC DISTORTION vs FREQUENCY 700 −40 THD − Total Harmonic Distortion − dB CL= 0, CF = 1 pF VCC = ±15 V, VO = 2 VPP 600 VCC = ±15 V, VO = 4 VPP 550 VCC = ±5 V, VO = 2 VPP 500 450 400 −40 VCC = ±5 V, VO = 4 VPP −20 40 0 20 60 T − Temperature −°C 80 −50 −60 −70 Single Input to Differential Output −80 Differential Input to Differential Output −90 −100 100 k 100 1M 10 M 100 M f − Frequency − Hz Figure 5 Figure 6 TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGE −70 THD − Total Harmonic Distortion − dB SR − Slew Rate − V/µ s 650 Gain = 1, Rf = 390 Ω, RL = 800 Ω, VO = 2 Vpp, VCC = ±5 V to ±15 V VCC = ±5 to ±15 Gain = 1, Rf = 390 Ω, RL = 800 Ω, f = 1 MHz Single Input to Differential Output −80 Differential Input to Differential Output −90 −100 0.2 1.2 2.2 3.2 VO − Output Voltage − V 4.2 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLOS321D − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY −40 −60 −50 Harmonic Distortion − dB Harmonic Distortion − dB −50 −40 Single Input to Differential Output Gain = 1, Rf = 390 Ω, RL = 800 Ω, VO = 2 Vpp, VCC = ±2.5 V −70 3rd HD −80 2nd HD −90 −100 5th HD 4th HD −110 −120 100 k 1M −60 Single Input to Differential Output Gain = 1, Rf = 390 Ω, RL = 800 Ω, VO = 2 Vpp, VCC = ±5 V 5th HD −70 3rd HD −80 −90 2nd HD −100 −110 10 M 4th HD −120 100 k 100 M 1M f − Frequency − Hz Figure 8 HARMONIC DISTORTION vs FREQUENCY −40 −60 −50 5th HD −70 −80 2nd HD −90 −100 −110 −120 100 k 8 −40 Single Input to Differential Output Harmonic Distortion − dB Harmonic Distortion − dB −50 100 M Figure 9 HARMONIC DISTORTION vs FREQUENCY Gain = 1, Rf = 390 Ω, RL = 800 Ω, VO = 2 Vpp, VCC = ±15 V 10 M f − Frequency − Hz −60 Gain = 1, Rf = 390 Ω, RL = 800 Ω, VO = 2 Vpp, VCC = ±2.5 V Differential Input to Differential Output −70 3rd HD −80 2nd HD −90 4th HD −100 5th HD 3rd HD −110 4th HD 1M 10 M 100 M −120 10 k 100 k 1M f − Frequency − Hz f − Frequency − Hz Figure 10 Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 M SLOS321D − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY −40 −40 −60 −70 −80 3rd HD 2nd HD −90 5th HD −100 4th HD −110 −120 100 k 1M Gain = 1, Rf = 390 Ω, RL = 800 Ω, VO = 2 Vpp, VCC = ±15 V −50 Harmonic Distortion − dB −50 Harmonic Distortion − dB Differential Input to Differential Output Gain = 1, Rf = 390 Ω, RL = 800 Ω, VO = 2 Vpp, VCC = ±5 V −60 −70 −80 3rd HD 2nd HD −90 4th HD −100 5th HD −110 10 M −120 10 k 100 M 100 k 1M 10 M f − Frequency − Hz f − Frequency − Hz Figure 13 Figure 12 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs OUTPUT VOLTAGE −70 −70 Single Input to Differential Output Single Input to Differential Output 3rd HD −80 3rd HD −80 2nd HD Harmonic Distortion − dB Harmonic Distortion − dB Differential Input to Differential Output 5th HD −90 −100 4th HD Gain = 1, Rf = 390 Ω, RL = 800 Ω, VCC = ±5 V f = 1 MHz −110 2nd HD −90 5th HD −100 Gain = 1, Rf = 390 Ω, RL = 800 Ω, VCC = ±15 V f = 1 MHz −110 −120 4th HD −120 0 1 2 3 4 5 0 VO − Output Voltage − V 1 2 3 4 5 VO − Output Voltage − V Figure 14 Figure 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLOS321D − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs OUTPUT VOLTAGE −70 −70 Differential Input to Differential Output Differential Input to Differential Output 3rd HD −80 Harmonic Distortion − dB Harmonic Distortion − dB −80 2nd HD −90 5th HD −100 4th HD Gain = 1, Rf = 390 Ω, RL = 800 Ω, VCC = ±5 V f = 1 MHz −110 2nd HD −90 5th HD −100 Gain = 1, Rf = 390 Ω, RL = 800 Ω, VCC = ±15 V f = 1 MHz −110 −120 4th HD −120 0 1 2 3 4 5 0 VO − Output Voltage − V 1 2 100 Gain = 1, Rf = 390 Ω, RL = 800 Ω, VCC = ±5 V, f = 1 MHz VCC = 5 V to ±15 V Single Input to Differential Output V n − Voltage Noise − nV/ Hz Third Intermodulation Distortion − dB 5 VOLTAGE NOISE vs FREQUENCY −70 −90 −100 −110 −12 4 Figure 17 THIRD INTERMODULATION DISTORTION vs OUTPUT VOLTAGE −80 3 VO − Output Voltage − V Figure 16 −7 −2 10 1 3 8 10 VO − Output Voltage − V 100 1k f − Frequency − Hz Figure 18 10 3rd HD Figure 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 k 100 k SLOS321D − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS CURRENT NOISE vs FREQUENCY OUTPUT VOLTAGE vs SINGLE-ENDED LOAD RESISTANCE 100 15 VCC = ±15 V VOUT+ 10 VO − Output Voltage − V I n − Current Noise − pA/ Hz VCC = 5 V to ±15 V 10 VCC = ±5 V VOUT+ 5 0 VOUT− VCC = − ±5 V −5 VOUT− −10 VCC = − ±15 V 1 10 100 1k 10 k f − Frequency − Hz −15 10 100 k 100 1k 10 k RL − Single-Ended Load Resistance − Ω Figure 20 Figure 21 POWER SUPPLY CURRENT SHUTDOWN vs SUPPLY VOLTAGE OUTPUT CURRENT RANGE vs SUPPLY VOLTAGE 2.5 100 TA = 25°C TA = 40°C 90 I O − Output Current Range − mA I CC− Power Supply Current Shutdown − mA 100 k 2 1.5 1 0.5 TA = 25°C 80 70 TA = 125°C 60 TA = 85°C 50 40 30 20 10 0 0 2 4 6 8 10 12 VCC − Supply Voltage − ±V 14 16 0 1 2 3 Figure 22 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC − Supply Voltage − V Figure 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLOS321D − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS COMMON MODE REJECTION RATIO vs FREQUENCY 0 100 CMRR − Common Mode Rejection Ratio − dB VOS − Single-Ended Output Offset Voltage − mV SINGLE-ENDED OUTPUT OFFSET VOLTAGE vs COMMON-MODE OUTPUT VOLTAGE VCC = 2.5 V 60 VCC = 5 V 20 −20 VCC = 15 V −60 −100 −12 −10 VCC = 5 V to ±15 V, VI = 0.25 VRMS −20 −30 −40 −50 −60 −70 −80 −90 1M −7 −2 3 8 VOCM − Common-Mode Output Voltage − V 10 M Figure 25 IMPEDANCE OF THE VOCM TERMINAL vs FREQUENCY OUTPUT IMPEDANCE (POWERED UP) vs FREQUENCY 100 16000 VCC = ±5 V VCC = 5 V to ±15 V 14000 Output Impedance − Ω z − Impedance of the VOCM Terminal − Ω 1G f − Frequency − Hz Figure 24 12000 10000 8000 6000 10 1 4000 2000 0 100 k 1M 10 M 100 M 1G 0.1 100 k 1M 10 M f − Frequency − Hz f − Frequency − Hz Figure 26 12 100 M Figure 27 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 M 1G SLOS321D − MAY 2000 − REVISED JANUARY 2004 TYPICAL CHARACTERISTICS OUTPUT IMPEDANCE (SHUTDOWN) vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY 1000 −10 PSRR − Power Supply Rejection Ratio − dB Output Impedance (Shutdown) − Ω VCC = ±5 V Rf = R(g) = 500 Ω 100 10 100 k 1M 10 M 100 M 1G VCC+ = 2.5 V, 5 V, 15 V −20 −30 −40 −50 −60 −70 100 k f − Frequency − Hz Figure 28 VCC− = 225 mVRMS + (-2.5 V) dc = 225 mVRMS + (-5 V) dc = 225 mVRMS + (-15 V) dc 1M 10 M 100 M f − Frequency − Hz 1G Figure 29 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLOS321D − MAY 2000 − REVISED JANUARY 2004 APPLICATION INFORMATION resistor matching Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion will diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. VOCM sets the dc level of the output signals. If no voltage is applied to the VOCM pin, it will be set to the midrail voltage internally defined as: ǒVCC)Ǔ ǒ ) V Ǔ CC– 2 In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential mode is the same as the input when gain is 1. VOCM has a high bandwidth capability up to the typical operation range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM pin as a bypass capacitor. Figure 30 shows the simplified diagram of the THS415x. VCC+ Output Buffer VIN− x1 VOUT+ C VIN+ Vcm Error Amplifier + _ C x1 VCC+ 30 kΩ 30 kΩ VCC− VCC− VOCM Figure 30. THS415x Simplified Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 R VOUT− Output Buffer 14 R SLOS321D − MAY 2000 − REVISED JANUARY 2004 APPLICATION INFORMATION data converters Data converters are one of the most popular applications for the fully differential amplifiers. The following schematic shows a typical configuration of a fully differential amplifier attached to a differential ADC. VDD VCC 5V VIN + − AVDD AIN1 − + AIN2 AVSS VOCM 0.1 µF DVDD Vref −5 V VCC− Figure 31. Fully Differential Amplifier Attached to a Differential ADC Fully differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit. If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input terminal of the amplifier should not exceed the common-mode input voltage range. VDD VCC 5V VIN + − AVDD AIN1 − + AIN2 AVSS VOCM 0.1 µF DVDD Vref Figure 32. Fully Differential Amplifier Using a Single Supply POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLOS321D − MAY 2000 − REVISED JANUARY 2004 APPLICATION INFORMATION data converters (continued) Some single supply applications may require the input voltage to exceed the common-mode input voltage range. In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within the specifications of the amplifier. VDD VCC Rf VCC RPU R(g) VIN 5V VP V OCM 0.1 µF VOUT + − − + VOUT R(g) RPU VCC AVDD DVDD AIN1 THS1206 AIN2 Vref AVSS Rf Figure 33. Circuit With Improved Common-Mode Input Voltage The following equation is used to calculate RPU: R PU + V –V P CC 1 1 V –V ) V –V IN P RG P RF OUT ǒ Ǔ ǒ Ǔ driving a capacitive load Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS415x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 34. A minimum value of 20 Ω should work well for most applications. For example, in 50-Ω transmission systems, setting the series resistor value to 20 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. 390 Ω 20 Ω 390 Ω Output THS415x 20 Ω 390 Ω Output 390 Ω Figure 34. Driving a Capacitive Load 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLOS321D − MAY 2000 − REVISED JANUARY 2004 APPLICATION INFORMATION Active antialias filtering For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass filters can prevent the aliasing of the high frequency noise with the frequency of operation. The following figure presents a method by which the noise may be filtered in the THS415x. R2 C1 VCC R4 + R1 − VIN− + VIN+ R(t) THS415x − + C2 Vs C3 R3 VIN+ R1 THS1050 VIN− VOCM VOCM R3 C3 VIC R4 VCC− + C1 R2 Figure 35. Antialias Filtering The transfer function for this filter circuit is: ȡ ȣȡ Rt ȣ 2R4 ) Rt K ȧ ȧ xȧ H (f) + d ȧ f 2 1 jf ȧ 1 ) j2πfR4RtC3ȧ 2R4 ) Rt Ȥ Ȣ–ǒFSF x fcǓ ) Q FSF x fc ) 1Ȥ Ȣ FSF x fc + Where K + R2 R1 Ǹ2 x R2R3C1C2 1 and Q + Ǹ R3C1 ) R2C1 ) KR3C1 2π 2 x R2R3C1C2 K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency-scaling factor, and Q is the quality factor. FSF + ǸRe 2 ) |Im| 2 and Q + ǸRe 2 ) |Im| 2 2Re where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 = C, and C2 = nC results in: FSF x fc + Ǹ2 x mn 1 and Q + Ǹ 1 ) m(1 ) K) 2πRC 2 x mn Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select C and calculate R for the desired fc. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SLOS321D − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION theory of operation The THS415x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereas fully differential amplifiers are differential in/differential out. THS415x Fully differential Amplifier VCC+ Differential Amplifier Rf R(g) _ VIN+ + R(g) _ VIN− + Rf VO+ + _ VO− VOCM VCC− Figure 36. Differential Amplifier Versus a Fully Differential Amplifier To understand the THS415x fully differential amplifiers, the definition for the pinouts of the amplifier are provided. Input voltage definition V Output voltage definition V Transfer function V ǒ + V ID Ǔ – ǒVI–Ǔ I) ǒ OD + V OD + V Output common mode voltage V OC Ǔ – ǒVO–Ǔ O) ID V IC V + OC ǒVI)Ǔ ) ǒVI–Ǔ 2 + ǒVO)Ǔ ) 2 x Aǒ Ǔ f + V OCM Differential Structure Rejects Coupled Noise at the Input Differential Structure Rejects Coupled Noise at the Output VCC+ VIN− VIN+ Differential Structure Rejects Coupled Noise at the Power Supply _ + VO+ + _ VO− VOCM VCC− Figure 37. Definition of the Fully Differential Amplifier 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ǒVO–Ǔ SLOS321D − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION theory of operation (continued) The following schematics depict the differences between the operation of the THS415x, fully differential amplifier, in two different modes. Fully differential amplifiers can work with differential input or can be implemented as single in/differential out. Rf VIN− R(g) VCC+ VO+ −+ Vs +− VIN+ VO− VOCM R(g) VCC− Note: For proper operation, maintain symmetry by setting Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g) ⇒ A = Rf/R(g) Rf Figure 38. Amplifying Differential Signals Rf VIN− R(g) VIN+ VCC+ RECOMMENDED RESISTOR VALUES −+ VO+ +− VO− VOCM R(g) Vs GAIN R(g) Ω Rf Ω 1 2 5 10 390 374 402 402 390 750 2010 4020 VCC− Rf Figure 39. Single In With Differential Out If each output is measured independently, each output is one-half of the input signal when gain is 1. The following equations express the transfer function for each output: V O) + V I) 2 ) V OCM The second output is equal and opposite in sign: V O– + –V I) 2 ) V OCM VOCM will be set to midrails if it is not derived by any external power source. Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting amplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice as much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input signal of 1 VPP. If the output of the amplifier is 2 VPP, then it will not be practical to feed a 2-VPP signal into the targeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-VPP signals with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differential amplifier. The final result indicates twice as much dynamic range. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SLOS321D − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION theory of operation (continued) Figure 40 illustrates the increase in dynamic range. The gain factor should be considered in this scenario. The THS415x fully differential amplifier offers an improved CMRR and PSRR due to its symmetrical input and output. Furthermore, second harmonic distortion is improved. Second harmonics tend to cancel because of the symmetrical output. a VOD= 1−0 = 1 VCC+ VIN− VIN+ +1 _ + + _ VO+ 0 VO− +1 0 VOCM VOD = 0−1 = −1 VCC− b Figure 40. Fully Differential Amplifier With Two 1-VPP Signals Similar to the standard inverting amplifier configuration, input impedance of a fully differential amplifier is selected by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to implement the differential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the fully differential amplifier. The following schematic depicts the general format of instrumentation amplifiers. The general transfer function for this circuit is: V ǒ Ǔ R OD f 1 ) 2R2 + R R1 V –V (g) IN1 IN2 THS4012 VIN1 R(g) + _ Rf R2 _ R1 THS415x + R2 _ VIN2 + THS4012 R(g) Rf Figure 41. Fully Differential Instrumentation Amplifier 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLOS321D − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION circuit layout considerations To achieve the levels of high frequency performance of the THS415x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS415x evaluation board is available to use as a guide for layout or for evaluating the device performance. D Ground planes—It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements—Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components—Using surface-mount passive components is recommended for high frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 SLOS321D − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION power-down mode The power-down mode is used when power saving is required. The power-down terminal (PD) found on the THS415x is an active low terminal. If it is left as a no-connect terminal, the device will always stay on due to an internal 50 kΩ resistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC−. This means that if the PD terminal is 1.4 V above VCC −, the device is active. If the PD terminal is less than 1.4 V above VCC −, the device is off. For example, if VCC − = −5 V, then the device is on when PD reaches 3.6 V, (-5 V + 1.4 V = −3.6 V). By the same calculation, the device is off below −3.6 V. It is recommended to pull the terminal to VCC − in order to turn the device off. The following graph shows the simplified version of the power-down circuit. While in the power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is typically greater than 1 MΩ in the power-down state. VCC 50 kΩ To Internal Bias Circuitry Control PD VCC− Figure 42. Simplified Power-Down Circuit Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of the amplifier. An example of the closed-loop output impedance is shown in Figure 43. OUTPUT IMPEDANCE (SHUTDOWN) vs FREQUENCY 1000 Output Impedance (Shutdown) − Ω VCC = ±5 V Rf = R(g) = 500 Ω 100 10 100 k 1M 10 M 100 M f Frequency − Hz Figure 43 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1G SLOS321D − MAY 2000 − REVISED JANUARY 2004 PRINCIPLES OF OPERATION general PowerPAD design considerations The THS415x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 44(a) and Figure 44(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 44(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking. More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002). This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 44. Views of Thermally Enhanced DGN Package POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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