EM MICROELECTRONIC - MARIN SA
EM6620
Ultra Low Power Microcontroller with 4x8 LCD Driver
Features
Figure 1. Architecture
• Low Power
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
- 2.1 µA active mode, LCD On
- 0.5 µA standby mode, LCD Off
- 0.1 µA sleep mode
@ 1.5V, 32kHz, 25°C
Low Voltage
- 1.2 to 3.6 V
SVLD - metal mask programmable (2.0V)
ROM
- 1280 × 16 bits
RAM
- 64 × 4 bits
2 clocks per instruction cycle
72 basic instructions
Oscillation supervisor
Timer watchdog (2 sec)
Max. 8 inputs ; port A, port B
max. 4 outputs ; port B
LCD 8 segments, 3 or 4 times multiplexed
Universal 10-bit counter, PWM, event counter
Prescaler down to 1 Hz (crystal = 32 KHz)
1/1000 sec, 12 bit binary coded decimal counter
with hard or software start/stop function
Frequency output 1Hz, 2048 Hz, 32 KHz, PWM
7 internal interrupt sources (BCD counter,
2×10-bit counter, 3× prescaler, SVLD)
5 external interrupt sources (port A, compare)
Description
The EM6620 is an advanced single chip CMOS 4bit microcontroller. It contains ROM, RAM, power
on reset, watchdog timer, oscillation detection
circuit, 10 bit up/down counter, Millisecond counter,
prescaler, voltage level detector (SVLD), compare
input, frequency output, LCD driver and several
clock functions. The low voltage feature and low
power consumption make it the most suitable
controller for battery, stand alone and mobile
equipment. The EM6620 is manufactured using EM
Microeletronic’s Advanced Low Power (ALP) CMOS
Process.
Figure 2. Pin Configuration
Typical Applications
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•
•
•
Timing device
Medical applications
Domestic appliance
Timer / sports timing devices
Safety and security devices
Automotive controls with display
Measurement equipment
Interactive system with display
Bicycle computers
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EM6620
EM6620 at a glance
• Power Supply
- Low voltage low power architecture
including internal voltage regulator
- 1.2 ... 3.6 V battery voltage
- 2.1 µA in active mode (Xtal, LCD on, 25°C)
- 0.5 µA in standby mode (Xtal, LCD off, 25°C)
- 0.1 µA in sleep mode (25°C)
- 32 KHz Oscillator
•
RAM
•
ROM
•
CPU
- 64 x 4 bit, direct addressable
- 1280 x 16 bits, metal mask programmable
•
4-Bit Bi-directional Port B
- All different functions bit-wise selectable
- Direct input read on the port terminals
- Data output latches
- CMOS or Nch. open drain outputs
- Pull-down or pull-up selectable
- Weak pull-up in Nch. open drain mode
- Selectable PWM, 32kHz, 1kHz and 1Hz output
- Dynamic Input Comparator on PB[0] (SVLD level)
• Voltage Level Detector
- Mask selectable level, default 2.0V
- Busy flag during measure
- Interrupt request at end of measure
- 4 bit RISC architecture
- 2 clock cycles per instruction
- 72 basic instructions
• Main Operating Modes and Resets
- Active Mode (CPU is running)
- Standby Mode (CPU in halt)
- Sleep Mode (no clock, reset state)
- Initial reset on power on (POR)
- Watchdog reset (logic and oscillation watchdogs)
- Reset with input combination on port A (register
selectable)
• Liquid Crystal Display Driver
- 8 segments 3 or 4 times multiplexed
- Internal or external voltage multiplier
- Free segment allocation architecture
(metal 2 mask)
- LCD switch off for power save
• Prescaler
- 15 stage system clock divider down to 1Hz
- 3 Interrupt requests; 1Hz, 32Hz or 8Hz, Blink
- Prescaler reset (4kHz to 1Hz)
(LCD)
• 4-Bit Input Port A
- Direct input read on the port terminals
- Debouncer function available on all inputs
- Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by register
- Test variables (software) for conditional jumps
- PA[0] and PA[3] are inputs for the event counter
- PA[3] is Start/Stop input for the millisecond
counter
- Reset with input combination (register selectable)
•
10-Bit Universal Counter
•
Millisecond Counter
- 10, 8, 6 or 4 bit up/down counting
- Parallel load
- Event counting (PA[0] or PA[3])
- 8 different input clocks- Full 10 bit or limited (8, 6, 4 bit) compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[3] and PA[0]
- Pulse width modulation (PWM) output
- 3 digits binary coded decimal counter (12 bits)
- PA[3] signal pulse width and period measurement
- Internal 1000 Hz clock generation
- Hardware or software controlled start stop mode
- Interrupt request on either 1/10 Sec or 1Sec
• Interrupt Controller
- 5 external and 7 internal interrupt request sources
- Each interrupt request individually maskable
- Each interrupt flag individually resettable
- Automatic reset of each interrupt request register
after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request
flag when going into HALT mode
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EM6620
Table of Contents
Features _________________________________1
Description _______________________________1
TYPICAL applications _______________________1
EM6620 at a glance ________________________2
1. PIN DESCRIPTION FOR EM6620 _________ 4
2. OPERATING MODES ___________________ 6
2.1
ACTIVE MODE ________________________6
2.2
STANDBY MODE ______________________6
2.3
SLEEP MODE _________________________6
3.
POWER SUPPLY ______________________ 7
4. RESET _______________________________ 8
4.1
OSCILLATION DETECTION CIRCUIT __________9
4.2
INPUT PORT A RESET ____________________9
4.3
DIGITAL WATCHDOG TIMER RESET ________10
4.4
CPU STATE AFTER RESET _______________10
5. OSCILLATOR AND PRESCALER ________ 11
5.1
OSCILLATOR __________________________11
5.2
PRESCALER __________________________11
6. INPUT AND OUTPUT PORTS ___________ 13
6.1
PORTS OVERVIEW ______________________13
6.2
PORT A______________________________14
6.2.1
IRQ on Port A ____________________14
6.2.2
Pull-up/down _____________________15
6.2.3
Software test variables______________15
6.2.4
Port A for 10-Bit Counter and MSC ___15
6.3
PORT A REGISTERS _____________________15
6.4
PORT B______________________________17
6.4.1
Input / Output Mode _______________17
6.4.2
Pull-up/Down ____________________18
6.4.3
CMOS / NCH. Open Drain Output ____18
6.4.4
PWM and Frequency output _________19
6.5
PB[0] DYNAMIC INPUT COMPARATOR ______19
6.6
PORT B REGISTERS _____________________20
7. 10-BIT COUNTER _____________________ 21
7.1
FULL AND LIMITED BIT COUNTING _________21
7.2
FREQUENCY SELECT AND UP/DOWN COUNTING22
7.3
EVENT COUNTING _____________________23
7.4
COMPARE FUNCTION ___________________23
7.5
PULSE WIDTH MODULATION (PWM) _______23
7.5.1
How the PWM Generator works.______24
7.5.2
PWM Characteristics_______________24
7.6
COUNTER SETUP ______________________25
7.7
10-BIT COUNTER REGISTERS _____________25
8. MILLISECOND COUNTER ______________ 27
8.1
PA[3] INPUT FOR MSC _________________27
8.2
IRQ FROM MSC_______________________27
8.3
MSC-MODES _________________________28
8.4
8.5
MODE SELECTION _____________________ 28
MILLISECOND COUNTER REGISTERS _______ 30
9. INTERRUPT CONTROLLER ____________31
9.1
INTERRUPT CONTROL REGISTERS __________ 32
10.
10.1
SUPPLY VOLTAGE LEVEL DETECTOR _33
SVLD REGISTER ______________________ 33
11.
RAM ______________________________34
12.
12.1
12.2
12.3
12.4
LCD DRIVER _______________________35
LCD CONTROL _______________________ 36
LCD ADDRESSING _____________________ 36
FREE SEGMENT ALLOCATION _____________ 37
LCD REGISTERS ______________________ 37
13.
PERIPHERAL MEMORY MAP _________39
14.
OPTION REGISTER MEMORY MAP ____42
15.
ACTIVE SUPPLY CURRENT TEST _____43
16.
MASK OPTIONS ____________________44
16.1
INPUT / OUTPUT PORTS _________________ 44
16.1.1
Port A Metal Options ______________ 44
16.1.2
Port B Metal Options ______________ 45
16.1.3
Voltage Regulator Option___________ 46
16.1.4
SVLD and Input Comp Level Option __ 46
16.1.5
Debouncer frequency Option ________ 46
16.1.6
User defined LCD Segment allocation _ 46
17.
17.1
17.2
17.3
17.4
TEMP. AND VOLTAGE BEHAVIORS ____47
IDD CURRENT (TYPICAL) _______________ 47
PULL-DOWN RESISTANCE (TYPICAL) _______ 47
PULL-UP RESISTANCE (TYPICAL) __________ 48
OUTPUT CURRENTS (TYPICAL)____________ 48
18.
EM6620 ELECTRICAL SPECIFICATIONS 49
18.1
ABSOLUTE MAXIMUM RATINGS ___________ 49
18.2
HANDLING PROCEDURES ________________ 49
18.3
STANDARD OPERATING CONDITIONS _______ 49
18.4
DC CHARACTERISTICS - POWER SUPPLY ____ 49
18.5
SVLD AND INPUT COMPARATOR _________ 50
18.6
OSCILLATOR _________________________ 50
18.7
DC CHARACTERISTICS - I/O PINS _________ 51
18.8
LCD SEG[8:1] OUTPUTS ________________ 52
18.9
LCD COM[4:1] OUTPUTS _______________ 52
18.10
DC OUTPUT COMPONENT _____________ 52
18.11
LCD VOLTAGE MULTIPLIER ____________ 52
19.
PAD LOCATION DIAGRAM ___________53
20.
20.1
20.2
20.3
PACKAGE & ORDERING INFORMATION 54
ORDERING INFORMATION _______________ 56
PACKAGE MARKING ___________________ 56
CUSTOMER MARKING __________________ 56
21.
SPEC. UPDATE _____________________57
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than
circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves
the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure
that the information given has not been superseded by a more up-to-date version.
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EM6620
1. Pin Description for EM6620
Chip QFP DIL
44
40
1
13
7
2
14
8
3
15
9
4
16
10
5
18
11
QFP
32
9
10
11
12
13
Signal Name
C2B
C2A
C1B
C1A
VL1
Function
Voltage multiplier
Voltage multiplier
Voltage multiplier
Voltage multiplier
Voltage multiplier level 1
6
19
12
14
VL2
Voltage multiplier level 2
7
20
13
15
VL3
Voltage multiplier level 3
8
21
14
16
COM[4]
LCD back plane 4
9
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
29
30
31
32
33
35
36
37
17
18
19
20
21
22
23
24
25
27
28
29
17
18
19
nc
20
21
22
23
24
25
26
27
COM[3]
COM[2]
COM[1]
SEG[8]
SEG[7]
SEG[6]
SEG[5]
SEG[4]
SEG[3]
SEG[2]
SEG[1]
Test
21
38
30
28
PB[0]
22
39
31
29
PB[1]
23
40
32
30
PB[2]
24
41
33
31
PB[3]
LCD back plane 3
LCD back plane 2
LCD back plane 1
LCD segment 8
LCD segment 7
LCD segment 6
LCD segment 5
LCD segment 4
LCD segment 3
LCD segment 2
LCD segment 1
Input test terminal
Internal pull-down 15k
Input/output, open drain
port B terminal 0
Input/output, open drain
port B terminal 1
Input/output, open drain
port B terminal 2
Input/output, open drain
port B terminal 3
25
43
35
32
PA[0]
Input port A terminal 0
26
27
28
1
2
3
36
37
38
1
2
3
PA[1]
PA[2]
PA[3]
Input port A terminal 1
Input port A terminal 2
Input port A terminal 3
29
30
5
6
39
40
4
5
VBAT=VDD
Vreg
Positive power supply
Internal voltage regulator
31
32
33
8
10
11
1
3
5
6
7
8
Qout / Osc2
Qin / Osc1
VSS
Crystal terminal
Crystal terminal
Negative power supply
Remarks
Not needed if ext. supply
Not needed if ext. supply
Not needed if ext. supply
Not needed if ext. supply
LCD level 1 input, if external supply
selected
LCD level 2 input, if external supply
selected
LCD level 3 input, if external supply
selected
Not used if 3 times multiplex
selected
Not bonded for QFP 32
For EM tests only, GND 0 ! except
when needed for MFP programming
Port B data[0] I/O or
dynamic input comparator input
Port B data[1] I/O or
ck[12] output
Port B data[2] I/O or
ck[1] output
Port B data[3] I/O or
PWM output
Testvar 1
Event counter
Testvar 2
Testvar 3
Event counter
MSC start/stop control
MFP Connection
Connect to minimum 100nF,
MFP Connection
32kHz crystal, MFP Connection
32kHz crystal, MFP Connection
Reference terminal, MFP Connection
* gray shaded : terminals needed for MFP programming connections (VDD, VregLogic, Qin, Qout, Test, VSS).
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EM6620
Figure 3. Typical configuration
L C D D is play
C1
VL1
C1
VL2
C1
C O M [4 :1 ]
a ll C a p a c ito rs 1 0 0 n F
c rys ta l
S E G [8 :1 ]
Q IN
QOUT
VL3
C2
C 1A
C 1B
C2
C 2A
C 2B
EM 6620
V D D (V B A T )
V re g
T est
C3
P o rt A
C4
VSS
P o rt B
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EM6620
2. Operating modes
The EM6620 has two low power dissipation modes, standby and sleep. Figure 4 is a transition diagram for
these modes.
2.1 ACTIVE Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Leaving the active mode: via the halt instruction to go into standby mode, writing the SLEEP bit to go
into Sleep mode or detecting the reset condition from port A to go into reset mode.
2.2 STANDBY Mode
Executing a HALT instruction puts the EM6620 into
standby mode. The voltage regulator, oscillator,
watchdog timer, LCD, interrupts, timers and counters
are operating. However, the CPU stops since the
clock related to instruction execution stops.
Registers, RAM and I/O pins retain their states prior
to STANDBY mode. STANDBY is canceled by a
RESET or an Interrupt request if enabled.
Figure 4 Mode transition diagram
Active
Halt
instruction
Sleep bit
write
IRQ
Standby
Sleep
Reset=0
Reset=1
2.3 SLEEP Mode
Writing to the Sleep bit in the RegSysCntl1 register
puts the EM6620 in sleep mode. The oscillator stops
and most functions of the EM6620 are inactive. To
be able to write to the Sleep bit, the SleepEn bit in
RegSysCntl2 must first be set to "1". In SLEEP
mode only the voltage regulator is active to maintain
the RAM data integrity, all other functions are in
reset state. SLEEP mode may be canceled only by
the input reset combination from port A.
Reset=1
Reset=1
Reset
Due to the cold-start characteristics of the oscillator, waking up from sleep mode may take some time to
guarantee stable oscillation. During sleep mode and the following start up the EM6620 is in reset state. Waking
up from sleep mode clears the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to determine if
the EM6620 was powered up (SleepEn = "0") or woken from sleep mode (SleepEn = "1").
TAKE CARE !!! To quit sleep mode, one must be sure to have a suitable defined combination of port A inputs
for reset (see section 4.2). The Bit NoInpReset has no action during sleep mode.
Table 2.3.1 Shows the state of the EM6620 functions in STANDBY and SLEEP modes
FUNCTION
STANDBY
SLEEP
Oscillator
Active
Stopped
Oscillator supervisor
Active
Stopped
Instruction execution
Stopped
Stopped
Interrupt functions
Active
Stopped
Registers and flags
Retained
Reset
RAM data
Retained
Retained
Option registers
Retained
Retained
Timer/Counter's
Active
Reset
Logic watchdog
Active
Reset
I/O port B
Active
High Impedance, no pulls
Input port A
Active
Only active for Reset generation
NoInputRes = "0" for reset generation
NoInputRes = "X"
LCD
Active
Stopped (display off)
Voltage Level Detector
finishes on going measure, then stop
Stopped
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EM6620
3. Power Supply
The EM6620 is supplied by a single external power supply between VDD (Vbat) and VSS (ground). A built-in
voltage regulator generates Vreg providing regulated voltage for the oscillator and the internal logic. The output
drivers are supplied directly from the external supply VDD. A internal power configuration is shown in Figure 5.
To supply the internal core logic it is possible to use either the internal voltage regulator (Vreg < VDD) or Vbat
directly ( Vreg = VDD). The selection is done by metal 1 mask option. By default the voltage regulator is used.
Refer to chapter 16.1.3 for the metal mask selection.
The internal voltage regulator is chosen for high voltage systems. It saves power by reducing the internal core
logic’s power supply to an optimum value. However, due to the inherent voltage drop over the regulator the
minimal VDD value is restricted to 1.4V .
A direct Vbat connection can be selected for systems running on a 1.5V battery. The 1kOhm resistor together
with the external capacitor on Vreg is filtering the VDD supply to the internal core. In this case the minimum
VDD value can be as low as 1.2 V.
Figure 5. Internal power supply
Term inal
V bat
M V reg
M 1B
1kO h m
M 1A
A ll P ad
input &
output
buffers,
S V LD
T erm inal
V reg
R ef. Logic
C ore Logic,
LC D Logic,
O scillator
V oltage m ultiplier,
LC D outputs
R ef. LC D
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EM6620
4. Reset
Figure 6 illustrates the reset structure of the EM6620. One can see that there are five possible reset sources :
(1) Internal initial reset from the Power On Reset (POR) circuitry.
--> POR
(2) External reset by simultaneous high/low inputs to port A.
--> System Reset, Reset CPU
(Combinations are defined in the registers OptInpRSel1 and OptInpRSel2
(3) Internal reset from the Digital Watchdog.
--> System Reset, Reset CPU
(4) Internal reset from the Oscillation Detection Circuit.
--> System Reset, Reset CPU
(5) Internal reset when SLEEP mode is activated.
--> System Reset, Reset CPU
All reset sources activate the System Reset and the Reset CPU. The ‘System Reset Delay’ ensures that the
system reset remains active long enough for all system functions to be reset (active for N system clock cycles).
The ‘CPU Reset Delay’ ensures that the Reset CPU remains active until the oscillator is in stable oscillation.
As well as activating the system reset and the Reset CPU, the POR also resets all option registers and the
sleep enable (SleepEn) latch. System reset and Reset CPU do not reset the option registers nor the sleep
enable latch.
Figure 6. Reset structure
Internal Data Bus
Digital
W atchdog
W rite Reset
Read Status
CK[1]
W rite Active
Read Status
SLEEP
ENABLE
Latch
SLEEP
Latch
R
R
Inhibit
Digital
W atchdog
CPU Reset
Delay
Enable
POR
Reset
CPU
Activate
POR
ck[1]
System Reset
Delay
DEBOUNCE
ck[15]
ck[8]
POR
POR to Option
Registers & SLEEP
ENABLE latch
Oscillation
Detection
Inhibit
Oscillation
detection
CK[10]
Reset from port A Input
combination
NoInpReset
Sleep
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EM6620
4.1 Oscillation Detection Circuit
At power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry,
and thus the system reset. The CPU of the EM6620 remains in the reset state for the ‘CPU Reset Delay’, to
allow the oscillator to stabilize after power up.
The oscillator is disabled during sleep mode. So when waking up from sleep mode, the CPU of the EM6620
remains in the reset state for the ‘CPU Reset Delay’ , to allow the oscillator to stabilize. During this oscillator
stabilization period, the oscillation detection circuit is inhibited.
In active or standby modes, the oscillator detection circuit monitors the oscillator. If it stops for any reason, a
system reset is generated. After clock restart, the CPU waits for the CPU Reset Delay before executing the first
instructions.
The oscillation detection circuitry can be inhibited with NoOscWD = 1 in register RegVLDCntl. At power up, and
after any Reset, the function is activated.
The ‘CPU Reset Delay’ is 32768 system clocks ( ck[16] ) long.
4.2 Input Port A Reset
By writing the OptInpRSel1 and OptInpRSel2 registers it is possible to choose any combination of port A input
values to execute a system reset. The reset condition must be valid for at least 16 ms (system clock = 32 KHz)
in active and standby mode. The applied port A reset condition will immediately trigger a system reset in Sleep
mode.
Bit NoInputReset in option register OptFSelPB selects the input port A reset function in active and standby
mode. If set to "0" the occurrence of the selected combination for input port A reset will trigger a system reset.
Set to ‘1’ the input port A reset function is inhibited.
This option bit has no action in sleep mode, where the occurrence of the selected input port A reset combination
will always immediately trigger a system reset.
Reset combination selection (InpReset) in registers OptInpRSel1 and OptInpRSel2.
InpReset = InpResPA[0] • InpResPA[1] • InpResPA[2] • InpResPA[3]
Figure 7. Input port A reset structure
InpRes1PA[n]
0
0
1
1
n = 0 to 3
InpRes2PA[n]
0
1
0
1
InpResPA[n]
VSS
PA[n]
not PA[n]
VDD
i.e. ; - No reset if InpResPA[n] = VSS.
- Don't care function on a single bit with
its InpResPA[n] = VDD.
BIT
[0]
Input PortA Reset
Bit[0] selection
BIT
[1]
Input PortA Reset
Bit[1] selection
BIT
[2]
Input PortA Reset
Bit[2] selection
BIT
InpRes1PA[3]
[3]
InpRes2PA[3]
- Always Reset if InpResPA[3:0] = 'b1111.
VSS
PA[3]
PA[3]
VDD
0
1 MUX
2
3 1 0
InpResPA
Input
Reset
from
PortA
InpResPA[3]
Input PortA Reset
Bit[3] selection
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EM6620
4.3 Digital Watchdog Timer Reset
The Digital Watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck1]. It
will generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by
activating an inhibit digital watchdog bit (NoLogicWD) located in RegVLDCntl. At power up, and after any
system reset, the watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system
reset signal. This function can be used to detect program overrun, endless loops, etc. For normal operation,
the watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32
KHz), or a system reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and
timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer
operates also in the standby mode and thus, to avoid a system reset, standby should not be active for more
than 2.5 seconds.
From a System Reset state, the watchdog timer will become active after 3.5 seconds. However, if the
watchdog timer is influenced from other sources (i.e. prescaler reset), then it could become active after just
2.5 seconds. It is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the
watchdog every second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the
counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’, {WDVal1 WDVal0}. When reaching
the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the system
reset which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always
reads ‘0’.
Table 4.3.1 Watchdog timer register RegSysCntl2
Bit
Name
Reset
R/W
3
WDReset
0
R/W
2
1
0
SleepEn
WDVal1
WDVal0
0
0
0
Description
Reset the Watchdog
1 -> Resets the Logic Watchdog
0 -> no action
The Read value is always '0'
See Operating modes (sleep)
Watchdog timer data 1/4 ck[1]
Watchdog timer data 1/2 ck[1]
R/W
R
R
4.4 CPU State after Reset
Reset initializes the CPU as shown in Table 4.4.1 below.
Table 4.4.1 Initial CPU value after Reset.
Name
Bits
Program counter 0
12
Program counter 1
12
Program counter 2
12
Stack pointer
2
Index register
7
Carry flag
1
Zero flag
1
Halt
1
Instruction register
16
Periphery registers
4
Symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
Initial Value
$000 (as a result of Jump 0)
Undefined
Undefined
SP[0] selected
Undefined
Undefined
Undefined
0
Jump 0
Reg.....
See peripheral memory map
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EM6620
5. Oscillator and Prescaler
5.1 Oscillator
A built-in crystal oscillator generates the system operating clock for the CPU and peripheral blocks, from an
externally connected crystal (typically 32.768kHz). The oscillator circuit is supplied by the regulated voltage,
Vreg. In sleep mode the oscillator is stopped.
EM’s special design techniques guarantee the low current consumption of this oscillator. The external
impedance between the oscillator pads must be greater than 10 MOhm. Connection of any other components to
the two oscillator pads must be confirmed by EM Microelectronic-Marin SA.
5.2 Prescaler
The prescaler consists of fifteen elements divider chain which delivers clock signals for the peripheral circuits
such as timer/counter, buzzer, LCD voltage multiplier, debouncer and edge detectors, as well as generating
prescaler interrupts. The input to the prescaler is the system clock signal. Power on initializes the prescaler to
Hex(0001).
Table 5.2.1 Prescaler Clock Name Definition
Function
System clock
System clock / 2
System clock / 4
System clock / 8
System clock/ 16
System clock / 32
System clock / 64
System clock / 128
Name
Ck[16]
Ck[15]
Ck[14]
Ck[13]
Ck[12]
Ck[11]
Ck[10]
ck [9]
32 KHz Xtal
32768 Hz
16384 Hz
8192 Hz
4096 Hz
2048 Hz
1024 Hz
512 Hz
256 Hz
Function
System clock / 256
System clock / 512
System clock / 1024
System clock / 2048
System clock / 4096
System clock / 8192
System clock / 16384
System clock / 32768
Table 5.2.2 Control of Prescaler Register RegPresc
Bit
3
2
1
0
Name
PWMOn
ResPresc
PrIntSel
DebSel
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Name
Ck[8]
Ck[7]
Ck[6]
Ck[5]
Ck[4]
Ck[3]
Ck[2]
Ck[1]
32 KHz Xtal
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
Figure 8. Prescaler Frequency Timing
Description
see 10 bit counter
Write Reset prescaler
1 -> Resets the divider chain
from Ck[14] down to
Ck[2], sets Ck[1].
0 -> No action.
Prescaler Reset
System Clock
Ck[16]
Ck[15]
Ck[14]
The Read value is always '0'
Interrupt select.
0 -> Interrupt from Ck[4]
1 -> Interrupt from Ck[6]
Debouncer clock select.
0 -> Debouncer with Ck[8]
1 -> Debouncer with Ck[11]
or Ck[14]
Horizontal Scale Change
Ck[2]
Ck[1]
First positive edge of 1 Hz clock is 1s after
the falling reset edge
With DebSel = 1 one may choose either the Ck[11] or Ck[14] debouncer frequency by selecting the
corresponding metal mask option. Relative to 32kHz the corresponding max. debouncer times are then 2 ms or
0.25 ms. For the metal mask selection refer to chapter 16.1.5.
Switching the PrIntSel may generate an interrupt request. Avoid it with MaskIRQ32/8 = 0 selection during the
switching operation.
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EM6620
The prescaler contains 3 interrupt sources:
- IRQ32/8 ; this is Ck[6] or Ck[4] positive edge interrupt,
the selection is depending on bit PrIntSel.
- IRQHz1 ; this is Ck[1] positive edge interrupt
- IRQBlink ; this is 3/4 of Ck[1] period interrupt
Figure 9. Prescaler Interrupts
Ck[2]
Ck[1]
There is no interrupt generation on reset.
IRQ Hz1
The first IRQHz1 Interrupt occurs 1 sec (32kHz)
after reset.
IRQBlink
A possible application for the IRQBlink is LCD-Display
blinking control together with IRQHz1.
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EM6620
6. Input and Output ports
The EM6620 has:
- one 4-bit input port ( port A )
- one 4-bit input/output port. ( port B )
Pull-up and Pull-down resistors can be added to all this ports with metal and/or register options.
6.1 Ports overview
Table 6.1.1 Input and Output ports overview
Port
Mode
Mask(M:) or Register(R:)
option
Function
PA
Input
M: Pull-up
-Input
M: Pull-down (default)
-Bit-wise interrupt request
R: Pull(up/down) select
-Software test variable
[3:0]
R: Debounced or direct
Bitwise Multi-Function on Ports
PA[3]
conditional jump
input for IRQ request
-PA[3],PA[0] input for the
and Counter
event counter
R: + or - for IRQ-edge
and Counter
R: Input reset
-PA[3] input for the
millisecond counter
-Port A reset inputs
PA[2] PA[1]
10 bit
Event
Counter
-
-
clock
start /
stop of
MSC
PA[0]
10 bit
Event
Counter
clock
-
-
-
combination
PB
bit-wise R: CMOS or
input or
[3:0]
Nch open drain output
output
R: Pull-down on input
R: Pull-up on input
-Input or Output
PB[3]
PB[2] PB[1]
PB[0]
PWM
output
ck[1]
output
ck[16]
output
-PB[3] for the PWM output
-PB[2:0] for the ck[16,12,1]
output
-Tristate output
- PB[0] dynamic input
ck[12]
output
Comp.
input
comparator
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6.2 Port A
The EM6620 has one four bit general purpose CMOS input port. The port A input can be read at any time, pullup or pull-down resistors can be chosen. All selections concerning port A are bit-wise executable. I.e. Pull-up on
PA[2], pull-down on PA[0], positive IRQ edge on PA[0] but negative on PA[1], etc.
In sleep mode the port A inputs are continuously monitored to match the input reset condition which will
immediately wake up the EM6620. The pull-up or pull-down resistors remain active as defined in the option
register.
Figure 10. Input Port A Configuration
NoDebIntPA[n]=1
VBAT
IntEdgPA[n]=0
(VDD )
PA3 for the
Millisecond
Counter
Mask opt
MPAPU[n]
IRQPA[3:0]
PA[n]terminal
PA0, PA3
for 10-bit
Counter
Debouncer
Mask opt
MPAPD[n]
µP TestVar
Ck[8]
Ck[11] or Ck[14]
DB[3:0]
VSS
NoPull[n]
6.2.1 IRQ on Port A
For interrupt request generation (IRQ) one can choose direct or debounced input and positive or negative edge
IRQ triggering. With the debouncer selected ( OPtDebIntPA ) the input must be stable for two rising edges of
the selected debouncer clock (RegPresc). This means a worst case of 16ms(default) or 2ms (0.25ms by metal
mask) with a system clock of 32kHz.
Either a positive or a negative edge on the port A inputs - after debouncer or not - can generate an interrupt
request. This selection is done in the option register OPTIntEdgPA.
All four bits of port A can provide an IRQ, each pin with its own interrupt mask bit in the RegIRQMask1 register.
When an IRQ occurs, inspection of the RegIRQ1, RegIRQ2 and RegIRQ3 registers allow the interrupt to be
identified and treated.
At power on or after any reset the RegIRQMask1 is set to 0, thus disabling any input interrupt. A new interrupt is
only stored with the next active edge after the corresponding interrupt mask is cleared. See also the interrupt
chapter 9.
It is recommended to mask the port A IRQ’s while one changes the selected IRQ edge. Else one may generate
a IRQ (Software IRQ). I.e. PA[0] on ‘0’ then changing from positive to negative edge selection on PA[0] will
immediately trigger an IRQPA[0] if the IRQ was not masked.
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6.2.2 Pull-up/down
Each of the input port terminals PA[3:0] has a resistor integrated which can be used either as pull-up or pulldown resistor, depending on the selected metal mask options. The pull resistor can be inhibited using the
NoPullPA[n] bits in the register OptNoPullPA. Refer also to chapter 16.1.1 .
Table 6.2.1. Pull-up or Pull-down Resistor on Port A select
Option mask
Option mask
NoPullPA[n]
pull-up
pull-down
value
MPAPU[n]
MPAPD[n]
no
no
x
no
yes
0
no
yes
1
yes
no
0
yes
no
1
yes
yes
x
Action
with
n=0…3
no pull-up, no pull-down
no pull-up, pull-down
no pull-up, no pull-down
pull-up, no pull-down
no pull-up , no pull-down
not allowed*
* only pull-up or pull-down may be chosen on any port A terminal (one choice is excluding the other)
Any port A input must never be left open (high impedance state, not connected, etc. ) unless the internal pull
resistor is in place (mask option) and switched on (register selection). Any open input may draw a significant
cross current which adds to the total chip consumption.
6.2.3 Software test variables
The port A terminals PA[2:0] are also used as input conditions for conditional software branches. Independent
of the OPtDebIntPA and the OPTIntEdgPA. These CPU inputs are always debounced and non-inverted.
- debounced PA[0] is connected to CPU TestVar1
- debounced PA[1] is connected to CPU TestVar2
- debounced PA[2] is connected to CPU TestVar3
6.2.4 Port A for 10-Bit Counter and MSC
The PA[0] and PA[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count" mode.
As for the IRQ generation one can choose debouncer or direct input with the register OPTDebIntPA and noninverted or inverted input with the register OPTIntEdgPA. Debouncer input is always recommended.
Pad input PA[3] is also used as start/stop control for the millisecond counter. This control signal is derived from
PA[3], it is independent of the port A debouncer and edge selection. Refer also to Figure 10.
6.3 Port A registers
Table 6.3.1 Register RegPA
Bit
Name
Reset
3
PA[3]
2
PA[2]
1
PA[1]
0
PA[0]
* Direct read on Port A terminals
R/W
R*
R*
R*
R*
Description
PA[3] input status
PA[2] input status
PA[1] input status
PA[0] input status
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Table 6.3.2 Register RegIRQMask1
Bit
Name
3
MaskIRQPA[3]
2
MaskIRQPA[2]
1
MaskIRQPA[1]
0
MaskIRQPA[0]
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Interrupt mask for PA[3] input
Interrupt mask for PA[2] input
Interrupt mask for PA[1] input
Interrupt mask for PA[0] input
Default "0" is: interrupt request masked, no new request stored
Table 6.3.3 Register RegIRQ1
Bit
Name
Reset
R/W
Description
3
IRQPA[3]
0
R/W*
Interrupt request on PA[3]
2
IRQPA[2]
0
R/W*
Interrupt request on PA[2]
1
IRQPA[1]
0
R/W*
Interrupt request on PA[1]
0
IRQPA[0]
0
R/W*
Interrupt request on PA[0]
W*; Write "1" clears the bit, write "0" has no action, Default "0" is: No Interrupt request
Table 6.3.4 Register OPTIntEdgPA
Bit
Name
power on
value
3
IntEdgPA[3]
0
2
IntEdgPA[2]
0
1
IntEdgPA[1]
0
0
IntEdgPA[0]
0
Default "0" is: Positive edge selection
R/W
Description
R/W
R/W
R/W
R/W
Interrupt edge select for PA[3]
Interrupt edge select for PA[2]
Interrupt edge select for PA[1]
Interrupt edge select for PA[0]
Table 6.3.5 Register OPTDebIntPA
Bit
Name
power on
R/W
value
3
NoDebIntPA[3]
0
R/W
2
NoDebIntPA[2]
0
R/W
1
NoDebIntPA[1]
0
R/W
0
NoDebIntPA[0]
0
R/W
Default "0" is: Debounced inputs for interrupt generation
Table 6.3. Register OPTNoPullPA
Bit
Name
power on
value
3
NoPullPA[3]
0
2
NoPullPA[2]
0
1
NoPullPA[1]
0
0
NoPullPA[0]
0
Default "0" is depending on mask selection.
Description
Interrupt debounced for PA[3]
Interrupt debounced for PA[2]
Interrupt debounced for PA[1]
Interrupt debounced for PA[0]
R/W
Description
R/W
R/W
R/W
R/W
Pull-up/down selection on PA[3]
Pull-up/down selection on PA[2]
Pull-up/down selection on PA[1]
Pull-up/down selection on PA[0]
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EM6620
6.4 Port B
The EM6620 has one four bit general purpose I/O port. Each bit can be configured individually by software for
input/output, pull-up, pull-down and CMOS or Nch. open drain output type. The port outputs either data,
frequency or PWM signals.
6.4.1 Input / Output Mode
Each port B terminal is bit-wise bi-directional. The input or output mode on each port B terminal is set by writing
the corresponding bit in the RegPBCntl control register. To set for input (default), 0 is written to the
corresponding bit of the RegPBCntl register which results in a high impedance state for the output driver. The
output mode is set by writing 1 in the control register, and consequently the output terminal follows the status of
the bits in the RegPBData register.
The port B terminal status can be read on address RegPBData even in output mode. Be aware that the data
read on port B is not necessary of the same value as the data stored on RegPBData register.
See also Figure 11 for details.
While the dynamic input comparator is selected (PB0CompSel =‘1’) the PPB[0] input is cut off, a read on port B
PPB[0] returns ‘1’.
Figure 11. Port B Architecture
Pull-down
Option Register
Internal Data Bus
Open Drain Option
Register
Pd[n]
OD[n]
Port B Direction Reg
DDR[n]
SLEEP
Port B
Control
PortB Data Reg
DR[n]
Mask Option
MPBPD[n]
MUX
Multiplexed
Outputs are:
PWM, CK[16],
CK[11], CK[1]
Active Pull-up if
Open Drain
Mode
PB[n]
I / O Terminal
Multiplexed
Output
Mask Option
MPBPD[n]
Multiplexed
Output Active
4
RD
Active
Pull-down
DB[n]
RD for PB[3:1]
PB0CompSelect for PB[0]
1
Dynamic Input
Comparator
PB0CompEnable
IRQPB0Comp
PB0CompResult
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6.4.2 Pull-up/Down
For each terminal of PB[3:0] an internal input pull-up (metal mask MPBPU[n]) or pull-down (metal mask
MPBPD[n]) resistor can be connected per metal mask option. Per default the two resistors are in place. In this
case one can chose per software to have either a pull-up, a pull-down or no resistor. See below.
For Metal mask selection and available resistor values refer to chapter 16.1.2.
Pull-down ON : MPBPD[n] must be in place ,
AND the bit NoPdPB[n] must be ‘0’ .
Pull-down OFF: MPBPD[n] is not in place,
OR if MPBPD[n] is in place NoPdPB[n] = ‘1’ cuts off the pull-down.
OR selecting NchOpDPB[n] = ‘1’ cuts off the pull-down.
Pull-up ON *
: MPBPU[n] must be in place,
AND the bit NchOpDPB[n] must be ‘1’ ,
AND the bit PBIOCntl[n] = ‘0’ (input mode) OR if PBIOCntl[n] = ‘1’ while PBData[n] = 1.
Pull-up OFF*
: MPBPU[n] is not in place,
OR if MPBPU[n] is in place NchOpDPB[n] = ‘0’ cuts off the pull-up,
OR if MPBPU[n] is in place and if NchOpDPB[n] = ‘1’ then PBData[n] = 0 cuts off the pull-up.
Never can pull-up and pull-down be active at the same time.
For POWER SAVING one can switch off the port B pull resistors between two read phases. No cross current
flows in the input amplifier while the port B is not read. The recommended order is :
• switch on the pull resistor.
• allow sufficient time - RC constant - for the pull resistor to drive the line to either VSS or VDD.
• Read the port B
• Switch off the pull resistor
Minimum time with current on the pull resistor is 4 periods of the system clock, if the RC constant is lower than
1 system clock period. Adding a NOP before reading moves the number of periods with current in the pull
resistor to 6 and the maximum RC delay to 3 clock periods.
6.4.3 CMOS / NCH. Open Drain Output
The port B outputs can be configured as either CMOS or Nch. open drain outputs. In CMOS both logic ‘1’ and
‘0’ are driven out on the terminal. In Nch. open drain only the logic ‘0’ is driven out on the terminal, the logic ‘1’
value is defined by the internal pull-up resistor (if implemented) or high impedance.
If using the Dynamic Input Comparator one must put the PB[0] in CMOS input mode and should not use any pull
resistor on this terminal. If not doing so the device may draw excessive current.
Figure 12. CMOS or Open Drain outputs
N c h . O p e n D ra in O u tp u t
C M O S O u tp u t
A c tiv e P u llu p
fo r H ig h S ta te
MUX
D R [n ]
F re q u e n c y
O u tp u ts
1
D a ta
I / O
T e rm in a l
P B [n ]
T ri-S ta te O u tp u t
B u ffe r : c lo s e d
MUX
I / O
T e rm in a l
D R [n ]
F re q u e n c y
O u tp u ts
T ri-S ta te O u tp u t
B u ffe r : H ig h
Im p e d a n c e fo r
D a ta = 1
P B [n ]
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6.4.4 PWM and Frequency output
PB[3] can also be used to output the PWM (Pulse Width Modulation) signal from the 10-Bit Counter, the
Ck[16], Ck[11] as well as the Ck[1] prescaler frequencies.
-Selecting ck[16]
-Selecting ck[11]
-Selecting ck[1 ]
-Selecting PWM
output on PB[0] with bit PB32kHzOut in register OPTSelPB
output on PB[1] with bit PB2kHzOut in register OPTSelPB
output on PB[2] with bit PB1HzOut in register OPTSelPB
output on PB[3] with bit PWMOn
in register RegPresc.
6.5 PB[0] Dynamic Input Comparator
The EM6620 has one dynamic input comparator on PB[0], such that PB[0] input voltage level is compared at
regular intervals (ck[12] clock period) with the SVLD detection level (default : 2.0V).
To select this function, the bit PB0CompSelect in register RegPB0Comp must be set to “1. If using the
Dynamic Input Comparator one must put the PB[0] in CMOS input mode and should not use any pull resistor on
this terminal.
The Comparator shares the same internal block as the SVLD function, so one can only use one or the other
function at the same time. With bit PB0CompSelect set to ‘1’ the Comparator is chosen, ‘0’ selects the SVLD.
Setting the bit PB0CompEnable to “1“ enables the measurements.
The worst case first measurement time is :
ck[9] clock period + ck[14] clock period (synchronization + effective measurement)
(32kHz -> 4.125ms)
The time between two consecutive effective measurements is equal to 3 ck[14] clock periods. The
measurement stops at the end of the next measurement cycle after PB0CompEnable is cleared. At the end of
each measurement, the result is stored in PB0CompResult bit. At any time during the measurement
PB0CompResult bit can be read : If the result is
- “0“, the input level is greater than the detection level
- “1“, the input level is lower than the detection level.
An interrupt request IRQPB0Comp is generated on each result change except after the first measurement. This
interrupt request can be masked (default) (MaskIRQPB0Comp bit). See section 9 for more information about
the interrupt handling. See also section Supply Voltage Level Detector on page 33.
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6.6 Port B registers
Table 6.6.1 Register RegPBData
Bit
Name
3
PBData[3]
2
PBData[2]
1
PBData[1]
0
PBData[0]
Reset
-
R/W
R* /W
R* /W
R* /W
R* /W
Description
PB[3] input and output
PB[2] input and output
PB[1] input and output
PB[0] input and output
R* : Direct read on port B terminal (not the internal register read).
Table 6.6.2 Register RegPBCntl
Bit
Name
Reset
3
PBIOCntl[3]
0
2
PBIOCntl[2]
0
1
PBIOCntl[1]
0
0
PBIOCntl[0]
0
Default "0" is: PortB in input mode
R/W
R/W
R/W
R/W
R/W
Description
I/O control for PB[3]
I/O control for PB[2]
I/O control for PB[1]
I/O control for PB[0]
Table 6.6.3 Register RegPB0Comp
Bit
Name
Reset
R/W
3
---2
PB0CompResult
0
R
1
PB0CompEnable
0
R/W
0
PB0CompSelect
0
R/W
Default "0" is: Power supply voltage level detection
Description
Comparator result flag
Comparator measurements enable
Dynamic input Comparator function
Table 6.6.4 register OPTFSelPB
Bit
Name
power on
R/W
Description
value
3
PB1HzOut
0
R/W
Ck[1] output on PB[2]
2
PB2kHzOut
0
R/W
Ck[12] output on PB[1]
1
PB32kHzOut
0
R/W
Ck[16] output on PB[0]
0
NoInputRes
0
R/W
No Input Reset From Port A
Default "0" is: No frequency output, Port A can reset the EM6620.
Table 6.6.5 option register OPTNoPdPB
Bit
Name
power on
value
3
NoPdPB[3]
0
2
NoPdPB[2]
0
1
NoPdPB[1]
0
0
NoPdPB[0]
0
Default "0" is: Pull-down on
Table 6.6.6 option register OPTNchOpDPB
Bit
Name
power on
value
3
NchOpDPB[3]
0
2
NchOpDPB[2]
0
1
NchOpDPB[1]
0
0
NchOpDPB[0]
0
Default "0" is: CMOS on PB[3..0]
R/W
Description
R/W
R/W
R/W
R/W
No pull-down on PB[3]
No pull-down on PB[2]
No pull-down on PB[1]
No pull-down on PB[0]
R/W
Description
R/W
R/W
R/W
R/W
Nch. Open Drain on PB[3]
Nch. Open Drain on PB[2]
Nch. Open Drain on PB[1]
Nch. Open Drain on PB[0]
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7. 10-bit Counter
The EM6620 has a built-in universal cyclic counter. It can be configured as 10, 8, 6 or 4-bit counter. If 10-bits
are selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting.
The counter works in up- or down count mode. Eight clocks can be used as the input clock source, six of them
are prescaler frequencies and two are coming from the input pads PA[0] and PA[3]. In this case the counter can
be used as an event counter.
The counter generates an interrupt request IRQCount0 every time it reaches 0 in down count mode or 3FF in
up count mode. Another interrupt request IRQCntComp is generated in compare mode whenever the counter
value matches the compare data register value. Each of this interrupt requests can be masked (default). See
section 9 for more information about the interrupt handling.
A 10-bit data register CReg[9:0] is used to initialize the counter at a specific value (load into Count[9:0]). This
data register (CReg[9:0]) is also used to compare its value against Count[9:0] for equivalence.
A Pulse-Width-Modulation signal (PWM) can be generated and output on port B terminal PB[3].
Figure 13. 10-bit Counter Block Diagram
PA[0]
Ck[15]
Ck[12]
Ck[10]
Ck[8]
Ck[4]
Ck[1]
PA[3]
En
IRQCntComp
Comparator
ck
PWM
MUX
ck
Up/Down
En
IRQCount0
Up/Down Counter
EvCount
RegCCntl1, 2
RegCDataL, M, H
(Count[9:0])
Load
Counter Read Register
CountFSel2...0
Up/Down
Start
EvCount
Load
RegCDataL, M, H (CReg[9:0])
Data Register
EnComp
DB[3:0]
7.1 Full and Limited Bit Counting
Table 6.6.1. Counter length selection
In Full Bit Counting mode the counter uses its maximum
BitSel[1]
BitSel[0 ]
counter length
of 10-bits length (default ). With the BitSel[1,0] bits in
0
0
10-Bit
register RegCDataH one can lower the counter length,
0
1
8-Bit
for IRQ generation, to 8, 6 or 4 bits. This means that
1
0
6-Bit
actually the counter always uses all the 10-bits, but
1
1
4-Bit
IRQCount0 generation is only performed on the number
of selected bits. The unused counter bits may or may not
be taken into account for the IRQComp generation depending on bit SelIntFull. Refer to chapter 7.4.
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7.2 Frequency Select and Up/Down Counting
8 different input clocks can be selected to drive the Counter. The selection is done with bits CountFSel2…0 in
register RegCCntl1. 6 of this input clocks are coming from the prescaler. The maximum prescaler clock
frequency for the counter is half the system clock and the lowest is 1Hz. Therefore a complete counter roll over
can take as much as 17.07 minutes (1Hz clock, 10 bit length) or as little as 977 µs (Ck[15], 4 bit length). The
IRQCount0, generated at each roll over, can be used for time bases, measurements length definitions, input
polling, wake up from Halt mode, etc. The IRQCount0 and IRQComp are generated with the system clock
Ck[16] rising edge. IRQCount0 condition in up count mode is : reaching 3FF if 10-bit counter length (or FF, 3F,
F in 8, 6, 4-bit counter length). In down count mode the condition is reaching ‘0’. The non-selected bits are ‘don’t
care’. For IRQComp refer to section 7.4.
Note: The Prescaler and the Microprocessor clock’s are usually non-synchronous, therefore time bases
generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down mode).
However the prescaler clock can be synchronized with µP commands using for instance the prescaler reset
function.
Figure 14. Counter Clock Timing
P re s c a le r F re q u e n c ie s o r D e b o u n c e d P o rt A C lo c k s
S y s te m C lo c k
P re s c a le r C lo c k
C o u n tin g
C o u n te r IR Q ’s
N o n -D e b o u n c e d P o r t A C lo c k s (S y s te m C lo c k In d e p e n d e n t)
S y s te m C lo c k
P o rt A C lo c k
D iv id e d C lo c k
C o u n tin g
C o u n te r IR Q ’s
The two remaining clock sources are coming from the PA[0] or PA[3] terminals. Refer to the Figure 10 on page
14 for details. Both sources can be either debounced (Ck[11] or Ck[8]) or direct inputs, the input polarity can
also be chosen. The output after the debouncer polarity selector is named PA3 , PA0 respectively. For the
debouncer and input polarity selection refer to chapter 6.2.
In the case of port A input clock without debouncer, the counting clock frequency will be half the input clock on
port A. The counter advances on every odd numbered port A negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA3 or PA0 input clock edge. In this condition the
EM6621 is able to count with a higher clock rate as the internal system clock (Hi-Frequency Input). Maximum
port A input frequency is limited to 200kHz (@VDD ≥ 1.5 V). If higher frequencies are needed, please contact
EM-Marin.
In both, up or down count (default) mode, the counter is cyclic. The counting direction is chosen in register
RegCCntl1 bit Up/Down (default ‘0’ is down count). The counter increases or decreases its value with each
positive clock edge of the selected input clock source. Start up synchronization is necessary because one can
not always know the clock status when enabling the counter. With EvCount=0, the counter will only start on the
next positive clock edge after a previously latched negative edge, while the Start bit was already set to ‘1’. This
synchronization is done differently if event count mode (bit EvCount) is chosen. Refer also to Figure 15.
Internal Clock Synchronization.
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7.3 Event Counting
The counter can be used in a special event count mode where a certain number of events (clocks) on the PA[0]
or PA[3] input are counted. In this mode the counting will start directly on the next active clock edge on the
selected port A input.
The Event Count mode is switched on by setting bit EvCount in the register RegCCntl2 to ‘1’.PA[3] and PA[0]
inputs can be inverted depending on register OPTIntEdgPA and should be debounced. The debouncer is
switched on in register OPTDebIntPA bits NoDebIntPA[3,0]=0. Its frequency depends on the bit DebSel from
register RegPresc setting. The inversion of the internal clock signal derived from PA[3] or PA[0] is active with
IntEdgPA[3] respectively IntEdgPA[0] equal to 1. Refer also to Figure 10 for internal clock signal generation.
Figure 15. Internal Clock Synchronization
Ck
Ck
Start
Start
Count[9:0]
+/-1
Count[9:0]
EvCount = 0
+/-1
Ck
Ck
Start
Start
Count[9:0]
Count[9:0]
EvCount = 0
EvCount = 1
+/-1
EvCount = 1
7.4 Compare Function
A previously loaded register value (CReg[9:0]) can be compared against the actual counter value (Count[9:0]).
If the two are matching (equality) then an interrupt (IRQComp) is generated. The compare function is switched
on with the bit EnComp in the register RegCCntl2. With EnComp = 0 no IRQComp is generated. Starting the
counter with the same value as the compare register is possible, no IRQ is generated on start. Full or Limited
bit compare are possible, defined by bit SelIntFull in register RegSysCntl1.
EnComp must be written after a load operation (Load = 1). Every load operation resets the bit EnComp.
Full bit compare function.
Bit SelIntFull is set to ‘1’. The function behaves as described above independent of the selected counter length.
Limited bit counting together with full bit compare can be used to generate a certain amount of IRQCount0
interrupts until the counter generates the IRQComp interrupt. With PWMOn=‘1’ the counter would have
automatically stopped after the IRQComp, with PWMOn=‘0’ it will continue until the software stops it. EnComp
must be cleared before setting SelIntFull and before starting the counter again. Be careful, PWMOn also
redefines the port B PB[3] output data.(refer to section 7.5).
Limited bit compare
With the bit SelIntFull set to ‘0’ (default) the compare function will only take as many bits into account as
defined by the counter length selection BitSel[1:0] (see chapter 7.1).
7.5 Pulse Width Modulation (PWM)
The PWM generator uses the behavior of the Compare function (see above) so EnComp must be set to
activate the PWM function.. At each Roll Over or Compare Match the PWM state - which is output on port B
PB[3] - will toggle. The start value on PB[3] is forced while EnComp is 0 the value is depending on the up or
down count mode. Every counter value load operation resets the bit EnComp and therefore the PWM start
value is reinstalled.
Setting PWMOn to ‘1’ in register RegPresc routes the counter PWM output to port B terminal PB[3]. Insure that
PB[3] is set to output mode . Refer to section 6.4 for the port B setup.
The PWM signal generation is independent of the limited or full bit compare selection bit SelIntFull. However if
SelIntFull = 1 (FULL) and the counter compare function is limited to lower than 10 bits one can generate a
predefined number of output pulses. In this case, the number of output pulses is defined by the value of the
unused counter bits. It will count from the start value until the IRQComp match.
One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit
compare) in down count mode.
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For instance, loading the counter in up count mode with hex 000 and the comparator with hex C52 which will
be identified as :
- bits[11:10] are limiting the counter to limits to 4 bits length, =03
- bits [9:4] are the unused counter bits = hex 05 (bin 000101),
- bits [3:0] (comparator value = 2).
(BitSel[1,0])
(number of PWM pulses)
(length of PWM pulse)
Thus after 5 PWM-pulses of 2 clocks cycles length the Counter generates an IRQComp and stops.
The same example with SelIntFull=0 (limited bit compare) will produce an unlimited number of PWM at a length
of 2 clock cycles.
7.5.1 How the PWM Generator works.
For Up Count Mode; Setting the counter in up count and PWM mode the PB[3] PWM output is defined to be 0
(EnComp=0 forces the PWM output to 0 in upcount mode, 1 in downcount). Each Roll Over will set the output
to ‘1’ and each Compare Match will set it back to ‘0’. The Compare Match for PWM always only works on the
defined counter length. This, independent of the SelIntFull setting which is valid only for the IRQ generation.
Refer also to the compare setup in chapter 7.4.
In above example the PWM starts counting up on hex 0,
2 cycles later compare match -> PWM to ‘0’,
14 cycles later roll over -> PWM to ‘1’
2 cycles later compare match -> PWM to ‘0’ , etc. until the completion of the 5 pulses.
The normal IRQ generation remains on during PWM output. If no IRQ’s are wanted, the corresponding masks
need to be set.
Figure 16. PWM Output in Up Count Mode
Figure 17. PWM Output in Down Count Mode
Clock
Clock
Count[9 :0] 03E
03F
000
001
...
Data-1
Data
Roll-over
Compare
IRQCount0
Data+1
Data+2
Count[9 :0] 001
000
3FF
3FE
...
Data+1
Data
Data-1
Data-2
Roll-over
Compare
IRQCount0
IRQComp
IRQComp
PWM output
PWM output
In Down Count Mode everything is inverted. The
PWM output starts with the ‘1’ value. Each Roll Over will set the output to ‘0’ and each Compare Match will set it
back to ‘1’. For limited pulse generation one must load the complementary pulse number value. I.e. for 5 pulses
counting on 4 bits load bits[9 :4] with hex 3A (bin 111010).
7.5.2 PWM Characteristics
PWM resolution is
: 10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps)
the minimal signal period is
: 16 (4-bit) x Fmax*
-> 16 x 1/Ck[15]
-> 977 µs
(32 KHz)
the maximum signal period is : 1024 x Fmin*
-> 1024 x 1/Ck[1]
-> 1024 s
(32 KHz)
the minimal pulse width is
: 1 bit
-> 1 x 1/Ck[15]
-> 61 µs
(32 KHz)
* This values are for Fmax or Fmin derived from the internal system clock (32kHz). Much shorter (and longer)
PWM pulses can be achieved by using the port A as frequency input.
One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit
compare) in downcount mode.
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7.6 Counter Setup
RegCDataL[3:0], RegCDataM[3:0], RegCDataH[1:0] are used to store the initial count value called
CReg[9:0] which is written into the count register bits Count[9:0] when writing the bit Load to ‘1’ in RegCCntl2.
This bit is automatically reset thereafter. The counter value Count[9:0] can be read out at any time, except
when using non-debounced high frequency port A input clock. To maintain data integrity the lower nibble
Count[3:0] must always be read first. The ShCount[9:4] values are shadow registers to the counter. To keep
the data integrity during a counter read operation (3 reads), the counter values [9:4] are copied into these
registers with the read of the count[3:0] register. If using non-debounced high frequency port A input the counter
must be stopped while reading the Count[3:0] value to maintain the data integrity.
In down count mode an interrupt request IRQCount0 is generated when the counter reaches 0. In up count
mode, an interrupt request is generated when the counter reaches 3FF (or FF,3F,F if limited bit counting).
Never an interrupt request is generated by loading a value into the counter register.
When the counter is programmed from up into down mode or vice versa, the counter value Count[9:0] gets
inverted. As a consequence, the initial value of the counter must be programmed after the Up/Down selection.
Loading the counter with hex 000 is equivalent to writing stop mode, the Start bit is reset, no interrupt request is
generated.
How to use the counter;
If PWM output is required one has to put the port B[3] in output mode and set PWMOn=1 in step 5.
1st,
set the counter into stop mode (Start=0).
2nd,
select the frequency and up- or down count mode in RegCCntl1.
3rd,
write the data registers RegCDataL, RegCDataM, RegCDataH (counter start value and length)
4th,
load the counter, Load=1, and choose the mode. (EvCount, EnComp=0)
5th,
select bits PWMOn in RegPresc and SelIntFull in RegSysCntl1
6th,
if compare mode desired , then write RegCDataL, RegCDataM, RegCDataH (compare value)
7th,
set bit Start and select EnComp in RegCCntl2
7.7 10-bit Counter Registers
Table 7.7.1 Register RegCCntl1
Bit
Name
Reset
R/W
3
Up/Down
0
R/W
2
CountFSel2
0
R/W
1
CountFSel1
0
R/W
0
CountFsel0
0
R/W
Default : PA0 ,selected as input clock, Down counting
Table 7.7.2 Counter Input Frequency Selection with CountFSel[2..0]
CountFSel2
CountFSel1
CountFSel0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Description
Up or down counting
Input clock selection
Input clock selection
Input clock selection
clock source selection
Port A PA[0]
Prescaler Ck[15]
Prescaler Ck[12]
Prescaler Ck[10]
Prescaler Ck[8]
Prescaler Ck[4]
Prescaler Ck[1]
Port A PA[3]
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Table 7.7.3 Register RegCCntl2
Bit
Name
Reset
R/W
Description
3
Start
0
R/W
Start/Stop control
2
EvCount
0
R/W
Event counter enable
1
EnComp
0
R/W
Enable comparator
0
Load
0
R/W
Write: load counter register;
Read: always 0
Default : Stop, no event count, no comparator, no load
Table 7.7.4 Register RegSysCntl1
Bit
Name
Reset
3
IntEn
0
2
SLEEP
0
1
SelIntFull
0
0
ChTmDis
0
Default : Interrupt on limited bit compare
R/W
R/W
R/W
R/W
R/W
Description
General interrupt enable
Sleep mode
Compare Interrupt select
For EM test only
Table 7.7.5 Register RegCDataL, Counter/Compare Low Data Nibble
Bit
Name
Reset
R/W
3
CReg[3]
0
W
2
CReg[2]
0
W
1
CReg[1]
0
W
0
CReg[0]
0
W
3
Count[3]
0
R
2
Count[2]
0
R
1
Count[1]
0
R
0
Count[0]
0
R
Description
Counter data bit 3
Counter data bit 2
Counter data bit 1
Counter data bit 0
Data register bit 3
Data register bit 2
Data register bit 1
Data register bit 0
Table 7.7.6 Register RegCDataM, Counter/Compare Middle Data Nibble
Bit
Name
Reset
R/W
3
CReg[7]
0
W
2
CReg[6]
0
W
1
CReg[5]
0
W
0
CReg[4]
0
W
3
ShCount[7]
0
R
2
ShCount[6]
0
R
1
ShCount[5]
0
R
0
ShCount[4]
0
R
Description
Counter data bit 7
Counter data bit 6
Counter data bit 5
Counter data bit 4
Data register bit 7
Data register bit 6
Data register bit 5
Data register bit 4
Table 7.7.7 Register RegCDataH, Counter/Compare High Data Nibble
Bit
Name
Reset
R/W
Description
3
BitSel[1]
0
R/W
Bit select for limited bit count/compare
2
BitSel[0]
0
R/W
Bit select for limited bit count/compare
1
CReg[9]
0
W
Counter data bit 9
0
CReg[8]
0
W
Counter data bit 8
1
ShCount[9]
0
R
Data register bit 9
0
ShCount[8]
0
R
Data register bit 8
Table 7.7.8 Counter Length Selection
BitSel[1]
BitSel[0 ]
counter length
0
0
10-Bit
0
1
8-Bit
1
0
6-Bit
1
1
4-Bit
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8. Millisecond Counter
The EM6620 has a built-in millisecond binary coded decimal counter. It can be used to measure the time
elapsed between two events (hardware or software events). With a system clock of 32kHz, the counter
generates every 1/10 second or every second an interrupt request.
The counter value read on registers RegMSCDataL, RegMSCDataM and RegMSCDataH is in binary coded
decimal format (000 to 999). To maintain the data integrity for the 3 decimal digits inside BCD[11:0] one must
stop the counter while reading the full 3 digit value.
An overflow flag FlSec is set whenever the counter reached 999. This flag is helpful when the counter is used in
polling mode and twice the same value is read. In this case, if the flag is set to 1, it indicates that the two
readings were 1 second apart, in the case the flag is not set, the two readings must have been very short one
after the other. After every read of RegMSCCntl2 the FlSec gets automatically reset.
The millisecond counter is reset with every system reset. Setting the ResMSC flag located in register
RegMSCCntl1 resets the counter value only. This flag is automatically reset after the write operation. For good
resolution in Pa3-mode use the Ck[14 ] debouncer clock (250us). Or if the 1/1000 sec is not relevant then
choose Ck[10] (4ms) as debouncer clock. Doing so will save power. The debouncer selection is made in
register RegMSCCntl2 bit DebFreqSel.
Figure 18. MSC Block Diagram
This signal used
as reference in
text description
PA[3]
Term inal
RegMSCCntl1,2
Ck[14
0
Ck[10]
1
PA3
Debouncer
PosEdg
NegEdg
1
PA3Internal
0
Start/Stop
Control
dT/MSC
PA3Edge
DebFreqSel
Data
4
Data
BCD
1/10
Sec
BCD
1/100
Sec
1/10 Sec
1 Sec
PA3/uP
EN
Data Bus
FlSecl
RunEn
dT/MSC
Data
BCD
1/1000
Sec
CK1000
0
IRQMSC
1
IntSel
Changing PA3Edge while RunEn=1 or PA3/up=1 may generate a MSC event (start or stop). This behavior is
useful for the - CPU controlled start and PA3 controlled stop - mode, But in general one does all the setup
before starting the counter.
8.1 PA[3] Input for MSC
In hardware Start/Stop mode the counter is triggered with the port A terminal PA[3] input. In this case PA[3] is
debounced with the prescaler Ck[14] (or Ck[10]) clock. The triggering edge selection is made with bit PA3Edge
in register RegMSCCntl2 (default negative edge). The PA[3] input for the millisecond counter is totally
independent of the PA[3] interrupt edge selection and the PA[3] polarity selection for the 10 bit counter.
However the pull-up or pull-down selection is common to all peripheries sharing the port A.
8.2 IRQ from MSC
An Interrupt request IRQMSC is send on either every 1/10 seconds or every second, depending on the bit
IntSel in register RegMSCCntl2. For interrupt handling please refer to the interrupt control section.
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8.3 MSC-Modes
The millisecond counter can have many different modes of operation. The most common are :
- CPU controlled start and stop.
- CPU controlled start and PA[3] controlled stop.
- Port A terminal PA[3] controlled start and stop mode.
- Pulse width measurement of port A terminal PA[3] input signals.
All these different modes are controlled with the bits in the registers RegMSCCntl1 and RegMSCCntl2.
The main bits are :
- dT/MSC ;
Pulse-width or start stop measure. This bit only has a action if PA[3] input is chosen. If pulsewidth measure is selected, the counter starts with the first active edge on PA[3] and stops with
the next inverse edge (sets RunEn = 0). If MSC measure selected, the counter starts with the
first active PA[3] edge, stops on the next, restarts on the following etc. It does not reset RunEn.
- PA3/µP ;
Direct port A terminal PA[3] or CPU (µP) controlled start and stop function. If direct PA[3]
controlled start stop mode is chosen the counter, once enabled by setting RunEn/Stop = 1,
starts counting on the first active edge seen on PA[3]. It stops counting depending on the
dT/MSC bit either on the next inverse edge or on the next active edge. If µP is chosen, the
counter starts and stops depending on bit RunEn/Stop.
- RunEn/Stop; In CPU mode this bit starts or stops the counter. In PA3 mode it enables the counter which will
start with the next event on port A terminal PA[3]. If dT and PA3 mode, the RunEn gets reset
with the second active PA[3] edge.
- PA3Edge ;
This bit selects the active PA[3] edge which will trigger the dT/MSC selected measurement
mode. It has no effect if PA3/µP=0. Default 0 is negative edge.
8.4 Mode selection
Before using, the MSC counter needs to be reset by setting bit ResMSC to ‘1’. This bit is automatically reset
thereafter. Then select the IRQ frequency and the counting mode. Now the RunEn can be set to ‘1’ . To display
the counter value during run you may only want to read the MSB (1/10 sec) digit ,driven by IRQ or with polling,
and fully read the MSC value only once the counter is stopped. The counter data registers are read only. Any
Reset (system reset, POR, watchdog) is setting the MSC into stop mode and clears the counter registers.
• CPU controlled Start and Stop
As soon as the CPU writes the start bit RunEn/Stop=1 the counter starts up counting until the CPU clears the
start bit. The bit PA3/uP is ‘0’ for this mode.
Figure 19. CPU controlled Start Stop
CPU write
RunEn/Stop
Start
Counter
Stop
Counting
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• CPU controlled Start and PA[3] controlled Stop.
In this mode setting the bit RunEn=1 while PA3/uP=0 while immediately start the counting action. Afterwards
one needs to prepare for the stop by PA[3]. Therefore the PA[3] start condition must first be fulfilled. This is in
dT mode a rising edge on the PA3internal signal (PA3internal, refer to Figure 18). In MSC mode the start
condition is a positive pulse on PA3internal signal. The creation of this edge or pulse is done per software by
manipulating the PA3Edge selection. See Figure 20 for details. Afterwards one can change to PA3 controlled
stop mode (PA3/uP=1) where the next positive edge on PA3internal will stop the Counter. In dT mode the
RunEn/stop bit will be cleared with the PA3 stop condition where as in MSC mode MSC mode the RunEn is
not cleared.
Figure 20. CPU controlled Start PA[3] controlled Stop
d T / M S C = 1 , S t o p o n P A [ 3 ] F a llin g E d g e
d T /M S C = 1 , S to p o n P A [3 ] R is in g E d g e
C P U W r ite
C P U W r it e
R u n E n /S to p
R u n E n /S to p
P A 3 /u P
P A 3 /u P
P A [3 ]
P A [3 ]
PA3Edge
PA3Edge
P A 3 In te rn a l
P A 3 In te r n a l
C o u n t in g
C ount
S ta r t
µP
S ta r t
PA3
C o u n tin g
C ount
S to p
Set
I n it ia l
V a lu e s
S ta rt
µP
d T /M S C = 0 , S to p o n P A [3 ] R is in g E d g e
C P U W r it e
R u n E n /S to p
R u n E n /S to p
P A 3 /u P
P A 3 /u P
P A [3 ]
P A [3 ]
PA3Edge
PA3Edge
P A 3 In te rn a l
P A 3 In te r n a l
C o u n tin g
S ta r t
µP
S ta rt
PA3
Set
I n it ia l
V a lu e s
C o u n tin g
C ount
S to p
S to p
d T / M S C = 0 , S t o p o n P A [ 3 ] F a llin g E d g e
C P U W r ite
C ount
S ta r t
PA3
Set
I n it ia l
V a lu e s
S ta r t
µP
• Pulse-width measurement of PA[3] Input Signals.
In this mode the bit dT/MSC=1 and PA3/uP=1. Setting
RunEn/stop=1 enables the operation. The first positive
edge on PA3Internal signal will start the counter, the
following negative edge will stop the counter end set bit
RunEn/Stop to 0 . PA3internal signal is a copy of the PA[3]
terminal status if PA3Edge=1. with PA3Edge=0
PA3Internal has the inverted PA[3] value. See also Figure
18 and Figure 21.
• Port A PA[3] controlled Start and Stop Mode.
In this mode the bit dT/MSC=0 and PA3/uP=1. Setting
RunEn/stop=1 enables the operation. The first positive
edge on PA3Internal signal will start the counter , the
second edge will stop the counter, the third one will restart,
etc, . PA3internal signal is a copy of the PA[3] terminal
status if PA3Edge=1. With PA3Edge=0 PA3Internal has
the inverted PA[3] value. See also Figure 18 and Figure 21.
S ta rt
PA3
S to p
Set
In itia l
V a lu e s
Figure 21. dT/MSC behavior
dT/MSC, PA3/up=1
Pulse-width
Measurem ent
PA3 internal
start
stop
Counting
Counter
RunEn
dT/MSC=0,
PA3/up=1
Period
m easurem ent
PA3 internal
start
Counter
RunEn
stop
Counting
restart
Counting
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8.5 Millisecond Counter Registers
Table 8.5.1 Register RegMSCCntl1
Bit
Name
3
RunEn/Stop
2
PA3/µP
1
dT/MSC
0
ResMSC
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Enable counter
Port A or CPU start stop control
Pulse-width measurement
Reset if write of 1
Read value is always 0
Default: Stop, CPU controlled.
Table 8.5.2 Register RegMSCCntl2
Bit
Name
Reset
R/W
Description
3
DebFreqSel
0
R/W
Debouncer frequency select
2
PA3Edge
0
R/W
PA[3] edge selection
1
IntSel
0
R/W
Interrupt source selection
0
FlSec
0
R
Seconds flag
Default: Ck[14] is debouncer clock, negative edge, 1/10 Sec Interrupt requests
Table 8.5.3 Register RegMSCDataL
Bit
Name
Reset
3
BCD[3]
0
2
BCD[2]
0
1
BCD[1]
0
0
BCD[0]
0
R/W
R
R
R
R
Description
1/1000 Seconds BCD value 3
1/1000 Seconds BCD value 2
1/1000 Seconds BCD value 1
1/1000 Seconds BCD value 0
Table 8.5.4 Register RegMSCDataM
Bit
Name
Reset
3
BCD[7]
0
2
BCD[6]
0
1
BCD[5]
0
0
BCD[4]
0
R/W
R
R
R
R
Description
1/100 Seconds BCD value 3
1/100 Seconds BCD value 2
1/100 Seconds BCD value 1
1/100 Seconds BCD value 0
Table 8.5.5 Register RegMSCDataH
Bit
Name
Reset
3
BCD[11]
0
2
BCD[10]
0
1
BCD[9]
0
0
BCD[8]
0
R/W
R
R
R
R
Description
1/10 Seconds BCD value 3
1/10 Seconds BCD value 2
1/10 Seconds BCD value 1
1/10 Seconds BCD value 0
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EM6620
9. Interrupt Controller
The EM6620 has 12 different interrupt request sources individually maskable. These are:
External(5)
- Port A,
- Compare
PA[3] .. PA[0] inputs
PB[0] input
Internal(8)
- Prescaler
- Millisecond Counter
- 10-bit Counter
- SVLD
ck[1], Blink, 32Hz/8Hz
1/10Sec or 1Sec
Count0, CountComp
End of measure
The SVLD and the Compare share the same interrupt line.
To be able to send an interrupt to the CPU, at least one of the interrupt request flags must be set (IRQxx) and
the general interrupt enable bit IntEn located in the register RegSysCntl1 must be set to 1. The interrupt
request flags can only be set by a positive edge of IRQxx with the corresponding mask register bit
(MaskIRQxx) set to 1.
Figure 22. Interrupt Controller Block Diagram
One of these Blocks for each IRQ
DB
DB[n]
Mask
Interrupt Request
Capture Register
General
INT En
Write
Write
IRQ to µP
IRQxx
12 Input-OR
Read
ClrIntBit
Reset
At power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any
interrupt request to be stored. Also the general interrupt enable IntEn is set to 0 (No IRQ to CPU) by reset.
After each read operation on the interrupt request registers RegIRQ1, RegIRQ2 or RegIRQ3 the contents of the
addressed register are reset. Therefore one has to make a copy of the interrupt request register if there was
more than one interrupt to treat. Each interrupt request flag may also be reset individually by writing 1 into it
(ClrIntBit).
Interrupt handling priority must be resolved through software by deciding which register and which flag inside
the register need to be serviced first.
Since the CPU has only one interrupt subroutine and because the IRQxx registers are cleared after reading, the
CPU does not miss any interrupt request which comes during the interrupt service routine. If any occurs during
this time a new interrupt will be generated as soon as the software comes out of the current interrupt subroutine.
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EM6620
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their
corresponding mask setting and not on the general interrupt enable status. Whenever the EM6620 goes into
HALT Mode the IntEn bit is automatically set to 1, thus allowing to resume from Halt Mode with an interrupt.
9.1 Interrupt control registers
Table 9.1.1 Register RegIRQ1
Bit
Name
Reset
R/W
3
IRQPA[3]
0
R/W*
2
IRQPA[2]
0
R/W*
1
IRQPA[1]
0
R/W*
0
IRQPA[0]
0
R/W*
W*; Writing of 1 clears the corresponding bit.
Description
Port A PA[3] interrupt request
Port A PA[2] interrupt request
Port A PA[1] interrupt request
Port A PA[0] interrupt request
Table 9.1.2 Register RegIRQ2
Bit
Name
Reset
R/W
3
IRQHz1
0
R/W*
2
IRQHz32/8
0
R/W*
1
IRQBlink
0
R/W*
0
IRQPB0Comp
0
R/W*
W*; Writing of 1 clears the corresponding bit.
Description
Prescaler interrupt request
Prescaler interrupt request
Prescaler interrupt request
Compare interrupt request
Table 9.1.3 Register RegIRQ3
Bit
Name
Reset
R/W
3
IRQVLD
0
R/W*
2
IRQMSC
0
R/W*
1
IRQCount0
0
R/W*
0
IRQCntComp
0
R/W*
W*; Writing of 1 clears the corresponding bit.
Description
VLD interrupt request
Millisecond Counter int. request
Counter interrupt request
Counter interrupt request
Table 9.1.4 Register RegIRQMask1
Bit
Name
Reset
3
MaskIRQPA[3]
0
2
MaskIRQPA[2]
0
1
MaskIRQPA[1]
0
0
MaskIRQPA[0]
0
Interrupt is not stored if the mask bit is 0.
R/W
R/W
R/W
R/W
R/W
Description
Port A PA[3] interrupt mask
Port A PA[2] interrupt mask
Port A PA[1] interrupt mask
Port A PA[0] interrupt mask
Table 9.1.5 register RegIRQMask2
Bit
Name
Reset
3
MaskIRQHz1
0
2
MaskIRQHz32/8
0
1
MaskIRQBlink
0
0
MaskIRQPB0Comp
0
Interrupt is not stored if the mask bit is 0.
R/W
R/W
R/W
R/W
R/W
Description
Prescaler interrupt mask
Prescaler interrupt mask
Prescaler interrupt mask
Compare interrupt mask
Table 9.1.6 register RegIRQMask3
Bit
Name
Reset
3
MaskIRQVLD
0
2
MaskIRQMSC
0
1
MaskIRQCount0
0
0
MaskIRQCntComp
0
Interrupt is not stored if the mask bit is 0
R/W
R/W
R/W
R/W
R/W
Description
VLD interrupt mask
Millisecond Counter interrupt mask
Counter interrupt mask
Counter interrupt mask
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EM6620
10. Supply Voltage Level Detector
The EM6620 has a built-in Supply Voltage Level Detector (SVLD), such that the CPU can compare the supply
voltage against a pre-selected value. During Sleep Mode this function is inhibited.
The CPU activates the supply voltage level Figure 23. SVLD Timing Diagram
SVLD <VBAT
SVLD >VBAT
detector by writing VldStart=1 in the register
VBAT =VDD
RegVldCntl. The actual measurement starts on
the next ck[9] rising edge and lasts during the compare level
ck[9] high period (2ms at 32kHz). The busy flag
ck[9] (256Hz)
VldBusy stays high from Start set until the
measurement is finished. The worst case time
CPU starts
CPU starts
measure
measure
until the result is available is 1.5 ck[9] prescaler
clock periods (32kHz -> 6ms).
Busy Flag
During the actual measurement the device will
measure
draw an additional 5uA of IVDD current. After the
end of the measure an interrupt request
0
1
Result
IRQVLD is generated and the result is available
by inspection of the bit VLDResult. If the result
Read Result
is read 0, then the power supply voltage was
greater than the detection level value. If read 1,
the power supply voltage was lower than the detection level value. During each read while Busy=1 the
VLDResult is not guaranteed.
10.1 SVLD Register
Table 10.1.1 register RegVldCntl
Bit
Name
Reset
R/W
3
VLDResult
0
R*
2
VLDStart
0
W
2
VLDBusy
0
R
1
NoOscWD
0
R/W
0
NoLogicWD
0
R/W
R*; VLDResult is not guaranteed while VLDBusy=1
Description
VLD result flag
VLD start
VLD busy flag
No Oscillator watchdog
No logic watchdog
The SVLD and the PB0 Input Comparator are using the same internal measurement block. Therefore
only one of the two functions can be activated at the same time.
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EM6620
11. RAM
The EM6620 has one 64x4 bit RAM built-in located on addresses hex 0 to 3F. All the RAM nibbles
are direct addressable.
Figure 24. RAM Architecture
64 x 4 direct addressable RAM1
RAM1_63
RAM1_61
4 bit R/W
4 bit R/W
4 bit R/W
RAM1_60
4 bit R/W
RAM1_62
.
.
.
.
.
.
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
RAM1_3
RAM1_2
RAM1_1
RAM1_0
RAM Extension : Unused R/W Registers can often be used as possible RAM extension. Be careful not to use
registers which start, stop, or reset some functions.
Unused LCD register latches can also be used as RAM extension. In case of 3 times multiplex and using all the
8 segment outputs you may have two additional 4 bit registers available. Also for each unused segment output
you may have one additional 4 bit register.
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EM6620
12. LCD Driver
The EM6620 has a built-in Liquid Crystal Display driver. A maximum of 32 segments can be displayed using
the 8 segment driver outputs (SEG[8:1) in 4:1 multiplex - 24 segments in the case of 3:1 multiplex - and the 4
back-planes (COM[4:1]).
The LCD driver has its own voltage regulator (1.05 Volt) and voltage multiplier to generate the driver bias
voltages VL1, VL2 and VL3 (VLCD). Using the metal1 mask the user can choose higher LCD reference
voltages. Please check with EM Marin the possible values and their impact on power consumption.
The special architecture of this LCD driver allows the user to specify the data and address for each individual
segment by metal mask option. It therefore adapts to every possible LCD display with a maximum of 32
independent segments. The LCD clock frequency is 256Hz. Thus the frame frequency is 256/8 Hz if 4:1
multiplex, or 256/6 if 3:1 multiplex.
Figure 25. LCD Architecture
VL3
x3
LCD Off
Enable
VL2
x2
RefLCD
LCD External
Supply
Voltage
Multiplier
VL1
x1
LCD Blank
1
Von
Phase 1 to 4
Voff
2
MUX
SEG[n]
3
4
Address
Bus
Data
Bus
Phase
Selection
Data
Latches
Output
Switches
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EM6620
12.1 LCD Control
The LCD driver has two control registers RegLCDCntl1,2
consumption, operation mode and bias voltage source.
to optimize for display contrast,
power
LCDExtSupply: Choosing external supply (LcdExtSupply=‘1’) disables the internal LCD voltage regulator and
voltage multiplier, it also puts the bias voltage terminals VL1, VL2 and VL3 into high impedance state. External
bias levels can now be connected to the VL1, VL2 and VL3 terminals. (Resistor divider chain or others).
Another way to adapt the VL1, VL2 and VL3 levels to specific user needs is to overdrive the VL1 output
(LcdExtSupply=0) with the desired value. The internal multiplier will multiply this new VL1 level to generate the
corresponding levels VL2 and VL3. The bit LCDExtSupply is only reset by initial POR.
LCD4Mux: With this switch one selects either 3:1 or 4:1 (default) times multiplexing of the 8 segment driver
outputs. In the case of 3:1 multiplexing the COM[4] is off.
LCDOff: Disables the LCD. The voltage multiplier and regulator are switched off ( 0 current ).The segment
latch information is maintained. The VL1, VL2 and VL3 outputs are pulled to VSS.
LCDBlank: All segment outputs are turned off. The voltage multiplier and regulator remain switched on.
LcdBlank can be used with the 1Hz and Blink interrupt to let the whole display blink (software controlled).
CkTripSel1,0: Selecting the appropriate voltage multiplier frequency to optimize display contrast and power
consumption. The value to use is also depending on the selected multiplier booster capacitors (typically 100nF).
12.2 LCD addressing
The LCD driver addressing is direct using
the registers LCD_0, LCD_1, LCD_2 until
LCD_15. All LCD Segment registers are
R/W..
A total of 16 addresses are available to the
user to define the addressing of the LCD
segment latches. For each of these latches
the user may also choose the data bit to be
connected. See also section 12.3. However
only 8x4 LCD segment latches are
implemented. The unused address and bit
locations are empty and can not be used as
RAM.
Figure 26. LCD addressing
1 6 x 4 d ire c t a d d re s s a b le L C D la tc h e s
b u t m a xim u m 8 x4 b its a r e R /W
4 b it R /W
LCD_15
LCD_14
LCD_13
LCD_12
LCD_11
LCD_10
LCD_9
LCD_8
LCD_7
LCD_6
4 b it R /W
4 b it R /W
4 b it R /W
4 b it R /W
4 b it R /W
4 b it R /W
4 b it R /W
4 b it R /W
LCD_5
LCD_4
LCD_3
LCD_2
4
4
4
4
LCD_1
4 b it R /W
LCD_0
4 b it R /W
4 b it R /W
b it
b it
b it
b it
R /W
R /W
R /W
R /W
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EM6620
12.3 Free segment allocation
Each segment (SEG[8:1]) terminal outputs the time multiplexed information from its 4 segment data latches.
Data latch 1 outputs during phase1, latch 2 during phase 2, latch 3 during phase 3 and latch 4 during phase 4.
In the case of 3 to 1 multiplexing the phase 4 is not used. This phase information together with the Common
(COM[4:1]), also called Back-planes, outputs defines if a given segment is light or not. COM[1] is on during
phase 1 and off during phase 2,3,4 , COM[2] is on during phase 2 and off during phase 1,3,4 , etc.
For each segment data latch the address location within the LCD address spacing (LCD_15 ... LCD_0 -->
LcdAdr[15:0]) can be user defined.
For each segment data latch the data bus connection (DB[3:0]) can be user defined.
Segment outputs
COM[1]
COM[2]
COM[3]
COM[4]
SEG[1]
DB[0], LCDAdr[0]
DB[1], LCDAdr[0]
DB[2], LCDAdr[0]
DB[3], LCDAdr[0]
SEG[2]
DB[0], LCDAdr[1]
DB[1], LCDAdr[1]
DB[2], LCDAdr[1]
DB[3], LCDAdr[1]
SEG[3]
DB[0], LCDAdr[2]
DB[1], LCDAdr[2]
DB[2], LCDAdr[2]
DB[3], LCDAdr[2]
...
...
...
...
...
SEG[6]
DB[0], LCDAdr[5]
DB[1], LCDAdr[5]
DB[2], LCDAdr[5]
DB[3], LCDAdr[5]
SEG[7]
DB[0], LCDAdr[6]
DB[1], LCDAdr[6]
DB[2], LCDAdr[6]
DB[3], LCDAdr[6]
SEG[8]
DB[0], LCDAdr[7]
DB[1], LCDAdr[7]
DB[2], LCDAdr[7]
DB[3], LCDAdr[7]
12.4 LCD Registers
Table 12.4.1 Register RegLcdCntl1
Bit
Name
3
-2
-1
CkTripSel1
0
CkTripSel0
Reset
R/W
Description
0
0
R/W
R/W
LCD multiplier clock select
LCD multiplier clock select
Table 12.4.2 multiplier clock frequency select
CkTripSel0
CkTripSel1
0
0
1
0
0
1
1
1
Table 12.4.3 Register RegLcdCntl2
Bit
Name
Reset
3
LCDBlank
1
2
LCDOff
1
1
Lcd4Mux
1
0
LCDExtSupply
X
(0 on POR)
multiplier clock
Ck[10]
Ck[9]
Ck[8]
Ck[7]
R/W
R/W
R/W
R/W
R/W
on 32 KHz operation
512 Hz
256 Hz
128 Hz
64 Hz
Description
LCD segment outputs off
LCD off (multiplier off)
4 : 1 multiplexed
external supply for VL1, VL2 and VL3
LCDExtSupply is set to ‘0’ by POR only
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EM6620
Figure 27. LCD Multiplexing Waveform
SEG[1] SEG[2] SEG[3] SEG[4] SEG[5]
CkLcd
Frame
COM1
COM2
COM1
VL3
COM3
VL2
COM4
VL1
VSS
COM2
VL3
VL2
VL1
COM1 VL3
VL2
SEG[1]
VL1
VSS
COM3
VL3
VSS
value =
hex 0
VL2
-VL1
-VL2
-VL3
VL1
VSS
COM4
VL3
COM1 VL3
VL2
SEG[2]
VL1
VL2
VL1
VSS
VSS
value =
hex 1
-VL1
-VL2
-VL3
SEG[1] VL3
value =
hex 0
VL2
VL1
VSS
COM2 VL3
VL2
SEG[3]
VL1
VSS
SEG[2] VL3
value =
hex 1
VL2
value =
hex 2
VL1
-VL1
-VL2
-VL3
VSS
SEG[3] VL3
value =
hex 2
VL2
COM3 VL3
VL2
SEG[4]
VL1
VL1
VSS
VSS
value =
hex 4
SEG[4] VL3
value =
hex 4
-VL1
-VL2
-VL3
VL2
VL1
VSS
COM4 VL3
VL2
SEG[5]
VL1
SEG[5] VL3
value =
hex 8
VL2
VL1
VSS
value =
hex 8
VSS
-VL1
-VL2
-VL3
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EM6620
13. PERIPHERAL MEMORY MAP
Reset values are valid after power up or after every system reset.
Register
Name
Ram_0
...
Ram_63
Add Add
Hex Dec
00
...
3F
0
...
63
Reset
Value
b'3210
Read Bits
Write Bits
Read / Write Bits
0: data0
1: data1
2: data2
3: data3
xxxx
Direct addressable Ram
64x4
...
...
0: data0
1: data1
2: data2
3: data3
xxxx
LCD_0
40
64
xxxx
...
...
...
...
LCD_15
4F
79
xxxx
RegPA
50
80
xxxx
RegPBCntl
51
81
0000
RegPBData
52
82
xxxx
RegPB0Comp
53
83
0000
RegCCntl1
5B
91
0000
RegCCntl2
5C
92
0000
Remarks
Direct addressable Ram
64x4
0: Data0
1: Data1
2: Data2
3: Data3
Direct addressable LCD
0: Data0
1: Data1
2: Data2
3: Data3
0: PA[0]
1: PA[1]
2: PA[2]
3: PA[3]
Direct addressable LCD
----
0: PBIOCntl[0]
1: PBIOCntl[1]
2: PBIOCntl[2]
3: PBIOCntl[3]
0: PB[0]
0: PBData[0]
1: PB[1]
1: PBData[1]
2: PB[2]
2: PBData[2]
3: PB[3]
3: PBData[3]
0:
0:
PB0CompSelect
PB0CompSelect
1:
1:
PB0CompEnable
PB0CompEnable
2:
2: -PB0CompResult
3: -3: '0'
0: CountFSel0
1: CountFSel1
2: CountFSel2
3: UP/Down
0: '0'
0 : Load
1: EnComp
1: EnComp
2: EvCount
2: EvCount
3: Start
3: Start
Read port A directly
Port B Control
Default: input mode
Port B data output
Pin port B read
Default : 0
Port B[0] dynamic
input comparator control
10 bit counter
control 1;
Frequency and up/down
10 bit counter control 2;
comparison, event counter
and start
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EM6620
Register
Name
Add
Hex
Add
Dec
Reset
Value
b'3210
RegCDataL
5D
93
0000
RegCDataM
5E
94
0000
RegCDataH
5F
95
0000
RegMSCCntl1
60
96
0000
RegMSCCntl2
61
97
0000
RegMSCDataL
62
98
0000
RegMSCDataM
63
99
0000
RegMSCDataH
64
100
0000
RegIRQMask1
65
101
0000
RegIRQMask2
66
102
0000
RegIRQMask3
67
103
0000
RegIRQ1
68
104
0000
RegIRQ2
69
105
0000
Read Bits
Write Bits
Read / Write Bits
0: Count[0]
0: CReg[0]
1: Count[1]
1: CReg[1]
2: Count[2]
2: CReg[2]
3: Count[3]
3: CReg[3]
0: Count[4]
0: CReg[4]
1: Count[5]
1: CReg[5]
2: Count[6]
2: CReg[6]
3: Count[7]
3: CReg[7]
0: Count[8]
0: CReg[8]
1: Count[9]
1: CReg[9]
2: BitSel[0]
2: BitSel[0]
3: BitSel[1]
3: BitSel[1]
0: '0'
0: ResMSC
1: dT/MSC
1: dT/MSC
2: PA3/µP
2: PA3/µP
3:RunEn/Stop
3:RunEn/Stop
0: FlSec
0: -1: IntSel
1: IntSel
2: PA3Edge
2: PA3Edge
3: DebFreqSel
3: DebFreqSel
0: BCD[0]
0: 1: BCD[1]
1: 2: BCD[2]
2: 3: BCD[3]
3: 0: BCD[4]
0: 1: BCD[5]
1: 2: BCD[6]
2: 3: BCD[7]
3: 0: BCD[8]
0: 1: BCD[9]
1: 2: BCD[10]
2: 3: BCD[11]
3: 0: MaskIRQPA[0]
1: MaskIRQPA[1]
2: MaskIRQPA[2]
3: MaskIRQPA[3]
0: MaskIRQPB0Comp
1: MaskIRQBlink
2: MaskIRQHz32/8
3: MaskIRQHz1
0: MaskIRQCntComp
1: MaskIRQCount0
2: MaskIRQMSC
3: MaskIRQVLD
0: IRQPA[0]
0: RIRQPA[0]
1: IRQPA[1]
1: RIRQPA[1]
2: IRQPA[2]
2: RIRQPA[2]
3:IRQPA[3]
3: RIRQPA[3]
0: IRQPB0Comp 0: RIRQPB0Comp
1: IRQBlink
1: RIRQBlink
2: IRQHz32/8
2: RIRQHz32/8
3: IRQHz1
3: RIRQHz1
Remarks
10 bit counter
data low bits
10 bit counter
data middle bits
10 bit counter
data high bits
Millisecond counter
control register 1;
Reset, delta time, control
source
Millisecond counter
control
register 2;
1 sec flag, Interrupt
and PA3 edge select
Millisecond counter;
binary coded decimal
value, low nibble
Millisecond counter;
binary coded decimal
value, middle nibble
Millisecond counter;
binary coded decimal
value, high nibble
Port A interrupt mask;
masking active low
Prescaler interrupt mask;
masking active low
10 bit counter, millisecond
counter, serial interrupt
mask
masking active low
Read: Port A interrupt
Write: Reset if data bit = 1
Read: prescaler IRQ ;
Write: Reset if data bit = 1
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EM6620
Register
Name
Add Add
Hex Dec
Reset
Value
b'3210
RegIRQ3
6A
106
0000
RegSysCntl1
6B
107
0000
RegSysCntl2
6C
108
0p00
p=POR
RegPresc
6D
109
0000
IXLow
6E
110
xxxx
IXHigh
6F
111
xxxx
RegLcdCntl1
71
113
RegLcdCntl2
72
114
--00
111p
p=POR
RegVLDCntl
73
115
0000
Read Bits
Write Bits
Read / Write Bits
0:IRQCntComp
0: RIRQCntComp
1: IRQCount0
1: RIRQCount0
2: IRQMSC
2: RIRQMSC
3: IRQVLD
3: RIRQVLD
0: ChTmDis
0: ChTmDis
1: SelIntFull
1: SelIntFull
2: '0'
2: Sleep
3: IntEn
3: IntEn
0: WDVal0
0: -1: WDVal1
1: -2: SleepEn
2: SleepEn
3: '0'
3: WDReset
0: DebSel
0: DebSel
1: PrIntSel
1: PrIntSel
2: '0'
2: ResPresc
3: PWMOn
3: PWMOn
0: IXLow[0]
1: IXLow[1]
2: IXLow[2]
3: IXLow[3]
0: IXHigh[4]
0: IXHigh[4]
1: IXHigh[5]
1: IXHigh[5]
2: IXHigh[6]
2: IXHigh[6]
3: '0'
3: -0: CkTripSel0
1: CkTripSel1
2: -3: -0: LCDExtSupply
1: Lcd4xMux
2: LCDOff
3: LCDBlank
0: NoLogicWD
0: NoLogicWD
1: NoOscWD
1: NoOscWD
2: VldBusy
2: VldStart
3: VLDResult
3: --
Remarks
Read: 10 bit counter,
millisecond counter, serial
interrupt
Write: Reset if data bit =1.
System control 1
ChTmDis only usable for Em
test modes with Test=1
System control 2;
watchdog value and
periodical reset, enable
sleep mode
Prescaler control;
debouncer and prescaler
interrupt select
Internal µP index
register low nibble;
Internal µP index
register high nibble;
LCD control 0
multiplier clock
LCD control 1;
main selects
voltage level
detector control
P=POR means that this bit is set to 0 on POR only.
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EM6620
14. Option Register Memory Map
The values of the Option Registers are set by initial reset on power up and through write
operations only. Other resets as reset from watchdog, reset from input port A do not change the
options register value.
Register
Name
OPTDebIntPA
Add Add
Hex Dec
.
Power
On
Value
b'3210
75
117
0000
76
118
0000
77
119
0000
78
120
0000
79
121
0000
7B
123
0000
OPT[3:0]
OPTIntEdgPA
OPT[7:4]
OPTNoPullPA
OPT[11:8]
OPTNoPdPB
OPT[15:12]
OPTNchOpDPB
OPT[19:16]
OPTFSelPB
OPT[31:28]
OptInpRSel1
7C
124
0000
OptInpRSel2
7D
125
0000
RegTestEM
7F
127
----
Read Bits
Write Bits
Read / Write Bits
0: NoDebIntPA[0]
1: NoDebIntPA[1]
2: NoDebIntPA[2]
3: NoDebIntPA[3]
0: IntEdgPA[0]
1: IntEdgPA[1]
2: IntEdgPA[2]
3: IntEdgPA[3]
0: NoPullPA[0]
1: NoPullPA[1]
2: NoPullPA[2]
3: NoPullPA[3]
0: NoPdPB[0]
1: NoPdPB[1]
2: NoPdPB[2]
3: NoPdPB[3]
0: NchOpDPB[0]
1: NchOpDPB[1]
2: NchOpDPB[2]
3: NchOpDPB[3]
0: NoInputReset
1: PB32kHzOut
2: PB2kHzOut
3: PB1HzOut
0: InpRes1PA[0]
1: InpRes1PA[1]
2: InpRes1PA[2]
3: InpRes1PA[3]
0: InpRes2PA[0]
1: InpRes2PA[1]
2: InpRes2PA[2]
3: InpRes2PA[3]
----
accu
Remarks
Option register;
debouncer on Port A
for interrupt gen.
default: debouncer on
Option register;
interrupt edge select on port A
default: pos. edge
option register;
pull-down selection on port A
default: pull-down
Option register;
pull-down selection on port B
default: pull-down
Option register;
n-channel open drain
output on port B
default: CMOS output
Option register;
port A input reset selection,
frequency output on port B
Option register;
port A input reset selection,
refer to reset part
Option register;
reset through port A inputs
selection,
refer to reset part
for EM test only;
write accu on port B
Test = 1
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EM6620
15. Active Supply Current test
For this purpose, five instructions at the end of the ROM will be added. This will be done at EM Marin.
So the user must keep must only use up to 1275 Instructions.
Testloop:
STI
LDR
NXORX
JPZ
JMP
00H, 0AH
1BH
Testloop
00H
To stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop:
1BH:
32H:
6EH:
6FH:
0101b
1010b
0010b
0011b
Free space after last instruction: JMP 00H (0000)
Remark: empty space within the program are filled with NOP (FOFF).
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EM6620
16. Mask Options
Most options which in many µControllers are realized as metal mask options are directly user selectable with the
option registers, therefore allowing a maximum freedom of choice .See chapter: 14.
The following options can be selected at the time of programming the metal mask ROM, except the LCD
Segment allocation which is defined using the interconnect metal2 mask.
16.1 Input / Output Ports
16.1.1 Port A Metal Options
Figure 28. Port A Pull Options
Pull-up or no pull-up can be selected
for each port A input. A pull-up
Input Circuitry
selection is excluding a pull-down on
the same input.
Pull-up Control
Pull-down (default) or no pull-down
can be selected for each port A input.
A pull-down selection is excluding a
pull-up on the same input.
PA[n]
The total pull value (pull-up or pullTerminal Resistor R1
down) is a series resistance out of
100 KOhm
the resistance R1 and the switching
OR
transistor. As a switching transistor
the user can choose between a high
impedance (weak) or a low
impedance (strong) switch. Weak,
strong or none must be chosen. The
Pull-down Control
default is strong. The default resistor
R1 value is 100 KOhm. The user
may choose a different value from
150 KOhm down to 0 Ohm. However
the value must first be checked and
agreed by EM Microelectronic Marin
SA. Refer also to chapter 17.2 and 17.3 for the pull values.
Strong
Pulldown
Option
Name
1
MPAPD[3]
MPAPD[2]
MPAPD[1]
MPAPD[0]
R1
Value
typ.100k
No
Pulldown
2
3
4
MPAPUstrong[n]
Strong Pull-up
No Pull-up
No Pull-down
MPAPDstrong[n]
Strong Pull-down
MPAPDweak[n]
Weak Pull-down
To select an option put an X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : Strong pulldown with R1=100 KOhm
PA3 input pull-down
PA2 input pull-down
PA1 input pull-down
PA0 input pull-down
Option
Name
MPAPU[3]
MPAPU[2]
MPAPU[1]
MPAPU[0]
W
Pulldown
MPAPUweak[n]
Weak Pull-up
Strong
Pull-up
Weak
Pull-up
R1
Value
typ.100k
No
Pull-up
1
2
3
4
To select an option put an X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : Strong pull-up
with R1=100 KOhm
PA3 input pull-up
PA2 input pull-up
PA1 input pull-up
PA0 input pull-up
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EM6620
16.1.2 Port B Metal Options
Pull-up or no pull-up can be
selected for each port B input. The
pull-up is only active in Nch. open
drain mode.
Pull-down or no pull-down can be
selected for each port B input.
Figure 29. Port B Pull Options
Input Circuitry
Pull-Up Control
The total pull value (pull-up or pulldown) is a series resistance out of
the resistance R1 and the switching
transistor. As a switching transistor
the user can choose between a high
impedance (weak) or a low
impedance (strong) switch. Weak ,
strong or none must be chosen.
The default is strong. The default
resistor R1 value is 100 KOhm. The
user may choose a different value
from 150 KOhm down to 0 Ohm.
However the value must first be
checked and agreed by EM
Microelectronic Marin SA. Refer
also to chapter 17.2 and 17.3 for
the pull values.
PB[n]
Terminal
or
No Pull-up
No Pull-down
Pull-down Control
Weak
Pulldown
2
R1
Value
Typ.100k
3
No
Pulldown
MPBPDweak[n]
Weak Pull-down
To select an option put an X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
4
The default value is : Strong pulldown with R1=100 KOhm
PB3 input pull-down
PB2 input pull-down
PB1 input pull-down
PB0 input pull-down
Option
Name
MPBPU[3]
MPBPU[2]
MPBPU[1]
MPBPU[0]
Resistor R1
100 KOhm
MPBPDstrong[n]
Strong Pull-down
1
MPBPD[3]
MPBPD[2]
MPBPD[1]
MPBPD[0]
MPBPUstrong[n]
Strong Pull-up
Block
Strong
Pulldown
Option
Name
MPBPUweak[n]
Weak Pull-up
Strong
Pull-up
Weak
Pull-up
1
2
R1
value
Typ. 100k
3
NO
Pull-up
4
To select an option put an X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : Strong pull-up
with R1=100 KOhm
PB3 input pull-up
PB2 input pull-up
PB1 input pull-up
PB0 input pull-up
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EM6620
16.1.3 Voltage Regulator Option
Option
name
MVreg
Voltage Regulator
Default
value
A
YES
user
value
B
By default the internal voltage regulator supplies the
core logic the RAM and the ROM. With option
MVreg(B) the regulator is cut and Vbat is supplying
the core logic the ROM and the RAM.
16.1.4 SVLD and Input Comp Level Option
Option
name
VSVLD
Comparator Level
and SVLD Level
Default
value
A
2.0
user
value
B
By default the level is 2.0 Volts. The maximum value
is 3.3 Volt and the minimum is 1.2 Volts.
Before choosing a value other than the default,
please contact EM Microelectronic Marin SA, to check
for already existing levels.
The chosen value is called VSVLDNom.
16.1.5 Debouncer frequency Option
Option
name
MDeb
Debouncer freq.
Default
value
A
ck[11]
user
value
B
By default the debouncer frequency is ck[11]. The
user may choose ck[14] instead of ck[11].
Ck[14 ]corresponds to maximum 0.25ms debouncer
time in case of a 32kHz oscillator.
16.1.6 User defined LCD Segment allocation
If using a different segment allocation from the one described in chapter 0 , one needs to fill in the table
below.
The segment allocation connections are realized with the interconnect Metal 2 mask.
in case of 4 times
MUX
COM[1]
COM[2]
COM[3]
COM[4]
in case of 3 times
MUX
COM[1]
COM[2]
COM[3]
--
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
The customer should specify the required options at the time of ordering. A copy of
the pages 44 to 46 as well as the « Software ROM characteristic file » generated by
the assembler (*.STA) should be attached to the order. Also the Customer package
marking, 7 Characters, should be defined at that time.
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EM6620
17. Temp. and Voltage Behaviors
17.1 IDD Current (typical)
ID D H a l t M o d e ; R e g u l a t o r ; V D D = 3 .0 V
ID D H a l t M o d e ; N o R e g u l a t o r ; V D D = 1.5 V
750
750
[ nA ]
[ nA ]
50 0
50 0
2 50
2 50
0
0
-2 0
0
20
6 0 [ °C ]
40
-2 0
80
ID D H a l t M o d e L C D O n ; N o R e g u l a t o r ; V D D = 1.5 V
0
20
40
[ °C ]
60
80
ID D H a l t M o d e L C D O n ; R e g u l a t o r ; V D D = 3 .0 V
900
900
[ nA ]
600
600
[ nA ]
300
300
0
-2 0
0
20
40
[ °C ]
60
0
80
-2 0
ID D R u n M o d e L c d O n ; N o R e g u l a t o r ; V D D = 1.5 V
[ nA ]
2000
15 0 0
15 0 0
10 0 0
20
40
60
40
60
[ °C ]
80
[ °C ]
80
2 50 0
2000
0
20
ID D R u n M o d e L C D O n ; R e g u l a t o r ; V D D = 3 .0 V
2 50 0
[ nA ]
-2 0
0
10 0 0
[ °C ]
80
-2 0
0
20
40
60
17.2 Pull-down Resistance (typical)
P u lld o w n W e a k ; N o R e g u la t o r ; 2 5 D e g
P u lld o w n W e a k ; R e g u la t o r ; 2 5 D e g
300
400
[ k O hm ]
[ k O hm ]
300
200
200
10 0
10 0
0
1. 2
1.4
0
[V ]
1. 6
1. 8
1. 4
P u lld o w n S t r o n g ; N o R e g u la t o r ; 2 5 D e g
2
2 .6
3 .2
[V ]
P u lld o w n S t r o n g ; R e g u la t o r ; 2 5 D e g
10 5
[ k O hm ]
10 2 . 5
10 5
[ k O hm ]
10 2 . 5
10 0
10 0
9 7 .5
9 7 .5
95
1.2
1. 4
95
[V ]
1.6
P u l l d o w n W e a k ; N o R e g u l a t o r ; V D D = 1. 5 V
200
[ k O hm ]
1.4
1.8
15 0
600
[ k O hm ]
4 50
10 0
300
50
15 0
0
-2 0
0
20
40
60
[ °C ]
2
3 .2 [ V ]
2 .6
P u ll d o w n W e a k , R e g u l a t o r ; V D D = 3 .0 V
0
80
-2 0
P u l l d o w n S t r o n g ; N o R e g u l a t o r ; V D D = 1. 5 V
0
20
40
60
[ °C ]
80
P u l l d o w n S t r o n g ; R e g u l a t o r ; V D D = 3 .0 V
15 0
15 0
[ k O hm ]
[ k O hm ]
10 0
10 0
50
50
0
-2 0
0
20
40
60
0
[ °C ] 8 0
-2 0
0
20
40
60
[ °C ]
80
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17.3 Pull-up Resistance (typical)
P u llu p W e a k ; N o R e g u la t o r ; T e m p =2 5 D e g
P u llu p W e a k ; R e g u la t o r ; T e m p =2 5 D e g
2000
[ k O hm ]
15 0 0
2000
[ k O hm ]
15 0 0
10 0 0
10 0 0
50 0
50 0
0
0
1.2
1.4
[V ]
1.6
1.8
1.4
P u llu p S t r o n g ; N o R e g u la t o r ; T e m p =2 5 D e g
2
2 .6
[V ]
3 .2
P u llu p S t r o n g ; R e g u la t o r ; T e m p =2 5 D e g
14 0
14 0
[ k O hm ]
12 0
[ k O h m 12
] 0
10 0
10 0
80
80
1.2
1.4
P u llu p
[V ]
1.6
1.8
1.4
W e a k ; N o R e g u l a t o r ; V D D = 1.5 V
2
2 .6
[V ]
3 .2
P u l l u p W e a k ; R e g u l a t o r ; V D D = 3 .0 V
10 0 0
300
[ k O hm ]
800
[ k O hm ]
200
600
10 0
400
-2 0
0
20
40
[ °C ]
60
0
80
-2 0
P u l l u p S t r o n g ; N o R e g u l a t o r ; V D D = 1.5 V
0
20
40
[ °C ]
60
80
P u l l u p S t r o n g ; R e g u l a t o r ; V D D = 3 .0 V
15 0
15 0
[ k O hm ]
[ k O hm ]
10 0
10 0
50
50
0
-2 0
0
20
40
[ °C ]
60
0
80
-2 0
0
20
40
60
[ °C ]
80
17.4 Output currents (typical)
IOL C urrent s; V D S=0 .15/ 0 .3 / 0 .5/ 1.0 V ; Temp =2 5D eg
1.2
15.0
[ mA ]
12 .0
0 .0
1.0
0 .15
-3 .0
9 .0
0 .3
0 .5
6 .0
0 .15
0 .0
0 .5
-6 .0
0 .3
3 .0
-9 .0
1.0
[ mA ]
1.2
1.8
2 .4
3
[V]
3 .6
-12 .0
IOH C urrent s; V D D =3 .0 V ; V D S=0 .15/ 0 .3 / 0 .5/ 1.0 V
IOH C urrent s; V D D =1.5V ; V D S=0 .15/ 0 .3 / 0 .5/ 1.0 V
-2 0
0
20
40
60
-2 0
[ °C ] 8 0
0
20
40
60
[ °C ] 8 0
0 .0
0 .0
0 .15
0 .3
0 .5
-3 .0
-0 .5
0 .15
-1.0
0 .3
-6 .0
-1.5
0 .5
-9 .0
[ mA ]
-2 .0
1.0
[ mA ]
-12 .0
IOL C urrent s; V D D =1.5V ; V D S=0 .15/ 0 .3 / 0 .5/ 1.0 V
1.0
IOL C urrent s; V D D =3 .0 V ; V D S=0 .15/ 0 .3 / 0 .5/ 1.0 V
15.0
5.0
[ mA ]
IOH C urrent s; V D S=0 .15/ 0 .3 / 0 .5/ 1.0 V ; Temp =2 5D eg
[ V ] 3 .6
1.8
2 .4
3
[ mA ]
4 .0
3 .0
1.0
10 .0
1.0
0 .5
2 .0
0 .3
1.0
0 .15
0 .5
0 .3
0 .15
5.0
0 .0
0 .0
-2 0
0
20
40
60
[ °C ] 8 0
-2 0
0
20
40
60
[ °C ] 8 0
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EM6620
18. EM6620 Electrical specifications
18.1 Absolute maximum ratings
Min.
- 0.2
VSS - 0,2
- 40
-2000
Max.
+ 3.6
VDD+0,2
+ 125
+2000
Units
V
V
°C
V
Power supply VDD-VSS
Input voltage
Storage temperature
Electrostatic discharge to
Mil-Std-883C Method 3015.7 with ref. to VSS
Maximum soldering conditions
10s x 250°C
Stresses above these listed maximum ratings may cause permanent damage to the device.
Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction.
18.2 Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions
should be taken as for any other CMOS component.
Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the
supply voltage range.
18.3 Standard Operating Conditions
Parameter
MIN
TYP
MAX
Unit
Description
Temperature
-20
25
85
°C
VDD_Range1
1.4
3.0
3.6
V
with
internal voltage regulator
VDD_Range2
1.2
1.5
1.7
without internal voltage regulator
VSS
0
V
Reference terminal
CVDDCA (note 1)
100
nF
regulated voltage capacitor
fq
32768
Hz
nominal frequency
Rqs
35
kOhm
typical quartz serial resistance
CL
8.2
pF
typical quartz load capacitance
df/f
+/- 30
ppm
quartz frequency tolerance
Note 1: This capacitor filters switching noise from VDD to keep it away from the internal logic cells.
In noisy systems the capacitor should be chosen bigger than minimum value.
18.4 DC characteristics - Power Supply
Conditions: Vdd=1.5V, T=25°C, without internal voltage regulator (unless otherwise specified)
Parameter
Conditions
Symbol
Min.
Typ.
Max. Unit
ACTIVE Supply Current
(note2,3)
2.0
3.0
µA
IVDDa1
(in active mode with LCD on)
-20 ... 85°C (note2,3)
3.1
µA
IVDDa1
STANDBY Supply Current
0.4
0.6
µA
IVDDh1
(in Halt mode, LCDOff)
-20 ... 85°C
0.8
µA
IVDDh1
SLEEP Supply Current
0.1
0.25
µA
IVDDs1
-20 ... 85°C
0.28
µA
IVDDs1
POR static level
-20 ... 85°C
0.85
1.1
V
VPOR1
RAM data retention
1.0
V
Vrd1
Note 2: Lcd Display NOT connected.
Note 3: For test reasons, the user has to provide a test loop with successive writing and reading of two different
addresses (5 instructions should be reserved for this measurement).
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Conditions: Vdd=3.0V, T=25°C, with internal voltage regulator (unless otherwise specified)
Parameter
ACTIVE Supply Current
(in active mode with LCD on)
STANDBY Supply Current
(in Halt mode, LCDOff)
SLEEP Supply Current
Conditions
Symb.
(note2,3)
-20 ... 85°C (note2,3)
IVDDa2
IVDDa2
IVDDh2
IVDDh2
IVDDs2
IVDDs2
-20 ... 85°C
Min.
Typ.
Max.
Unit
2.1
3.1
3.5
0.7
0.9
0.28
0.3
1.25
µA
µA
µA
µA
µA
µA
V
V
V
0.5
0.15
-20 ... 85°C
POR static level
-20 ... 85°C, No Load on Vreg
VPOR2
0.95
RAM data retention
-20 ... 85°C
Vrd2
1.2
Regulated voltage
Halt Mode, No Load
Vreg
1.2
1.4
1.7
Note 2: LCD Display NOT connected.
Note 3: For test reasons, the user has to provide a test loop with successive writing and reading of two different
addresses (5 instructions should be reserved for this measurement).
18.5 SVLD and Input Comparator
Conditions: Standard operating conditions (unless otherwise specified)
Parameter
Conditions
SVLD voltage Level
-10 ... 60°C
-20 ... 85°C
-10 ... 60°C
-20 ... 85°C
Symb.
VSVLD
VSVLD
VSVLD
VSVLD
Min.
Typ.
0.92 VSVLDNom
0.9 VSVLDNom
0.92 VSVLDNom
0.9 VSVLDNom
VSVLDNOM
VSVLDNOM
VSVLDNOM
VSVLDNOM
Max.
Unit
1.08 VSVLDNom
1.1 VSVLDNom
1.08 VSVLDNom
1.1 VSVLDNom
Input Comparator
VINMax=VDD+0.2V
VDD= VSVLDNom
Input Comparator
-100
-20 ... 85°C dVSVLD/dVDD
voltage dependency
versus VDD
Note 4: VSVLDNom is coming from the SVLD option Mask definition sheet (chapter 16.1.4).
V
V
V
V
mV/V
18.6 Oscillator
Conditions: T=25°C (unless otherwise specified)
Parameter
Conditions
Symb.
Min.
Typ.
Temperature stability
+15 ... +35 °C
df/f x dT
Voltage stability (note 5) VDD=1,4 - 1,6 V
df/f x dU
Input capacitor
Ref VSS
Cin
5,6
7
Output capacitor
Ref VSS
Cout
12,1
14
Transconductance
50mVpp,VDDmin
Gm
2.5
Oscillator start voltage
Tstart < 10 s
Ustart
VDDmin
Oscillator start time
VDD > VDDMin
tdosc
0.5
System start time
tdsys
1.5
(oscillator + cold start +
reset)
Oscillation detector
VDD > VDDmin
tDetFreq
frequency
Note 5 ; applicable only for the versions without the internal voltage regulator
Max.
0,3
5
8,4
15,9
15.0
Unit
3
4
ppm /°C
ppm /V
pF
pF
µA/V
V
s
s
12
kHz
03/02 REV. F/443
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EM6620
18.7 DC characteristics - I/O Pins
Conditions: T= -20 ... 85°C (unless otherwise specified)
VDD=1.5V means; measures without voltage regulator
VDD=3.0V means; measures with voltage regulator
Parameter
Conditions
Symb
Min.
Typ.
Max.
Unit
Input Low voltage
Ports A,B Test
VDD < 1.5V
VIL
Vss
0.2VDD
V
Ports A,B Test
VDD > 1.5V
VIL
Vss
0.3VDD
V
QIN with Regulator
VIL
Vss
0.1VREG V
QIN without Regulator
VIL
Vss
0.1VDD
V
Ports A,B Test
VIH
0.7VDD
VDD
V
QIN with Regulator
VIH
0.9VREG
VREG
V
QIN without Regulator
VIH
0.9VDD
VDD
V
QOUT (note 7)
Input High voltage
QOUT (note 7)
Output Low Current
VDD=1.5V , VOL=0.15V
IOL
1.1
mA
Port B
VDD=1.5V , VOL=0.30V
IOL
2.1
mA
VDD=1.5V , VOL=0.50V
IOL
3.1
mA
VDD=3.0V , VOL=0.15V
IOL
1.8
mA
VDD=3.0V , VOL=0.30V
IOL
3.6
mA
VDD=3.0V , VOL=0.50V
IOL
5.8
mA
VDD=3.0V , VOL=1.00V
IOL
11.0
mA
Output High Current
VDD=1.5V, VOH= VDD-0.15V
IOH
-0.6
mA
Port B
VDD=1.5V, VOH= VDD-0.30V
IOH
-1.1
mA
VDD=1.5V, VOH= VDD-0.50V
IOH
-1.5
VDD=3.0V, VOH= VDD-0.15V
IOH
-1.3
mA
VDD=3.0V , VOH= VDD-0.30V
IOH
-2.6
mA
VDD=3.0V , VOH= VDD-0.50V
IOH
-4.2
mA
VDD=3.0V , VOH= VDD-1.00V
IOH
-7.7
Input Pull-down
VDD=1.5V, Pin at 1.5V, 25°C
RPD
15k
Ohm
Test
VDD=3.0V, Pin at 3.0V, 25°C
RPD
15k
Ohm
Input Pull-down
VDD=1.5V, Pin at 1.5V, 25°C
RPD
100k
150k
300k
Ohm
Port A,B (note 8) weak
VDD=3.0V, Pin at 3.0V, 25°C
RPD
200k
300k
600k
Ohm
Input Pull-up
VDD=1.5V, Pin at 0.0V, 25°C
RPU
500k
800k
2000k
Ohm
Port A,B (note 8) weak
VDD=3.0V, Pin at 0.0V, 25°C
RPU
115k
190k
475k
Ohm
Input Pull-down
VDD=1.5V, Pin at 1.5V, 25°C
RPD
72k
102k
132k
Ohm
Port A,B (note 8) strong
VDD=3.0V, Pin at 3.0V, 25°C
RPD
70k
100k
130k
Ohm
Input Pull-up
VDD=1.5V, Pin at 0.0V, 25°C
RPU
76k
109k
142k
Ohm
Port A,B (note 8) strong
VDD=3.0V, Pin at 0.0V, 25°C
RPU
72k
103k
134k
Ohm
1.55
5.5
-0.75
-3.85
mA
mA
Note 7 ; QOUT (OSC2) is used only with Quartz.
Note 8 : Weak or strong are standing for weak pull resp. strong pull transistor. Values are for R1=100kOhm
03/02 REV. F/443
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EM6620
18.8 LCD Seg[8:1] Outputs
Conditions: T=25°C (unless otherwise specified)
Parameter
Conditions
Symb.
Driver Impedance Level 0
Iout = ±5µA,
ext. Supply
Iout = ±5µA,
ext Supply
Iout = ±5µA,
ext Supply
Iout = ±5µA,
ext Supply
RsegVL0
20
kOhm
RsegVL1
20
kOhm
RsegVL2
20
kOhm
RsegVL3
20
kOhm
Max.
10
Unit
kOhm
RcomVL1
10
kOhm
RcomVL2
10
kOhm
RcomVL3
10
kOhm
Driver Impedance Level 1
Driver Impedance Level 2
Driver Impedance Level 3
Min.
Typ.
Max.
Unit
18.9 LCD Com[4:1] Outputs
Conditions: T=25°C (unless otherwise specified)
Parameter
Conditions
Driver Impedance Level 0
Iout = ±5µA,
ext. Supply
Driver Impedance Level 1
Iout = ±5µA,
ext. Supply
Driver Impedance Level 2
Iout = ±5µA,
ext Supply
Driver Impedance Level 3
Iout = ±5µA,
ext Supply
Symb.
RcomVL0
Min.
Typ.
18.10 DC Output Component
Conditions: T=25°C (unless otherwise specified)
Parameter
Conditions
Symb.
DC Output component
No Load
Min.
±VDC_com
Typ.
Max.
20
Unit
mV
18.11 LCD voltage multiplier
Conditions: T=25°C, VDD=VDDtyp, All Multiplier Capa’s 100nF, Multiplier freq=512Hz. (unless otherwise
specified)
Parameter
Conditions
Symb.
Min.
Typ.
Max.
Unit
VVL1
Voltage Bias Level 1
0.95
1.05
1.15
V
1µA load
VVL2
Voltage Bias Level 2
2.10
V
1µA load
VVL3
Voltage Bias Level 3
3.15
V
1µA load
dV
VL1
/dT
-4.9
mV/°C
1
µ
A
load,
-10...60
°
C
Temp dependency VvL1
03/02 REV. F/443
Copyright 2002, EM Microelectronic-Marin SA
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EM6620
19. Pad Location Diagram
03/02 REV. F/443
Copyright 2002, EM Microelectronic-Marin SA
53
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EM6620
20. Package & Ordering information
Figure 32 TQFP32 Package Dimensions
TOP VIEW
D
ODD LEAD SIDES
EVEN LEAD SIDES
e
b
D1
DETAIL "A"
e
SEE DETAIL "A"
S
Y
M
B
O
L
A
TQFP32
ALL DIMENSIONS IN MILLIMETERS
MIN.
TYP.
SEE DETAIL "B"
DETAIL "B"
MAX.
1.20
A
A1
0.05
A2
0.95
0.15
1.00
D
9.00 BSC.
D1
7.00 BSC.
1.05
0° MIN.
L
0.08/0.20 R.
A2
0.08
R. MIN.
0.20 MIN.
0.60
0.75
32
0.80 BSC
e
b
A1
0.45
N
0.30
0.37
0.45
0-7°
L
1.00 REF.
1.00/0.10 MM FORM, 1.00 MM THICK
PACKAGE OUTLINE, TQFP, 7 X 7 MM BODY,
03/02 REV. F/443
Copyright 2002, EM Microelectronic-Marin SA
54
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EM6620
Figure 31 TQFP44 Package Dimensions
TOP VIEW
D
ODD LEAD SIDES
EVEN LEAD SIDES
e
b
D1
DETAIL "A"
e
SEE DETAIL "A"
S
Y
M
B
O
L
A
TQFP44
ALL DIMENSIONS IN MILLIMETERS
MIN.
TYP.
A1
SEE DETAIL "B"
DETAIL "B"
MAX.
1.6
A
0.05
0.15
1.4
A2
D
12.00 BSC.
D1
10.00 BSC.
1.45
0° MIN.
L
0.08/0.20 R.
A2
0.08
R. MIN.
0.20 MIN.
1.00 REF.
0.60
0.75
44
0.80 BSC
e
b
A1
0.45
N
0.30
0.37
0.45
0-7°
L
1.00/0.10 MM FORM, 1.4 MM THICK
PACKAGE OUTLINE, TQFP, 10X10 MM BODY,
© EM Microelectronic-Marin SA, 01/99, Rev. D/254
55
EM6620
20.1 Ordering Information
Packaged Device:
Device in DIE Form:
EM6620 %%% TQ32 B
EM6620 %%% WS 11
Customer Version:
customer-specific number
given by EM Microelectronic
Customer Version:
customer-specific number
given by EM Microelectronic
Package:
TQ32 = TQFP 32 pin
TQ44 = TQFP 44 pin
Die form:
WW = Wafer
WS = Sawn Wafer/Frame
WP = Waffle Pack
Thickness:
11 = 11 mils (280um), by default
27 = 27 mils (686um), not backlapped
(for other thickness, contact EM)
Delivery Form:
B = Tape&Reel
D = Trays (Plate)
Ordering Part Number (selected examples)
Part Number
Package/Die Form
EM6620%%%TQ32B
EM6620%%%TQ32D
EM6620%%%TQ44B
EM6620%%%TQ44D
EM6620%%%WS11
EM6620%%%WP11
EM6620%%%WW27
TQFP 32 pin
TQFP 32 pin
TQFP 44 pin
TQFP 44 pin
Sawn wafer
Die in waffle pack
Unsawn wafer
Delivery
Form/Thickness
Tape&Reel
Trays (Plate)
Tape&Reel
Trays (Plate)
11 mils
11 mils
27 mils
Please make sure to give the complete Part Number when ordering, including the 3-digit version. The version is made of 3
digits %%%: the first one is a letter and the last two are numbers, e.g. C05 , C12, P20, etc.
20.2 Package Marking
TQFP44 marking:
First line:
Second line:
Third line:
TQFP32 marking:
E M 6 6 2 0
0 % % Y
P P P P P P P P P P P
C C C C C C C C C C C
E M 6 6 2
P P P P P
C C C C C
0
P
Y
#
P
P
Where: %% = last two-digits of the customer-specific number given by EM (e.g. 05, 12, 20, etc.)
# = Last digit of the customer-specific number given by EM (e.g. 2, 4, 6, 8)
Y = Year of assembly
PP…P = Production identification (date & lot number) of EM Microelectronic
CC…C = Customer specific package marking on third line, selected by customer
20.3 Customer Marking
There are 11 digits available for customer marking on TQFP44.
There are 5 digits available for customer marking on TQFP32.
Please specify below the desired customer marking.
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than
circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves
the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure
that the information given has not been superseded by a more up-to-date version.
03/02 REV. F/443
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EM6620
21. Spec. Update
date ,name
Version
20/11/97 , JAG
B/156, Oct 97
20/11/97 , JAG
chapter
concerned
5.2
20/11/97 , JAG
16.1.5
20/11/97 , JAG
19/12/97, JAG
03/02/98, JAG
16/02/98, JAG
ALL
MSC
1.0
7.0
This means a worst case of
16ms(default) or 2ms (0.5ms) by
ck[14] corresponds to a maximum
0.5ms debouncing
new pagination
-
24/3/98, JAG
7.5.1
-
24/3/98, JAG
7.4
18.6.98, Jag
C/227, June 98
8.12.98 JAG
8.12.98 JAG
20.1.99 JAG
D/254 Feb 99
all
in 7.4 removed the phrase < One
must not use a compare value of hex
0 in upcount mode nor a value of hex
3FF (resp FF,3F, F if limited bit
compare) in downcount mode.>
new version in Doc Control
10
21
22
SVLD Level select in in RegSVLDL
TQFP44 Thickness 1.0mm
-
19.09.01 DIV
E/375 Sept 01
19.09.01 DIV
E/375 Sept 01
6.2.1
7.5
old text
new text
debouncer times are 2ms resp 0.5ms debouncer times are 2ms resp 0.25ms
15
18.4
01.11.01 PERT All
E/375
22.03.02
19 & 22
IVDDa, IVDDh, IVDDs Max. over
temperature change in 18.4 DC
characteristics.
-
This means a worst case of 16ms(default)
or 2ms (0.25ms) by
ck[14] corresponds to a maximum 0.5ms
debouncing
new detailed description + 1page
added marking for MFP programming
- included default marking for Up/Down
count mode and Load command
added < For limited pulse generation one
must
load the complementary pulse
number value. I.e for 5 pulses counting on
4 bits load bits[9 :4] with hex 3A (bin
111010).>
in 7.5 added the phrase <One must not
use a compare value of hex 0 in upcount
mode nor a value of hex 3FF (resp FF,3F,
F if limited bit compare) in downcount
mode. >
Spelling Corrections, Figure updates,
added Die size and Package drawings
SVLD Level select in in RegSVLDL
TQFP44 Thickness 1.4mm
Added the ordering information for
packaged devices inclusive device
marking and also ordering info for dies.
New testloop
18.4 DC Characteristics - Power Supply
Pins - new values for IVDDa, IVDDh,
IVDDs Max.
Change Header & footer, Add URL
mention
Change pad location diagram & ordering
information
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than
circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves
the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure
that the information given has not been superseded by a more up-to-date version.
03/02 REV. F/443
Copyright 2002, EM Microelectronic-Marin SA
57
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