EM MICROELECTRONIC - MARIN SA
EM6640
Low Power Microcontroller
with EEPROM AND RC Oscillator
Features
Figure 1 Architecture
• Low Power
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- 42µA active mode
- 8µA standby mode
- 0.3µA sleep mode
@ 3.0V, 600kHz, 25°C, typ
Voltage Range - 1.9 to 5.5 V
Supply voltage level detection (SVLD)
ROM
- 1280 × 16 bit
RAM
- 80 × 4 bit
EEPROM
- 32 x 8 bit
2 clocks per instruction cycle
72 basic instructions
RC oscillator
Oscillation detection circuit / Digital watchdog
timer reset.
Maximum 12 inputs (3 ports)
Maximum 8 outputs (2 ports)
Serial Write Buffer - 256 bits (SWB)
10 bit up/down counter with PWM capability
Frequency out 600kHz, 37.5kHz, 2.3kHz, PWM
Sleep Counter Reset (SCR) programmable.
8 internal interrupt sources (3×prescaler,
2×timer ,1xSWB, 1×SVLD, 1xEEPROM)
4 external interrupt sources (port A)
Reset with input combinations
Packages available : TSSOP16, SO16, SO18
Figure 2 Pin Configuration of TSSOP16
Description
The EM6640 is an advanced single chip CMOS 4-bit
microcontroller. It contains ROM, RAM, EEPROM,
watchdog timer, oscillation detection circuit, 10 bit
up/down counter, prescaler, supply voltage level
detector (SVLD), sleep counter reset (SCR),
frequency output and SWB.
The low voltage feature and low power consumption
make it the most suitable controller for battery, stand
alone and mobile equipment. The EM66XX series is
manufactured using EM Microelectronic’s Advanced
Low Power (ALP) CMOS Process.
Typical Applications
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remote controls
medical applications
domestic appliance
safety and security devices
measurement equipment
interactive system
keyless entry with rolling code
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EM6640
EM6640 at a glance
•
Power Supply
- Low voltage, low power architecture
including internal voltage regulator.
- 1.9V ... 5.5V battery voltage.
- 600 kHz RC oscillator.
- 42µA typical in active mode @ 3V, 25C°.
- 8µA typical in standby mode @ 3V, 25C°.
- 0.3µA typical in sleep mode @ 3V, 25C°.
•
RAM
- 80 x 4 bit, directly addressable.
•
ROM
- 1280 x 16 bit metal mask programmable.
•
EEPROM
- 32 x 8 bit, indirectly addressable (6 bits used to
adjust the oscillator frequency).
- Interrupt request at the end of writing operation.
- 60µA typical during read mode @ 3V, 25C°.
- 45µA typical during erase/write mode @ 3V, 25C°
•
CPU
- 4 bits RISC architecture.
- 2 clock cycles per instruction.
- 72 basics instructions.
•
Main Operating Modes and Resets
- Active mode (CPU is running).
- Standby mode (CPU in halt).
- Sleep mode (No clock, reset state).
- Initial reset on power on (POR).
- Watchdog timer (time out) reset.
- Oscillation detection watchdog reset.
- Reset with input combination.
•
4 Bits Input Port A
- Direct input read.
- Reset with input combination (register selectable).
- Debounced or direct input (register selectable).
- Interrupt request on input’s rising or falling
edge (register selectable).
- Pull-up, pull-down or none (register selectable).
- Software test variables for conditional jumps.
- PA[0] and PA[3] are input for the event counter.
•
4 Bits Input/Output Port B
- Input or Output port bitwise.
- Direct input read.
- CMOS or N-channel open drain outputs.
- Pull-up selectable in N-channel open drain mode.
- Pull-down or pull-up selectable by register.
- Selectable pulse width modulation (PWM).
- PWM output on PB[3].
- Output frequencies 600kHz, 37.5kHz, 2.3kHz.
•
4 Bits Input/Output Port C
- Input or output port bitwise.
- Direct input read.
- CMOS or N-channel open drain outputs.
- Pull-up selectable in N-channel open drain mode.
- Pull-down or pull-up selectable by register.
- Serial Write Buffer clock and data output.
•
Oscillator
- RC Oscillator at f=600kHz ±1% typ (-30°C...40°C).
- Absolute frequency adjustable with 6 bits EEPROM.
- No external components are necessary.
• Serial Write Buffer (SWB)
- Max. 256 bits long clocked with 150kHz; 75kHz
9.4kHz; 2,3kHz. External clock capability in
automatic mode, max: 1.5MHz.
- Automatic send mode: number of clocks of the last
nibble selectable by register and last data level
latched. External clock division capability by 1/1, 1/4,
1/88 and 1/352.
- Interactive send mode: interrupt request when buffer
is empty.
- Data sent at VDD or VregLogic levels selectable by
mask option.
•
Prescaler
- 19 stages system clock divider down to 1Hz.
- 3 interrupts requests: 9.4kHz; 586Hz and 1Hz.
- Prescaler reset.
•
Supply voltage Level Detector
- 2 levels software selectable (2,2V or 2,5V).
- Busy flag during measurement.
- Interrupt request when measurement is ready.
•
10-Bit Universal Counter
- 10, 8, 6, 4 bit up/down counting.
- 8 different input clocks.
- Event counting with PA[0] and PA[3] as input clocks.
- Full 10 bits or limited (8, 6, 4 bits) compare function.
- 2 interrupt requests (on compare and on 0).
- Pulse width modulation (PWM) output on PB[3].
•
Sleep Counter Reset (SCR)
- Wake up automatically the EM6640 from sleep.
- 8 timings selectable by register.
- Inhibit SCR by register.
•
Watchdogs
- Oscillation detection circuit.
- Digital watchdog timer reset.
•
Interrupt Controller
- 4 external interrupt sources from PortA.
- 5 internal interrupt sources: Prescaler (3),
Timer (2), SVLD (1), EEPROM (1), SWB (1)
NB: All frequencies written in this document are related to a typical system clock of 600 kHz.
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EM6640
INDEX
FEATURES
1. PIN DESCRIPTION FOR EM6640 :
2. OPERATING MODES
2.1
ACTIVE Mode
2.2
STANDBY Mode
2.3
SLEEP Mode
3. POWER SUPPLY
4. RESET
4.1
Power-Up
4.2
Oscillation Detection Circuit
4.3
Input-PortA-Reset
4.4
Sleep Counter Reset (SCR)
4.5
Digital Watchdog Timer Reset
4.6
CPU State after Reset
5. OSCILLATOR AND PRESCALER
5.1
Oscillator
5.2
Prescaler
6. INPUT AND OUTPUT PORTS
6.1
Ports overview
6.2
PortA
6.2.1
IRQ on portA
6.2.2
Pull-up/down
6.2.3
Software test variables
6.2.4
PortA for 10-bit Counter
6.2.5
PortA for serial write buffer (SWB)
6.3
PortA registers
6.4
PortB
6.4.1
Input / Output Mode
6.4.2
Pull-up/Down
6.4.3
CMOS / Nchannel Open Drain Output
6.4.4
PWM and Frequency output
6.5
PortB registers
6.6
PortC
6.6.1
Input / Output Mode
6.6.2
Pull-up/Down
6.6.3
CMOS / Nchannel Open Drain Output
6.6.4
Serial Write Buffer (SWB)
6.7
PortC registers
7. 10-BIT COUNTER
7.1
Full, Limited Bit Counting
7.2
Frequency Select and Up/Down Counting
7.3
Event Counting
7.4
Compare Function
7.5
Pulse Width Modulation (PWM) Generation
7.5.1
How the PWM generator works.
7.5.2
PWM characteristics
7.6
Counter setup
7.7
10-bit Counter Registers
8. SERIAL (OUTPUT) WRITE BUFFER - SWB
8.1
SWB Automatic send mode
8.1.1
SWB Automatic with external clock
31
8.1.2
How the SWB in automatic mode works
32
8.2
SWB Interactive send mode
33
8.2.1
How the SWB in interactive mode works
33
8.3
SWB registers
34
9. EEPROM
36
9.1
EEPROM registers
37
10.
INTERRUPT CONTROLLER
38
10.1
Interrupt control registers
39
11.
SUPPLY VOLTAGE LEVEL DETECTOR
40
11.1
Supply Voltage Level Detector Register
40
12.
RAM
41
12.1
RAM Extension
41
13.
PERIPHERAL MEMORY MAP
42
14.
OPTION REGISTER MEMORY MAP
45
15.
TEST AT EM - ACTIVE SUPPLY CURRENT TEST 46
16.
MASK OPTIONS
47
16.1
Input / Output ports
47
16.1.1
PortA Metal Options
47
16.1.2
PortB Metal Options
48
16.1.3
PortC Metal Options
49
16.2
Digital Watchdog Option
50
16.3
SWBdataLevel Option
50
16.4
Remaining metal mask options
50
16.5
Metal mask ordering
50
17.
TEMPERATURE AND VOLTAGE BEHAVIORS
51
17.1
RC oscillator (typical)
51
17.2
IDD Current (typical)
51
17.3
Regulated Voltage (typical)
52
17.4
Output Currents (typical)
52
17.5
Pull-up/down (typical)
54
18.
EM6640 ELECTRICAL SPECIFICATIONS
55
18.1
Absolute maximum ratings
55
18.2
Handling Procedures
55
18.3
Standard Operating Conditions
55
18.4
DC characteristics - Power Supply Pins
55
18.5
Supply Voltage Level Detector
56
18.6
Oscillator
56
18.7
Analogue filter on PortA
56
18.8
Sleep counter reset (SCR)
56
18.9
EEPROM
56
18.10
DC characteristics - input / output Pins
57
18.11
DC characteristics - pull up/down
58
19.
PAD LOCATION DIAGRAM
59
20.
PACKAGE & ORDERING INFORMATION
59
20.1
Ordering Information
61
20.2
Package Marking
61
20.3
Customer Marking
61
21.
UPDATES OF SPECIFICATIONS
62
1
3
4
5
5
5
5
6
7
8
9
10
11
12
13
13
14
15
15
16
16
17
17
17
17
17
19
19
19
20
20
21
22
22
22
23
23
23
24
24
25
26
26
26
27
27
27
28
30
31
1. Pin Description for EM6640 :
Pin Number Pin Name
1
VReg
Function
Internal voltage regulator
Remarks
MFP programming connection
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EM6640
2
Test
Input test terminal
3
Port A[0]
Input port A[0]
4
5
6
7
Port A[1]
Port A[2]
Port A[3]
Port B[0]
8
Port B[1]
9
Port B[2]
10
Port B[3]
11
Port C[0]
12
Port C[1]
13
Port C[2]
14
Port C[3]
15
VBat
Input port A[1]
Input port A[2]
Input port A[3]
Input/Output bitwise,
cmos/open drain port B[0]
Input/Output bitwise,
cmos/open drain port B[1]
Input/Output bitwise,
cmos/open drain port B[2]
Input/Output bitwise,
cmos/open drain port B[3]
Input/Output bitwise,
cmos/open drain port C[0]
Input/Output bitwise,
cmos/open drain port C[1]
Input/Output bitwise,
cmos/open drain port C[2]
Input/Output bitwise,
cmos/open drain port C[3]
Positive power supply terminal
16
VSS
Negative power supply terminal
For EM test purpose only, GND 0 !
And MFP programming connection
testvar1, event counter input, IRQPA[0],
SWB input clock
testvar2, IRQPA[1]
IRQPA[2]
event counter input, IRQPA[3]
ck[20] output
ck[16] output
ck[12] output
PWM output
SWB Clock Out
SWB Data Out
VBat=VDD, MFP programming
connection
reference terminal, MFP programming
connection
Figure 3 Typical configuration
VBat
PortA
VReg
PortB
EM6640
CVreg
+
C1
Test
PortC
VSS
2. Operating modes
The EM6640 has two low power dissipation modes, STANDBY and SLEEP. Figure 4 is a transition diagram for
these modes.
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EM6640
2.1 ACTIVE Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Go into standby mode via the halt instruction or go into sleep mode by writing the sleep bit.
2.2 STANDBY Mode
Executing a HALT instruction puts the EM6640 into
STANDBY mode. The voltage regulator, oscillator,
watchdog timer, interrupts and timers/counters are
operating. However, the CPU stops since the clock
related to instruction execution stops. Registers,
RAM and I/O pins retain their states prior to
STANDBY mode. STANDBY is canceled by a
RESET or an Interrupt request if enabled.
2.3 SLEEP Mode
Writing the Sleep bit in the RegSysCntl1 register
puts the EM6640 in SLEEP mode. The oscillator
stops and most functions of the EM6640 are
inactive. To be able to write the Sleep bit, the
SleepEn bit in RegSysCntl2 must first be set to "1".
In SLEEP mode only the voltage regulator is active.
The RAM data integrity is maintained. SLEEP mode
may be canceled only by the Input Reset from PortA
or the Sleep Counter Reset.
Figure 4 Mode transition diagram
ACTIVE
HALT
Instruction
SLEEP bit
write
IRQ
STANDBY
SLEEP
RESET=0
RESET=1
RESET=1
RESET=1
RESET
During SLEEP mode and the following start up the EM6640 is in reset state. Waking up from SLEEP mode clears
the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to determine if the EM6640 was powered
up (SleepEn = "0") or woken up from SLEEP mode (SleepEn = "1").
The bit NoInputRes in option register OptPaRst is inhibited is sleep mode.
TAKE CARE !!! To quit SLEEP mode, one must be sure to have a suitable defined combination of PortA inputs
for reset (see section 4.3).
Table 2.3.1 shows the state of the EM6640 functions in STANDBY and SLEEP modes
FUNCTION
Oscillator
Oscillator Watchdog
Instruction Execution
Interrupt Functions
Registers and Flags
EEPROM
RAM data
Option Registers
Timer/Counter's
Logic Watchdog
Input PortA
I/O Port B
I/O Port C
SCR
SWB
Voltage Level Detector
STANDBY
Active
Active
Stopped
Active
Retained
Retained
Retained
Retained
Active
Active
Active
NoInputRes = "0"
Active
Active
Stopped
Active
finishes on going measure, then stop
SLEEP
Stopped
Stopped
Stopped
Stopped
Reset
Retained
Retained
Retained
Reset
Reset
Active
NoInputRes = "x"
High Impedance, no pulls
High Impedance, no pulls
Active if enable
Stopped
Stopped
3. Power Supply
The EM6640 is supplied by a single external power supply between VDD (VBat) and VSS (GND). A built-in
voltage regulator generates VregLogic providing regulated voltage for the oscillator and the internal logic. An
external capacitor (CVreg) has to be put on Vreg terminal (see Standard Operating Conditions, on page 55).
Vreg terminal is not intended to be used with external load except CVreg.
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EM6640
The output drivers are supplied directly from the external supply VDD.
4. Reset
Figure 5 illustrates the reset structure of the EM6640. One can see that there are six possible reset sources:
(1) Internal initial reset from the Power On Reset (POR) circuitry.
(2) External reset by simultaneous high/low inputs to PortA.
(Combinations are defined in the registers OptInpRSel1 and OptInpRSel2
(3) Internal reset from the Digital Watchdog.
(4) Internal reset from the Oscillation Detection Circuit.
(5) Internal reset when SLEEP mode is activated.
(6) Internal reset from Sleep Counter Reset.
All reset sources activate the System Reset and the Reset CPU. The ‘System Reset Delay’ ensures that the
System Reset remains active long enough for all system functions to be reset (active for N SysClk cycles).
The ‘CPU Reset Delay‘ ensures that the Reset CPU remains active until the oscillator is in stable oscillation.
As well as activating the System Reset and the Reset CPU, the POR also resets all Option Registers and the
SLEEP ENABLE latch. System Reset and Reset CPU do not reset Option Registers nor the SLEEP ENABLE
latch.
Figure 5. Reset structure
Internal D ata Bus
W rite R eset
R ead Status
Digital W atchdog
CK[1]
W rite Activ e
R ead Status
SLEEP
ENABLE
Latch
SLE EP
Latch
R
R
Inhibit
D igital
W atchdog
C P U R eset
Delay
ck[11]
Reset
CP U
R eset
set
POR
Sleep
Sleep Counter
R eset
Inhibit
S CR
A nalog
D ebouncer
D E B O U N CE R
(for reset)
EN
S ystem R eset
D elay
ck[10]
POR
PO R to O ption
R egisters & S LEEP
ENAB LE latch
C K[10]
O scillation
D etection
System
R eset
ck[18]
Inhibit
O scillation
detection
R eset from PortA Input
com bination
N oInpR eset
Sleep
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EM6640
4.1 Power-Up
At power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry, and
thus the System Reset. The CPU of the EM6640 remains in the reset state for the ‘CPU Reset Delay’, to allow
the oscillator to stabilize after power up.
Because the oscillator is disabled during SLEEP mode, then when waking up from SLEEP mode, the CPU of the
EM6640 remains in the reset state for the ‘CPU Reset Delay’ also to allow the oscillator to stabilize.
The ‘CPU Reset Delay’ is 512 system clocks (ck[11]) long.
VDD
V re g L o g
1
nPO R
R C osc
C k [1 1 ]
2
S y s te m R e s e t
3
C P U R eset
1
2
3
W h e n V re g L o g le v e l re a c h e s a p p r o x . 1 .3 v , th e p o w e r o n re s e t c irc u it
re m o v es n P O R .
T h e o s c illa to r s ta rts to ru n to s u p p ly a c lo c k s ig n a l to th e re s e t
s y n c h ro n is e r a n d th e p re s c a le r b lo c k s . A f te r 1 6 o s c illa to r c lo c k c y c le s ,
th e s y s te m R e s e t is re m o v e d .
A f ter 5 1 2 o s c illa to r c lo c k c y c le s , th e re is a f a llin g e d g e o f c k [1 1 ] a n d th e
C P U R es et is re m o v e d .
Figure 6 Power On Startup
S y s tem R es et
1
R es et s o u rc e: P o rtA res et,
d ig ita l w a tc h d o g , o s c illa tio n
d etec tio n c irc u it.
2
R es et s o u rc e: P O R , s leep ,
s leep c o u n ter res et (S C R ).
C P U R es et D ela y
C P U R es et
1
2
Figure 7 CPU Reset Delay (Coldstart)
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EM6640
4.2 Oscillation Detection Circuit
In ACTIVE or STANDBY modes, the Oscillator Detection Circuit monitors the oscillator. If it stops for any reason,
a reset is generated for the ‘CPU Reset Delay’.
The oscillation detection circuitry can be inhibited with NoOscWD = 1 in register RegSysCtl3. At power up, and
after any Reset, the function is activated.
During the CPU reset, the Oscillation Detection Circuit is inhibited because the oscillator is either off or in a
stabilization period. Then, it will be active.
For the electrical specifications, see section : EM6640 Electrical specifications.
Table 4.2.1 Watchdog timer register RegSysCntl3
Bit
Name
Reset
3
--2
--1
NoOscWD
0
0
NoLogicWD
0
R/W
Description
R/W
R/W
No oscillator watchdog
No logic watch dog
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EM6640
4.3 Input-PortA-Reset
By writing the OptInpRSel1 and OptInpRSel2 registers it is possible to choose any combination of PortA input
values to execute a system reset. The reset condition must be valid for at least 3.4mS (2 risings edges of ck[10]
with system clock = 600kHz) in ACTIVE and STANDBY mode.
When canceling the SLEEP mode, the debouncer is not active (oscillator off). However, the reset condition
passes through an analogue filter. The constant time is defined on the section EM6640 Electrical specifications,
on page 56. In this case, the reset condition must be at least two times this constant time (In ACTIVE and
STANDBY mode, the analogue filter is inhibited). The reset is generated for the ‘CPU Reset Delay’
Bit SelInpResMod in option register OptPaRst selects which kind of input reset modes will be used: through an
″OR logic″ or an ″AND logic″ (default at power on). With the first mode, at least one input matching its reset
condition will trigger a system reset. With the second mode, it is necessary to fully match the reset combination
chosen in the registers.
Bit NoInputReset in option register OptPaRst selects the Input-PortA-Reset function in ACTIVE and STANDBY
Mode. If set to "0" (default at power on) the occurrence of the selected combination for Input-PortA-Reset will
trigger a system reset. Set to ‘1’ the Input PortA Reset function is inhibited. This option bit has no action in SLEEP
Mode, where the occurrence of the selected Input-PortA-Reset combination will always immediately trigger a
system reset.
Reset combination selection (InpReset) in registers OptInpRSel1 and OptInpRSel2.
SelinpResMod = 0 =>
SelinpResMod = 1 =>
InpReset = InpResPA[0] • InpResPA[1] • InpResPA[2] • InpResPA[3]
InpReset = InpResPA[0] + InpResPA[1] + InpResPA[2] + InpResPA[3]
SelinpResMod = 0
0InpRes1PA[ InpRes2PA[n] InpResPA[n]
n]
0
0
VSS
0
1
PA[n]
1
0
not PA[n]
1
1
VDD
n = 0 to 3
i.e. ; - No reset if InpResPA[n] = VSS.
- With InpResPA[n] = VDD, concerning
terminal [n] inhibited.
- Always Reset if InpResPA[3:0] = 'b1111.
Figure 8.Input PortA Reset structure
InpResPA
BIT
[0]
Input PortA Reset
Bit[0] selection
BIT
[1]
Input PortA Reset
Bit[1] selection
BIT
[2]
Input PortA Reset
Bit[2] selection
BIT
InpRes1PA[3]
[3]
SelinpResMod = 1
InpRes1PA[n] InpRes2PA[n] InpResPA[n]
0
0
VSS
0
1
PA[n]
1
0
not PA[n]
1
1
VDD
n = 0 to 3
i.e. ; - No reset if InpResPA[3:0] = 'b0000.
- With InpResPA[n] = VSS, concerning
terminal [n] inhibited.
- Always Reset if InpResPA[n] = VDD.
InpRes2PA[3]
Input PortA Reset
Bit[3] selection
VSS
PA[3]
PA[3]
VDD
0
1 MUX
2
3 1 0
InpResPA[3]
Input
Reset
from
PortA
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EM6640
4.4 Sleep Counter Reset (SCR)
The Sleep Counter Reset, active only in SLEEP mode, will automatically trigger a reset which cancels Sleep Mode
after a programmable time defined by writing bit RstSlpTSel[2:0] in option register OptSlpCntRst. The
EnSlpCntRst bit in option register OptSlpCntRst set to "1" will enable the SCR as soon as the SLEEP bit in
RegSysCntl1 is written active. In this case, all the sleep considerations (low consumption) are taken into account
(refer to chapter SLEEP Mode, page 5 for more details). When the SCR generates a reset, the CPU reset is
removed after the ‘CPU Reset Delay’.
The typical time constant of SCR is defined in the section EM6640 Electrical specifications, on page 55.
=> The minimum programmable time is 1x the time constant.
=> The maximum programmable time is 128x the time constant.
Figure 9 Sleep Counter Reset representation with SCR timing=2x as an example.
S y s C lk
S le e p
C P U re s e t
SCR
a c tiv e m o d e
Table 10 register OptSlpCntRst
Bit
Name
3
EnSlpCntRst
2
RstSlpTSel[2]
1
RstSlpTSel[1]
0
RstSlpTSel[0]
S le e p m o d e
S C R tim in g = 2 x
Reset
0
0
0
0
C P U R s t D e la y a c tiv e m o d e
R/W
R/W
R/W
R/W
R/W
Description
enable SCR
timing selection
timing selection
timing selection
Table 11 Sleep Counter Reset timing
RstSlpTSel[2]
RstSlpTSel[1] RstSlpTSel[0]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
SCR timing
1x
2x
4x
8x
16x
32x
64x
128x
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4.5 Digital Watchdog Timer Reset
The Digital Watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of CK[1]. It will
generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by activating
an inhibit digital watchdog bit (NoLogicWD) located in RegSysCtl3. By metal 1 mask option, one can force the
Digital Watchdog to be always active, this mean that the bit NoLogicWD has no more effect (see: Digital
Watchdog Option, page 50). In that case, the read of the bit NoLogicWD will always give ‘0’. By default, the
Digital Watchdog can be controlled by the register RegSysCtl3. At power up, and after any System Reset, the
watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the System Reset
signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the
watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 600kHz), or a
System Reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and timer
operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer operates
also in the STANDBY mode and thus, to avoid a System Reset, STANDBY should not be active for more than 2.5
seconds.
From a System Reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog
timer is reset at any other time, then it could become active after just 2.5 seconds. In addition, using the
Prescaler reset function can lower this minimum watchdog time. It is therefore recommended to use the Prescaler
IRQ1Hz interrupt to periodically reset the watchdog every one second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the counting
sequence is (on each rising edge of CK[1]) : {WDVal1 WDVal0} ‘00’, ‘01’, ‘10’, ‘11’. When in the ‘11’ state, the
watchdog reset will be active within ½ second. The watchdog reset activates the system reset which in turn
resets the watchdog. If the watchdog is inhibited its timer is reset and therefore always reads ‘0’.
Table 4.5.1 Watchdog timer register RegSysCntl2
Bit
Name
Reset
R/W
3
WDReset
0
R/W
2
1
0
SleepEn
WDVal1
WDVal0
0
0
0
Description
Reset the Watchdog
1 -> Resets the Logic Watchdog
0 -> no action
The Read value is always '0'
see Operating modes (sleep)
Watchdog timer data 1/4 ck[1]
Watchdog timer data 1/2 ck[1]
R/W
R
R
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EM6640
4.6 CPU State after Reset
Reset initializes the CPU as shown in Table below.
Table 4.6.1 Initial CPU value after Reset.
Name
Bits
Program counter 0
12
Program counter 1
12
Program counter 2
12
stack pointer
2
index register
7
Carry flag
1
Zero flag
1
Halt
1
Instruction register
16
Periphery registers
4
Symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
Reg.....
Initial Value
$000 (as a result of Jump 0)
undefined
undefined
SP[0] selected
undefined
undefined
undefined
0
Jump 0
see peripheral memory map
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5. Oscillator and Prescaler
5.1 Oscillator
An RC oscillator generates the system operating clock for the CPU and peripheral circuits. The frequency can be
adjusted if necessary by ∼±32% in steps of ∼1% by writing bits OscAdj[5:0] in the registers OPTPaRST and
OPTOscAdj. The adjustable frequency range allowed is specified on page 55 (If you have a special request
please contact EM Microelectronic Marin SA).
At power up, the default frequency is the lowest. The frequency is stored by adjusting the 6 bits in the EEPROM
and transferring them to the registers OPTPaRST and OPTOscAdj. To increase frequency, put a higher
calibration values and to decrease it, put a lower calibration values.
The adjustment value of the oscillator is written at EM-Marin at the last address of the EEPROM. By reading these
6 EEPROM bits and writing the contents to the registers OPTOscAdj and OPTPaRST, the delivery state will be
600kHz typical. See also section: EM6640 Electrical specifications, page 55.
Frequency adjustment procedure (example):
- 1st: selecting ck[20] output on PB[0] with the bit PB600kHzOut in register OPTFSelPB.
- 2nd: measure the output frequency with a frequency meter.
- 3rd: if it is not the desired frequency, modify the 6 bits dedicated to the RC oscillator in the registers OPTOscAdj
and OPTPaRST.
- 4th: return to the point 2 until desired frequency is obtained.
- 5th: write the contents of the registers OPTOscAdj and OPTPaRST (2 MSB) to the EEPROM.
- (6th:read these 6 EEPROM bits and write the contents to the registers OPTOscAdj and OPTPaRST.)
The above procedure should be followed for the initial adjustment (first POR). For subsequent initializations the
calibration values can be read from the EEPROM (start from point 6). It is not necessary to do this after any other
resets (The values of the Option Registers are set by initial reset on power up and through write operations only).
To guarantee the good functionality of the whole circuit, it is recommended to adjust operating clock at 600 kHz.
User can decide himself which EEPROM address to use for the RC oscillator data if the last EEPROM address
can not be kept.
Three different frequencies can be provided on the PortB[2:0] terminals (see section: PWM and Frequency
output, on page 20). The highest is 600kHz which comes directly from the RC oscillator. The two others, 37.5kHz
and 2.3kHz, come from the prescaler.
The oscillator circuit is supplied by the regulated voltage, VregLogic. In SLEEP mode the oscillator is stopped.
No external components are necessary.
Table 5.1.1 register OPTPaRST
Bit
Name
3
2
1
0
power on
value
R/W
Description
0
0
0
0
R/W
R/W
R/W
R/W
Adjustment of RC oscillator in EEPROM (MSB)
Adjustment of RC oscillator in EEPROM
input reset mode (Or or AND logic)
PortA input reset option
OscAdj[5]
OscAdj[4]
SelinpResMod
NoInputReset
Default ″0″ is : no adjustment of the frequency
Table 5.1.2 register OPTOscAdj
Bit
Name
3
2
1
0
power on
value
R/W
Description
0
0
0
0
R/W
R/W
R/W
R/W
Adjustment of RC oscillator in EEPROM
Adjustment of RC oscillator in EEPROM
Adjustment of RC oscillator in EEPROM
Adjustment of RC oscillator in EEPROM (LSB)
OscAdj[3]
OscAdj[2]
OscAdj[1]
OscAdj[0]
Default ″0″ is : no adjustment of the frequency
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5.2 Prescaler
The input to the prescaler is the system clock signal. The prescaler consists of nineteen elements divider chain
which delivers clock signals for the peripheral circuits such as timer/counter, debouncers and edge detectors, as
well as generating prescaler interrupts. Power on initializes the prescaler to $0000.
Table 5.2.1 Prescaler clock name definition
function
system clock
system clock / 2
system clock / 4
system clock / 8
system clock/ 16
system clock / 32
system clock / 64
system clock / 128
system clock / 256
system clock / 512
name
ck[20]
ck[19]
ck[18]
ck[17]
ck[16]
ck[15]
ck[14]
ck [13]
ck [12]
ck[11]
value
600000 Hz
300000 Hz
150000 Hz
75000 Hz
37500 Hz
18750 Hz
9375 Hz
4688 Hz
2344 Hz
1172 Hz
function
system clock / 1024
system clock / 2048
system clock / 4096
system clock / 8192
system clock / 16384
system clock / 32768
system clock / 65536
system clock / 131072
system clock / 262144
system clock / 524288
1
0
Name
PWMOn
ResPresc
DebSel
Reset
0
0
0
0
R/W
R/W
R/W
R
R/W
value
586 Hz
293 Hz
146 Hz
73 Hz
37 Hz
18 Hz
9.2 Hz
4.6 Hz
2.3 Hz
1.1 Hz
Figure 12. Prescaler frequency timing
Table 5.2.2 Control of prescaler register RegPresc
Bit
3
2
name
ck[10]
ck[9]
ck[8]
ck[7]
ck[6]
ck[5]
ck[4]
ck[3]
ck[2]
ck[1]
Description
see 10 bit counter
Write Reset prescaler
1 -> Resets the divider chain
from ck[17] down to
ck[1]
0 -> no action.
Prescaler Reset
System clock
ck[20]
ck[19]
ck[17]
The Read value is always '0'
The Read value is always '0'
Debouncer clock select.
0 -> debouncer with ck[8]
1 -> debouncer with ck[17]
Horizontal Scale Change
ck[2]
ck[1]
First Positive Edge of ck[1] clock comes
one period after falling reset edge.
The Prescaler contains 3 interrupt sources:
- IRQ9k4Hz ; this is ck[14] positive edge interrupt.
- IRQ586Hz ; this is ck[10] positive edge interrupt.
- IRQ1Hz ; this is ck[1] positive edge interrupt.
Figure 13. Prescaler Interrupts example:
ck[2]
There is no interrupt generation on reset.
In reset mode, ck[1] is set to a high level.
The first IRQ1Hz Interrupt occurs ∼1sec (600kHz)
after reset.
ck[1]
IR Q 1Hz
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EM6640
6. Input and Output ports
The EM6640 has:
- one 4-bit input port ( PortA )
- two 4-bit input/output ports. ( PortB & PortC )
6.1 Ports overview
Table 6.1.1 Input and Output ports overview
Port
Mode
PA
Input
[3:0]
Mask(M:) or Register(R:)
option
M: Pull-up
M: Pull-down (default)
R: Pull(up/down) select
R: Debounced or direct
input for IRQ request
and Counter
R: + or - for IRQ-edge
and Counter
R: Input reset
combination
Function
Bitwise Multi Function on Ports
-Input
-Bitwise Interrupt request
-PA[3],PA[0] input for the
Event Counter
-Software Test Variable
conditional jump
-PortA Reset inputs
-SWB external input clock
PA[3]
PA[2]
PA[1]
PA[0]
IRQPA3
IRQPA2
IRQPA1
IRQPA0
-
-
10 bit
Event
Counter
clock
10 bit
Event
Counter
clock
Test
Var2
Test
Var1
SWB
CkExt
PB
bitwise R: CMOS or
[3:0] input or
Nch open drain output
output R: Pull-Down on input
R: Pull-Up on input
-Input or Output
-PB[3] for the PWM
output
-PB[2:0] for the ck[20,16,
12] output
-Tristatable in sleep mode
PC bitwise R: CMOS or
[3:0] input or
Nch open drain output
output R: Pull-Down on input
R: Pull-Up on input
-Input or Output
-PC[1:0] for the SWB
-Tristatable in sleep mode
PB[3]
PB[2]
PB[1]
PB[0]
PWM
output
ck[12]
output
ck[16]
output
ck[20]
output
PC[3]
PC[2]
PC[1]
PC[0]
SWB
Data
out
SWB
Clock
out
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6.2 PortA
The EM6640 has one four bit general purpose CMOS input port. The PortA input can be read at any time, pull-up
or pull-down resistors can be chosen by metal mask. All selections concerning PortA are bitwise executable. I.e.
Pull-up on PA[2], pull-down on PA[0], positive IRQ edge on PA[0] but negative on PA[1], etc.
In SLEEP mode the PortA inputs are continuously monitored to match the input reset condition which will
immediately wake the EM6640 from SLEEP mode. The pull-up or pull-down resistors remain active as defined in
the option register.
Figure 14. Input PortA configuration
NoDebIntPA[n]=1
VBAT
(VDD)
IntEdgPA[n]=0
SWB CkExt
Mask opt
MPAPU[n]
IRQPA[3:0]
PA[n]terminal
PA0, PA3
for 10-bit
Counter
Debouncer
(for port A)
Mask opt
MPAPD[n]
ck[8]
Input
combinations
ck[17]
Analog
debouncer
Sleep
control
µP TestVAR
DB[3:0]
VSS
NoPull[n]
6.2.1 IRQ on portA
For interrupt request generation (IRQ) one can choose direct or debounced input and positive or negative edge
IRQ triggering. With the debouncer selected ( OPtDebIntPA ) the input must be stable for two rising edges of the
selected debouncer clock ck[8] (default) or ck[17] (RegPresc), this means a worst case of 14mS (default) or 27µs
with a system clock of 600kHz.
Either a positive or a negative edge on the PortA inputs - after debouncer or not - can generate an interrupt
request. This selection is done in the option register OPTIntEdgPA.
All four bits of PortA can provide an IRQ, each pin with its own interrupt mask bit in the RegIRQMask1 register.
When an IRQ occurs, inspection of the RegIRQ1, RegIRQ2 and RegIRQ3 registers allow the interrupt to be
identified and treated.
At power on or after any reset the RegIRQMask1 is set to 0, thus disabling any input interrupt. A new interrupt is
only stored with the next active edge after the corresponding interrupt mask is cleared. See also the interrupt
chapter 10.
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6.2.2 Pull-up/down
Each of the input port terminals PA[3:0] has a resistor integrated which can be used either as pull-up or pull-down
resistor, depending on the selected metal mask options. See Table 6.2.1 and the PortA metal mask chapter for
details. The pull resistor can be inhibited using the NoPullPA[n] bits in the register OptNoPullPA.
Table 6.2.1 Pull-up or pull-down resistor on PortA select
opt mask pull-up
opt mask pull-down
NoPullPA[n] value
MPAPU[n]
MPAPD[n]
no
no
x
no
yes
0
no
yes
1
yes
no
0
yes
no
1
yes
yes
x
Action
with
n=0...3
no pull-up, no pull-down
no pull-up, pull-down
no pull-up, no pull-down
pull-up, no pull-down
no pull-up , no pull-down
not allowed*
* only pullup or pulldown may be chosen on any PortA terminal (one choice is excluding the other)
Any PortA input must never be left open (high impedance state, not connected, etc. ) unless the internal pull
resistor is in place (mask option) and switched on (register selection). Any open input may draw a significant cross
current which adds to the total chip consumption.
6.2.3 Software test variables
The PortA terminals PA[3:0] are also used as input conditions for conditional software branches. Independent of
the OPtDebIntPA and the OPTIntEdgPA these CPU inputs are always debounced and non-inverted.
- debounced PA[0] is connected to CPU TestVar1
- debounced PA[1] is connected to CPU TestVar2
6.2.4 PortA for 10-bit Counter
The PA[0] and PA[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count" mode.
As for the IRQ generation one can choose debounced or direct input with the register OPtDebIntPA and noninverted or inverted input with the register OPTIntEdgPA. Debouncer input is recommended when using PA[3] or
PA[0] for the event counting.
6.2.5 PortA for serial write buffer (SWB)
The PA[0] can be used as the external clock input terminal for the SWB in automatic mode. Depending of the
register RegSWBCntl2 contents, this external clock can be divided by 1/1, 1/4, 1/88 or 1/352.
As for the IRQ generation one can choose debounced or direct input with the register OPtDebIntPA and noninverted or inverted input with the register OPTIntEdgPA.
6.3 PortA registers
Table 6.3.1 register RegPA
Bit
Name
3
PAData[3]
2
PAData[2]
1
PAData[1]
0
PAData[0]
direct read on pin
Reset
-
R/W
R
R
R
R
Description
PA[3] input status
PA[2] input status
PA[1] input status
PA[0] input status
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Table 6.3.2 register RegIRQMask1
Bit
Name
Reset
R/W
3
MaskIRQPA[3]
0
R/W
2
MaskIRQPA[2]
0
R/W
1
MaskIRQPA[1]
0
R/W
0
MaskIRQPA[0]
0
R/W
Default "0" is: interrupt request masked, no new request stored
Description
interrupt mask for PA[3] input
interrupt mask for PA[2] input
interrupt mask for PA[1] input
interrupt mask for PA[0] input
Table 6.3.3 register RegIRQ1
Bit
Name
Reset
R/W
Description
3
IRQPA[3]
0
R/W*
interrupt request on PA[3]
2
IRQPA[2]
0
R/W*
interrupt request on PA[2]
1
IRQPA[1]
0
R/W*
interrupt request on PA[1]
0
IRQPA[0]
0
R/W*
interrupt request on PA[0]
W*; Write "1" clears the bit, write "0" has no action, Default "0" is: No Interrupt request
Table 6.3.4 register OPTIntEdgPA
Bit
Name
power on
value
3
IntEdgPA[3]
0
2
IntEdgPA[2]
0
1
IntEdgPA[1]
0
0
IntEdgPA[0]
0
Default "0" is: Positive edge selection
R/W
Description
R/W
R/W
R/W
R/W
interrupt edge select for PA[3]
interrupt edge select for PA[2]
interrupt edge select for PA[1]
interrupt edge select for PA[0]
Table 6.3.5 register OPTDebIntPA
Bit
Name
power on
R/W
value
3
NoDebIntPA[3]
0
R/W
2
NoDebIntPA[2]
0
R/W
1
NoDebIntPA[1]
0
R/W
0
NoDebIntPA[0]
0
R/W
Default "0" is: Debounced inputs for interrupt generation
Description
interrupt debounced for PA[3]
interrupt debounced for PA[2]
interrupt debounced for PA[1]
interrupt debounced for PA[0]
Table 6.3.6 register OPTNoPullPA
Bit
Name
power on
R/W
Description
value
3
NoPullPA[3]
0
R/W
pull-up/down selection on PA[3]
2
NoPullPA[2]
0
R/W
pull-up/down selection on PA[2]
1
NoPullPA[1]
0
R/W
pull-up/down selection on PA[1]
0
NoPullPA[0]
0
R/W
pull-up/down selection on PA[0]
Default "0" is: see Table 6.2.1 Pull-up or pull-down resistor on PortA select
Table 6.3.7 Register OPTPaRST
Bit
Name
3
2
1
0
power on
value
R/W
Description
1
0
0
0
R/W
R/W
R/W
R/W
Adjustment of RC oscillator in EEPROM (MSB)
Adjustment of RC oscillator in EEPROM
PortA input reset option
input reset mode (Or or AND logic)
OscAdj[5]
OscAdj[4]
SelinpResMod
NoInputReset
Default ″0″ is : bit[0] PortA can reset the EM6640, bit[1] input reset mode: AND logic
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6.4 PortB
The EM6640 has two four bit general purpose I/O ports: PortB and PortC. Each bit can be configured individually
(bitwise port) by software for input/output, pull-up, pull-down, CMOS/Nchannel Open Drain output, Frequency or
PWM output. The PortB has two high current output pads: PB[2:1].
6.4.1 Input / Output Mode
Each PortB terminal can be either input or output. These modes can be set by writing the corresponding bit in the
RegPBCntl control register. The RegPBData register contains the data written to the PortB terminal in output
mode. To set for input (default), 0 is written to the corresponding bit of the RegPBCntl register which results in a
high impedance state for the output driver. The output mode is set by writing 1 in the control register, and
consequently the output terminal follows the status of the bits in the RegPBData register. The PortB terminal
status can be read in any mode (read at address of RegPBData).
During SLEEP and Reset mode, PB[3:0] is in high impedance state with no pulls up/down active. Except during a
read phase on PortB (in active mode), all the PortB inputs are cut off (blocked).
Figure 15. PortB architecture
P u lld o w n
O p tio n R e g is te r
In te r n a l D a ta B u s
P d [n ]
P o r tB d ir e c tio n R e g
D D R [n ]
SLEEP
P o rt B
C o n tr o l
P o r tB d a ta R e g
D R [n ]
O p e n D r a in
O p tio n R e g is te r
O D [n ]
A c tiv e P u llu p if
O p e n D r a in
M ode
m a s k o p t io n
M P B P D [n ]
MUX
I / O T e r m in a l
M u ltip le x e d
O u tp u ts a r e :
P W M , C K [2 0 ],
C K [1 6 ], C K [1 2 ]
M u ltip le x e d
O u tp u t
P B [n ]
m a s k o p t io n
M P B P D [n ]
M u ltip le x e d
O u tp u t A c tiv e
RD
D B [n ]
A c tiv e
P u lld o w n
n R D P B [3 :0 ]
S le e p
6.4.2 Pull-up/Down
For each terminal of PB[3:0] an input pull-up (metal mask MPBPU[n]) or pull-down (metal mask MPBPD[n])
resistor can be implemented per metal mask option. Per default the two metal masks are in place, so one can
chose per software to have either a pull-up, a pull-down or no resistor.
For Metal mask selection and available resistor values refer to chapter ‘PortB Metal Options’.
Pulldown ON : MPBPD[n] must be in place ,
AND the bit NoPdPB[n] must be ‘0’ .
Pulldown OFF : MPBPD[n] is not in place,
OR if MPBPD[n] is in place NoPdPB[n] = ‘1’ cuts off the pulldown.
OR selecting NchOpDPB[n] = ‘1’ cuts off the pulldown.
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Pullup ON
: MPBPU[n] must be in place,
AND the bit NchOpDPB[n] must be ‘1’ ,
AND the bit PBIOCntl[n] = ‘0’ (input mode) OR if PBIOCntl[n] = ‘1’ while PBData[n] = 1.
Pullup OFF
: MPBPU[n] is not in place,
OR if MPBPU[n] is in place NchOpDPB[n] = ‘0’ cuts off the pullup,
OR if MPBPU[n] is in place and if NchOpDPB[n] = ‘1’ then PBData[n] = 0 cuts off the pullup.
Never can pull-up and pull-down be active at the same time.
For POWER SAVING one can switch off the PortB pull resistors between two read phases. No cross current flows
in the input amplifier while the PortB is not read. The recommended order is :
• switch on the pull resistor.
• allow sufficient time - RC constant - for the pull resistor to drive the line to either VSS or VDD.
• Read the PortB
• Switch off the pull resistor
Minimum time with current on the pull resistor is 4 periods of the system clock, if the RC constant is lower than 1
system clock period. Adding a NOP before reading moves the number of periods with current in the pull resistor
to 6 and the maximum RC delay to 3 clock periods.
6.4.3 CMOS / Nchannel Open Drain Output
The PortB outputs can be configured as either CMOS or Nchannel Open Drain outputs. In CMOS both logic ‘1’
and ‘0’ are driven out on the terminal. In Nchannel Open Drain only the logic ‘0’ is driven out on the terminal, the
logic ‘1’ value is defined by the pull-up resistor (if existing).
Figure 16. CMOS or Open Drain outputs
O pen Drain O utput
C M O S O utput
A ctiv e P ullup
for H igh S tate
MUX
D R [n]
F requency
O utputs
1
D ata
I/O
T erm inal
P B [n]
T ri-S tate O utput
B uffer : closed
MUX
I/O
T erm inal
D R [n]
F requency
O utputs
T ri-S tate O utput
B uffer : H igh
Im pedance for
D ata = 1
P B [n]
6.4.4 PWM and Frequency output
PB[3] can also be used to output the PWM (Pulse Width Modulation) signal from the 10-Bit Counter (refer to 10bit Counter chapter).
PB[2:0] can be used to output three different frequencies from the RC oscillator: ck[20], ck[16] and ck[12].
-Selecting ck[20] output on PB[0] with bit PB600kHzOut in register OPTFSelPB.
-Selecting ck[16] output on PB[1] with bit PB37k5HzOut in register OPTFSelPB.
-Selecting ck[12] output on PB[2] with bit PB2k3HzOut in register OPTFSelPB.
-Selecting PWM output on PB[3] with bit PWMOn in register RegPresc.
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6.5 PortB registers
Table 6.5.1 register RegPBData
Bit
Name
Reset
R/W
3
PBData[3]
R* /W
2
PBData[2]
R* /W
1
PBData[1]
R* /W
0
PBData[0]
R* /W
R* : direct read on pin (not the internal register read).
Table 6.5.2 register RegPBCntl
Bit
Name
Reset
3
PBIOCntl[3]
0
2
PBIOCntl[2]
0
1
PBIOCntl[1]
0
0
PBIOCntl[0]
0
Default "0" is: PortB in input mode
Table 6.5.3 register OPTFSelPB
Bit
Name
power on
value
3
2
PB2k3HzOut
0
1
PB37k5HzOut
0
0
PB600kHzOut
0
Default "0" is: No frequency output.
Table 6.5.4 option register OPTNoPdPB
Bit
Name
power on
value
3
NoPdPB[3]
0
2
NoPdPB[2]
0
1
NoPdPB[1]
0
0
NoPdPB[0]
0
Default "0" is: Pull-down on
Table 6.5.5 option register OPTNchOpDPB
Bit
Name
power on
value
3
NchOpDPB[3]
0
2
NchOpDPB[2]
0
1
NchOpDPB[1]
0
0
NchOpDPB[0]
0
Default "0" is: CMOS on PB[3..0]
Description
PB[3] input and output
PB[2] input and output
PB[1] input and output
PB[0] input and output
R/W
R/W
R/W
R/W
R/W
Description
I/O control for PB[3]
I/O control for PB[2]
I/O control for PB[1]
I/O control for PB[0]
R/W
Description
R/W
R/W
R/W
ck[12] output on PB[2]
ck[16] output on PB[1]
ck[20] output on PB[0]
R/W
Description
R/W
R/W
R/W
R/W
No pull-down on PB[3]
No pull-down on PB[2]
No pull-down on PB[1]
No pull-down on PB[0]
R/W
Description
R/W
R/W
R/W
R/W
N-Channel Open Drain on PB[3]
N-Channel Open Drain on PB[2]
N-Channel Open Drain on PB[1]
N-Channel Open Drain on PB[0]
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6.6 PortC
PortC has the same features as the PortB but instead of being used to outputs frequencies, it can be used to
output Serial Write Buffer (SWB) signals.
6.6.1 Input / Output Mode
Each PortC terminal can be either input or output. These modes can be set by writing the corresponding bit in the
RegPCCntl control register. The RegPCData register contains the data written to the PortC terminal in output
mode. To set for input (default), 0 is written to the corresponding bit of the RegPCCntl register which results in a
high impedance state for the output driver. The output mode is set by writing 1 in the control register, and
consequently the output terminal follows the status of the bits in the RegPCData register. The PortC terminal
status can be read in any mode (read at address of RegPCData).
During SLEEP and Reset mode, PC[3:0] is in high impedance state with no pulls up/down active. Except during a
read phase on PortC (in active mode), all the PortC inputs are cut off (blocked).
6.6.2 Pull-up/Down
For each terminal of PC[3:0] an input pull-up (metal mask MPCPU[n]) or pull-down (metal mask MPCPD[n])
resistor can be implemented per metal mask option. Per default the two metal masks are in place, so one can
chose per software to have either a pull-up, a pull-down or no resistor.
For Metal mask selection and available resistor values refer to chapter ‘PortC Metal Options’.
Pulldown ON : MPCPD[n] must be in place ,
AND the bit NoPdPC[n] must be ‘0’ .
Pulldown OFF : MPBPD[n] is not in place,
OR if MPCPD[n] is in place NoPdPC[n] = ‘1’ cuts off the pulldown.
OR seletcing NchOpDPC[n] = ‘1’ cuts off the pulldown.
Pullup ON
: MPCPU[n] must be in place,
AND the bit NchOpDPC[n] must be ‘1’ ,
AND the bit PCIOCntl[n] = ‘0’ (input mode) OR if PCIOCntl[n] = ‘1’ while PCData[n] = 1.
Pullup OFF
: MPCPU[n] is not in place,
OR if MPCPU[n] is in place NchOpDPC[n] = ‘0’ cuts off the pullup,
OR if MPCPU[n] is in place and if NchOpDPC[n] = ‘1’ then PCData[n] = 0 cuts off the pullup.
Never can pull-up and pull-down be active at the same time.
For POWER SAVING one can switch off the PortC pull resistors between two read phases. No cross current
flows in the input amplifier while the PortC is not read. The recommended order is :
• switch on the pull resistor.
• allow sufficient time - RC constant - for the pull resistor to drive the line to either VSS or VDD.
• Read the PortC
• Switch off the pull resistor
Minimum time with current on the pull resistor is 4 periods of the system clock, if the RC constant is lower than 1
system clock period. Adding a NOP before reading moves the number of periods with current in the pull resistor
to 6 and the maximum RC delay to 3 clock periods.
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6.6.3 CMOS / Nchannel Open Drain Output
The PortC outputs can be configured as either CMOS or Nchannel Open Drain outputs. In CMOS both logic ‘1’
and ‘0’ are driven out on the terminal. In Nchannel Open Drain only the logic ‘0’ is driven out on the terminal, the
logic ‘1’ value is defined by the pull-up resistor (if existing).
6.6.4 Serial Write Buffer (SWB)
If the serial write buffer is actived by EnSWB bit in RegSWBCntl, PC[0] is the output terminal for the serial clock
and PC[1] is the output terminal for the serial data. For details, see section: 8 Serial (Output) Write Buffer - SWB.
6.7 PortC registers
Table 6.7.1 register RegPCData
Bit
Name
Reset
R/W
3
PCData[3]
R/W*
2
PCData[2]
R/W*
1
PCData[1]
R/W*
0
PCData[0]
R/W*
R* : direct read on pin (not the internal register read).
Table 6.7.2 register RegPCCntl
Bit
Name
Reset
3
PCIOCntl[3]
0
2
PCIOCntl[2]
0
1
PCIOCntl[1]
0
0
PCIOCntl[0]
0
Default "0" is : PortC in input mode
Table 6.7.3 option register OPTNoPdPC
Bit
Name
power on
value
3
NoPdPC[3]
0
2
NoPdPC[2]
0
1
NoPdPC[1]
0
0
NoPdPC[0]
0
Default "0" is: Pull-down on
Table 6.7.4 option register OPTNchOpDPC
Bit
Name
power on
value
3
NchOpDPC[3]
0
2
NchOpDPC[2]
0
1
NchOpDPC[1]
0
0
NchOpDPC[0]
0
Default "0" is: CMOS on PC[3..0]
Description
PC[3] input and output
PC[2] input and output
PC[1] input and output
PC[0] input and output
R/W
R/W
R/W
R/W
R/W
Description
I/O control for PC[3]
I/O control for PC[2]
I/O control for PC[1]
I/O control for PC[0]
R/W
Description
R/W
R/W
R/W
R/W
No pull-down on PC[3]
No pull-down on PC[2]
No pull-down on PC[1]
No pull-down on PC[0]
R/W
Description
R/W
R/W
R/W
R/W
N-Channel Open Drain on PC[3]
N-Channel Open Drain on PC[2]
N-Channel Open Drain on PC[1]
N-Channel Open Drain on PC[0]
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7. 10-bit Counter
The EM6640 has a built-in universal cyclic counter. It can be configured as 10, 8, 6 or 4-bit counter. If 10-bits are
selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting.
The counter works in up- or down count mode. Eight clocks can be used as the input clock source, six of them
are prescaler frequencies and two of these clocks are coming from the input pads PA[0] and PA[3]. In this case
the counter can be used as an event counter.
The counter generates an interrupt request IRQCount0 every time it reaches 0 in down count mode or 3FF in up
count mode. Another interrupt request IRQCntComp is generated in compare mode whenever the counter value
matched the compare data register value. Each of this interrupt requests can be masked (default). See section 10
for more information about the interrupt handling.
A 10-bit data register CReg[9:0] is used to initialize the counter at a specific value (load into Count[9:0]). This
data register (Creg[9:0]) is also used to compare its value against Count[9:0] for equivalence.
A Pulse-Width-Modulation signal can be generated and output on PortB PB[3].
Figure 17. 10-bit Counter Block Diagram
PA[0]
ck[19]
ck[16]
ck[13]
ck[10]
ck[4]
ck[1]
PA[3]
IRQCntComp
Comparator
En
ck
PW M
MUX
ck
Up/Down
IRQCount0
Up/Down Counter
En
EvCount
RegCCntl1, 2
RegCDataL, M, H
(Count[9:0])
Load
Counter Read Register
CountFSel[2...0]
Up/Down
Start
EvCount
Load
RegCDataL, M, H (CReg[9:0])
Data Register
EnComp
DB[3:0]
7.1 Full, Limited Bit Counting
Table 6.7—1. Counter length selection
In Full Bit Counting Mode the counter uses its maximum
BitSel[1]
BitSel[0 ]
counter length
of 10-bits length (default ). With the BitSel[1,0] bits in
0
0
10-Bit
register RegCDataH one can lower the counter length,
0
1
8-Bit
for IRQ generation, to 8, 6 or 4 bits. This means that
actually the counter always uses all the 10-bits, but
1
0
6-Bit
IRQCount0 generation is only performed on the number
1
1
4-Bit
of selected bits. The unused counter bits may or may not
be taken into account for the IRQComp generation depending on bit SelIntComp. Refer to chapter 7.4.
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7.2 Frequency Select and Up/Down Counting
8 different input clocks can be selected to drive the Counter. The selection is done with bits CountFSel2…0 in
register RegCCntl1. 6 of this input clocks are coming from the prescaler. The maximum prescaler clock
frequency for the counter is half the system clock and the lowest is 1Hz. Therefore a complete counter roll over
can take as much as 17.07min (1Hz clock, 10 bit length) or as little as 53.3µs (ck[19], 4 bit length). The
IRQCount0, generated at each roll over, can be used for time bases, measurements length definitions, input
polling, wake up from Halt Mode, etc. The IRQCount0 and IRQComp are generated with the system clock
(ck[20]) rising edge. IRQCount0 condition in UpCount Mode is : reaching 3FF if 10-bit counter length (resp FF, 3F,
F in 8, 6, 4-bit counter length). In DownCount Mode the condition is reaching ‘0’. The nonselected bits are ‘don’t
care’. For IRQComp refer to section 7.4.
Note: The Prescaler and the Microprocessor clock’s are usually non-synchronous, therefore timebases
generated are max n, min n-1 clock cycles long (n being the selected counter start value in count down mode).
However the prescaler clock can be synchronized with the µP commands using the prescaler reset function.
Figure 18. Counter Clock Timing
p re s c a le r f re q . o r d e b o u n c e d P o rtA c lo c k s
s ys te m c lo c k
p re s c a le r c lo c k
c o u n tin g
c o u n te r IR Q ’s
N o n d e b o u n c e d P o rtA c lo c k s (s ys te m c lo c k in d e p e n d e n t)
s ys te m c lo c k
P o rtA c lo c k
d iv id e d c lo c k
c o u n tin g
c o u n te r IR Q ’s
The two remaining clock sources are coming from the PA[0] or PA[3] terminals. Refer to chapter PortA on page
16 for details. Both sources can be either debounced (ck[17], ck[8]) or direct inputs, the input polarity can also be
chosen. The output after the debouncer polarity selector is named PA3 , PA0 resp. For the debouncer and input
polarity selection, refer to chapter 6.2.1 on page 16.
In the case of PortA input clock without debouncer, the counting clock frequency will be half the input clock on
PortA. The counter advances on every odd numbered PortA negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA3 or PA0 input clock edge. In this condition the
EM6640 is able to count with a higher clock rate as its internal system clock (Hi-Frequency Input).
(Maximum PortA input frequency is at least 1MHz (@VDD ≥ 1.9V)).
In both, up or down count mode, the counter is cyclic. The counting direction is chosen in register RegCCntl1 bit
Up/Down (default=0, down counting). The counter increases or decreases its value with each positive clock edge
of the selected input clock source. Start up synchronization is necessary because one can not always know the
clock status when enabling the counter. With EvCount=0, the counter will only start on the next positive clock
edge after a previously latched negative edge, while the Start bit was already set to ‘1’.
This synchronization is done differently if Event Count Mode (bit EvCount) is chosen. Refer also to Figure 19.
Internal clock synchronization.
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7.3 Event Counting
The counter can be used in a special event count mode where a certain number of events (clocks) on the PA[0] or
PA[3] input are counted. In this mode the counting will start directly on the next active clock edge as selected on
the PortA input configuration. Internally the active clock edge is always the positive edge.
The Event Count Mode is switched on by setting bit EvCount in the register RegCCntl2 to ‘1’.
PA[3] and PA[0] inputs can be inverted depending on register OPTIntEdgPA but should be debounced. The
debouncer is switched on in register OPTDebIntPA bits NoDebIntPA[3]=0 and NoDebIntPA[0]=0 its frequency
depends on the bit DebSel from register RegPresc setting. The inversion of the internal clock signal derived from
PA[3] or PA[0] is active with IntEdgPA[3] respectively IntEdgPA[0] equal to 1.
Figure 19. Internal clock synchronization
ck
ck
Start
Start
Count[9:0]
+/-1
Count[9:0]
EvCount = 0
ck=counting clock frequency
+/-1
ck
ck
Start
Start
Count[9:0]
EvCount = 0
+/-1
EvCount = 1
Count[9:0]
+/-1
EvCount = 1
7.4 Compare Function
A previously loaded register value (Creg[9:0]) can be compared against the actual counter value (Count[9:0]). If
the two are matching (equality) then a interrupt (IRQComp) is generated. The compare function is switched on
with the bit EnComp in the register RegCCntl2. With EnComp = 0 never an IRQComp is generated. Starting the
counter with the same value as the compare register is possible, no IRQ is generated. The compare value must
be different from hex 0 in up-count mode and different from hex 3FF (resp. FF, 3F, F if limited bit counting) in
down-count mode. Full or Limited bit compare are possible, defined by bit SelIntComp in register RegSysCntl1.
The bit EnComp is reset with every load operation (Load = 1).
Full bit compare function.
To be in this mode, set the bit SelIntComp to ‘1’. The function behaves as described above independent of the
selected counter length. Limited bit counting together with full bit compare can be used to generate a certain
amount of IRQCount0 interrupts until the counter generates the IRQComp interrupt. With PWMOn=‘1’ the counter
would have automatically stopped after the IRQComp, with PWMOn=‘0’ it will continue until the software stops it.
Be careful, PWMOn also redefines the PortB PB[3] output data. (refer to section 7.5).
Limited bit compare
This is the default, with the bit SelIntComp set to ‘0’ the compare function will only take as many bits into account
as defined by the counter length (BitSel[1:0]) selection (see chapter 7.1).
7.5 Pulse Width Modulation (PWM) Generation
The PWM generator uses the behavior of the Compare function so EnComp must be set to activate the PWM
function. At each Roll Over or Compare Match the PWM state - which is output on PortB PB[3] - will toggle. The
start value on PB[3] is depending on the Up/DownCount Mode.
Setting PWMOn to ‘1’ in register RegPresc routes the counter PWM output to PortB PB[3]. Insure that PB[3] is
set to Output mode (refer to section 6.4 for the PortB setup). After using the PWM function, do not forget to reset
the bit PWMOn in order to have PB[3] in a normal mode.
The PWM signal generation is independent of the limited or full bit compare selection bit SelIntComp. However if
SelIntComp=1 (FULL) and the Counter Compare Function is limited to lower than 10 bits one can generate a
predefined number of output pulses. In this case, the number of output pulses is defined with the unused counter
bits. It will count from the start value until the IRQComp match.
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For instance, loading the counter in UpCount mode with hex 000 and the comparator with hex C52 which will be
identified as :
- bits [11:10] are limiting the counter to limits to 4 bits length,
(BitSel[1,0])
- bits [9:4] are the unused counter bits = 05,
(nbr of PWM pulses)
- bits [3:0] (comparator value = 2).
(length of PWM pulse)
Thus after 5 PWM-pulses of 2 clocks cycles length the Counter generates an IRQComp and stops.
The same example with SelIntComp=0 (limited bit compare) will produce an unlimited nbr of 2 cycles PWM
pulses.
7.5.1 How the PWM generator works.
For UpCount Mode; Setting the counter in UpCount and PWM mode, the PB[3] PWM output is defined to be 0.
Each Roll Over will set the output to ‘1’ and each Compare Match will set it back to ‘0’. The Compare Match for
PWM always only works on the defined counter length. This, independent of the SelIntComp setting which is
valid only for the IRQ generation.
In above example the PWM starts with ‘0’ (UpCount),
2 cycles later Compare Match -> PWM to ‘0’,
14 cycles later RollOver -> PWM to ‘1’
2 cycles later Compare Match -> PWM to ‘0’ , etc. until the completion of the 5 pulses.
The normal IRQ generation remains on during PWM output. If no IRQ’s are wanted, the corresponding masks
need to be set.
Figure 20. PWM Output in UpCount Mode
clock
Count[9:0] 3FE
Figure 21. PWM Output in DownCount Mode
clock
3FF
000
001
...
data
data-1
data+1 data+2
Count[9:0] 001
roll-over
roll-over
compare
compare
IRQCount0
IRQCount0
IRQComp
IRQComp
PWM Output
PWM Output
000
3FF
3FE
...
data+1 data
data-1
data-2
In DownCount Mode everything is inverted. The PWM output starts with the ‘1’ value. Each Roll Over will set the
output to ‘0’ and each Compare Match will set it back to ‘1’.
7.5.2 PWM characteristics
PWM resolution is
the minimal signal period is
the maximum signal period is
the minimal pulse width is
:
:
:
:
10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps)
16 (4-bit) x Fmax*
-> 16 x 1/ck[19]
-> 53 µs
(600kHz)
1024 x Fmin*
-> 1024 x 1/ck[1]
-> 1024 s
(600kHz)
1 bit
-> 1 x 1/ck[19]
-> 3.3µs
(600kHz)
* This values are for Fmax or Fmin derived from the internal system clock (600kHz). Much shorter (and longer)
PWM pulses can be achieved by using the PortA as frequency input (undebounced input).
7.6 Counter setup
RegCDataL[3:0], RegCDataM[3:0], RegCDataH[1:0] are used to store the initial count value called CReg[9:0]
which is written into the count register bits Count[9:0] with the Load command. Load is automatically reset
thereafter. The counter value Count[9:0] can be read out at any time - except when using nondebounced high
frequency PortA input - but to maintain data integrity the lower nibble Count[3:0] must always be read first. The
ShCount[9:4] values are shadow registers to the counter. To keep the data integrity during a counter read
operation (3 reads), the counter values [9:4] are copied into these registers with the read of the count[3:0] register.
If using nondebounced high frequency PortA input the counter must be stopped while reading the Count[3:0]
value to maintain the data integrity.
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In down count mode an interrupt request IRQCount0 is generated when the counter reaches 0. In up count
mode, an interrupt request is generated when the counter reaches 3FF (resp. FF,3F,F if limited bit counting).
Never an interrupt request is generated by loading a value into the counter register.
When the counter is programmed from Up into Down mode or vice versa, the counter value Count[9:0] gets
inverted. As a consequence, the initial value of the counter must be programmed after the Up/Down selection.
Loading the counter with hex 000 is equivalent to writing Stop mode, the Start bit is reset, no interrupt request is
generated.
How to use the counter;
1st, set the counter into stop mode (Start=0).
2nd, select the frequency and Up- or Down mode in RegCCntl1.
3rd, write the data registers RegCDataL, RegCDataM, RegCDataH (Counter start value and length)
4th, load the counter, Load=1, and choose the mode. (EvCount, PWM )
5th, if compare mode desired , then write RegCDataL, RegCDataM, RegCDataH (compare value)
6th, set bit Start and EnComp in RegCCntl2
7.7 10-bit Counter Registers
Table 7.7.1 register RegCCntl1
Bit
Name
Reset
R/W
3
Up/Down
0
R/W
2
CountFSel2
0
R/W
1
CountFSel1
0
R/W
0
CountFsel0
0
R/W
Default : PA0 ,selected as input clock, Down counting
Table 7.7.2 Counter input frequency selection with CountFSel[2..0]
CountFSel2
CountFSel1
CountFSel0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Table 7.7.3 register RegCCntl2
Bit
Name
3
Start
2
EvCount
1
EnComp
0
Load
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
up or down counting
input clock selection
input clock selection
input clock selection
clock source selection
Port A PA[0]
Prescaler ck[19]
Prescaler ck[16]
Prescaler ck[13]
Prescaler ck[10]
Prescaler ck[4]
Prescaler ck[1]
Port A PA[3]
Description
Start/Stop control
event counter enable
enable comparator
Write: load counter register
Read: always 0
Default : Stop, No event count, no comparator, no load
Table 7.7.4 register RegSysCntl1
Bit
Name
Reset
3
IntEn
0
2
SLEEP
0
1
SelIntComp
0
0
ChTmDis
0
Default : interrupt on limited bit compare
R/W
R/W
R/W
R/W
R/W
Description
general interrupt enable
Sleep mode
compare Interrupt select
for EM Test only
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Table 7.7.5 register RegCDataL, Counter/Compare low data nibble
Bit
Name
Reset
R/W
3
CReg[3]
0
W
2
CReg[2]
0
W
1
CReg[1]
0
W
0
CReg[0]
0
W
3
Count[3]
0
R
2
Count[2]
0
R
1
Count[1]
0
R
0
Count[0]
0
R
Description
counter data bit 3
counter data bit 2
counter data bit 1
counter data bit 0
data register bit 3
data register bit 2
data register bit 1
data register bit 0
Table 7.7.6 register RegCDataM, Counter/Compare middle data nibble
Bit
Name
Reset
R/W
3
CReg[7]
0
W
2
CReg[6]
0
W
1
CReg[5]
0
W
0
CReg[4]
0
W
3
ShCount[7]
0
R
2
ShCount[6]
0
R
1
ShCount[5]
0
R
0
ShCount[4]
0
R
Description
counter data bit 7
counter data bit 6
counter data bit 5
counter data bit 4
data register bit 7
data register bit 6
data register bit 5
data register bit 4
Table 7.7.7 register RegCDataH, Counter/Compare high data nibble
Bit
Name
Reset
R/W
Description
3
BitSel[1]
0
R/W
Bit select for limited bit count/compare
2
BitSel[0]
0
R/W
Bit select for limited bit count/compare
1
CReg[9]
0
W
counter data bit 9
0
CReg[8]
0
W
counter data bit 8
1
ShCount[9]
0
R
data register bit 9
0
ShCount[8]
0
R
data register bit 8
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8. Serial (Output) Write Buffer - SWB
The EM6640 has Serial Write Buffer which outputs serial data and serial clock coming from prescaler or a other
mode where the clock can be fed from outside (PA[0]).
The SWB is enabled by setting EnSWB bit in RegSWBCntl and by setting the PortC in output mode.
Serial Write Buffer clock is selected by the SWBFSel0 and SWBFSel1 bits in the RegSWBCntl register.
TestVar[3] signal, which is used to make conditional jumps, indicates "Transmission finished" in automatic send
mode or "SWBbuffer empty " interrupt in interactive send mode. In interactive mode, TestVar[3] is equivalent to
the interrupt request flags stored in RegIRQi registers : it permits to recognize the interrupt source. (See also the
interrupt handling section 10 for further information). To serve the "SWBbuffer empty " interrupt request, one only
has to make a conditional jump on TestVar[3].
On the receiver side, serial data can be evaluated on serial clock falling edge. Internally, new data goes out on
rising edge of the same clock.
By default the SWBdata level (on PPC[1]) will be equal to VDD as are all the others terminals. Depending on the
metal1 option MSWBdataLevel (refer to SWBdataLevel Option, on page 50), the level of PPC[1] can be selected
as VregLogic. When this metal option is in place, VregLogic is increased by ∼50mV.
In this case, a high current can be drawn from this terminal without penalizing the output level (see DC
characteristics on page 57).
This allows to transmit the data through a RF module for instance, without an additional regulator or amplifier.
To guarantee the electrical characteristics when PPC[1] is selected as VregLogic, VDD should not be below 2.2v
to output 2mA. If the PPC[1] terminal is used as an input, it’s input high level has to be VregLogic.
Size[5:0]
d
a
t
a
b
u
s
SWBauto
SWB buffer
Control
Logic
Addr. Counter
Shift register
RAM
80 nibbles
SWBFSel0,1
SWB buffer
register empty
IRQ (only in
interactive mode)
SWBStart
SWB data
1
PC[1]
0
PA[0]/9.4kHz
2.3kHz
75kHz
150kHz
Clk
Mux
SWB clock
1
PC[0]
0
EnSWB
TestVar3
Figure 22 Serial write buffer
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EM6640
The Serial Write Buffer has two possible working modes :
8.1 SWB Automatic send mode
In this mode, one has first to prepare data to be sent (up to 256 bits), select the clock and write the bit SWBAuto
in RegSWBSizeH register. Then, executing HALT instruction starts the sending operation. During automatic
sending, one can not do anything with the microcontroller (instructions can not be executed because
of STANDBY mode). At the end of transmission, EM6640 comes out of STANDBY mode and generates a high
level on TestVar[3] meaning “transmission finished“.
This mode has additional features compared to interactive mode. In order to be fully flexible, one can decide to
send for the last package a number of clocks not egal to 4. The number goes from 1 to 4 clocks depending on bit
DiscCk[1:0] in register RegSWBCntl2. All four data bits are always transmitted independent of the number of
clocks selected.
The level of the last bit of the last package is automatically latched as long as the SWB is enabled.
Figure 23 represents two ends of transmission in automatic mode: 1st with data=b1010 and 2nd with data=0010
for the last nibble. Bit DiscCk[0] and bit DiscCk[1] are set to ‘1’, so only one SWBclock will be send for the last
package.
Figure 23 exemple of 2 ends of transmission (SysClk is shown two times longer for a better visibility)
S y s C lk
C k150kH z
H a lt
la s t d a ta = b 1 0 1 0
S W B c lo c k
S W B d a ta
S W B c lo c k
S W B d a ta
0
0
1
0
0
0
0
1
1
1
0
1
1
1
1
1
0
1
0
1
0
0
1
1
1
0
1
1
1
1
1
0
1
0
0
la s t d a ta = b 0 0 1 0
0
LSB
0
1
0
0
la s t n i b b le
MSB
8.1.1 SWB Automatic with external clock
In automatic mode, setting SWBFSel0 and SWBFSel1 to ‘0’ in register RegSWBCntl, selects an external clock
from the PA[0] input which can be used as a serial transmission clock. Serial clock and serial data will go out at
the same frequency as the clock provided on the PA[0] input. Depending of the value of CkExtDiv[1:0] bits in
register RegSWBCntl, the external clock applied on PA[0] can be divided internally by 1 (default), 4, 88 or 352
times.
The PA[0] input can be inverted depending on the register OPTIntEdgPA and debounced depending on the
register OPTDebIntPA. Refer to chapter IRQ on portA, page 16.
For external clock/1 selection, the transmission will start on the third positive clock edge or on the second
negative clock edge applied on PA[0], following the HALT command. This is depending of the PA[0] input
configuration, positive edge for the first case and negative edge for the second case.
For external clock/4, external clock/88 and external clock/352 selection, the transmission will start on the half
clock edge selection + 2 clocks (resp. 4th external clock, 46th external clock and 178 external clock) following the
HALT command.
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EM6640
8.1.2 How the SWB in automatic mode works
Data to be sent must be prepared in the following order:
1st:
First 4-bit package must be written in RegSWBuff register.
2nd:
Other 4-bit packages must be loaded in the RAM from address 0
==> second package at address 0,
third at address 1... (the maximum address space for SWB is 3E hex ==> 64 4-bit packages = 256 bits).
3rd:
One has to load the data size (address of the last 4-bit package) into RegSWBSizeL and RegSWBSizeH
registers and has to set to “1“ at the same time the bit SWBAuto. Therefore, the number of 4-bit
packages which can be sent ranges from 2 (size = 0) to 64 (size = 3E hex).
4th:
To start the transmission, one has to put the EM6640 in HALT mode.
At the end of transmission, write any data to RegSWBuff in order to clear TESTvar[3] which allows the SWB to
be written again.
By writing SWBAuto to “1“, general interrupt enable flag IntEn is disabled until the end of SWB transmission and
therefore no interrupt can occur before transmission ends. Consequently, a HALT command should follow a
SWBAuto write in order not to miss any interruptions. When the transmission is finished, the bit SWBAuto is
cleared and TESTvar[3] goes high and stays at this level until RegSWBuff register is written.
SysClk is shown two times longer for a better visibility !
Figure 24 Automatic Serial Write Buffer transmission
At the end of transmission the general interrupt enable flag IntEn is set to its active high state again when HALT
becomes inactive. An internal START signal enables the CPU to come out of HALT and execute the following
instruction. However if an interrupt occurs during SWB transmission, the CPU will service this first.
One can restart the transmission with the same data by simply reloading the register RegSWBuff and then the
registers RegSWBSizeL and RegSWBSizeH (with bit SWBauto set to “1“), disabling the general interrupt enable
flag and putting again the EM6640 into HALT mode.
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EM6640
8.2 SWB Interactive send mode
In interactive send mode, data to be sent must be loaded in RegSWBuff register (no RAM space is used for serial
transmission).
8.2.1 How the SWB in interactive mode works
One has first to select the serial transmission clock in RegSWBCntl register and load the first 4-bit package to be
sent in RegSWBuff register.
Then setting to “1“ the bit SWBStart in RegSWBSizeH register starts the transmission : data are transferred
from RegSWBuff register to shift register and put on serial data output. When RegSWBuff register is empty, an
interrupt request SWBempty which can not be masked is generated and TestVar[3] goes high.
According to the selected clock, one has to take into account how many instructions are needed to process
SWBempty interrupt request : recognize this interrupt (conditional jump on TESTvar[3]) and load the new 4-bit
package in RegSWBuff register.
Indeed, If processing of SWBempty interrupt request is too long and internal SHIFT register is empty before new
4-bit package was written in RegSWBuff register, the transmission is broken : serial clock output stops at "0", bit
SWBStart and SWBempty are cleared to “0“ and TestVar[3] remains to “1“. This could be the case for a 150kHz
transmission speed. The application must restart the serial transmission by writing the SWBStart in
RegSWBSizeH register after writing the next nibble to the RegSWBuff register
SWBempty and TestVar[3] are cleared to "0" at each RegSWBuff register writing operation.
After loading the last nibble in the RegSWBuff register a new interrupt is generated when this data is transferred
to an intermediate Shift Register. Precaution must be made in this case because the SWB will give repetitive
interrupts until the last data is sent out completely and the SWBStart bit goes low automatically. One possibility to
overcome this is to check in the Interrupt subroutine that the SWBStart bit went low before exiting interrupt.
At the end of transmission, one must write RegSWBuff register to set to “0“ TESTvar[3].
SysClk is shown two times longer for a better visibility !
Figure 25 Interactive Serial Write Buffer mode
N.B.
In interactive mode, the number of clocks per package is always equal to 4 and the level of the last bit
of the last package is not latched. These 2 features are valid only in automatic mode.
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EM6640
8.3 SWB registers
Table 8.3.1 SWB clock selection register RegSWBCntl
Bit
Name
Reset
R/W
3
EnSWB
0
R/W
2
-1
SWBFSel1
0
R/W
0
SWBFSel0
0
R/W
Description
enable SWB
SWB clock selection
SWB clock selection
Table 8.3.2 Serial Write Buffer clock selection
SWB clock output
SWBFSel1 SWBFSel0
9375 Hz/CkExt
0
0
2344 Hz
0
1
75000 Hz
1
0
150000 Hz
1
1
For the first selection, 9375 Hz is dedicated to interactive mode and CkExt to automatic mode.
Table 8.3.3 SWB external clock and discard clock selection in register RegSWBCntl2
Bit
Name
Reset
R/W
Description
3
CkExtDiv[1]
0
R/W
SWB external clock divider selection
2
CkExtDiv[0]
0
R/W
SWB external clock divider selection
1
DiscCk[1]
0
R/W
SWB discard clock selection
0
DiscCk[0]
0
R/W
SWB discard clock selection
Table 8.3.4 Serial Write Buffer discard clock selection
Number of clocks during the last nibble
DiscCk[1]
4 clocks
0
3 clocks
0
2 clocks
1
1clock
1
DiscCk[0]
0
1
0
1
Table 8.3.5 Serial Write Buffer external clock divider selection
SWB clock output
CkExtDiv[1] CkExtDiv[0]
external clock / 1
0
0
external clock / 4
0
1
external clock / 88
1
0
external clock / 352
1
1
Table 8.3.6 SWB buffer register RegSWBuff
Bit
Name
Reset
3
Buff[3]
1
2
Buff[2]
1
1
Buff[1]
1
0
Buff[0]
1
R/W
R/W
R/W
R/W
R/W
Description
SWB buffer bit 3
SWB buffer bit 2
SWB buffer bit 1
SWB buffer bit 0
Table 8.3.7 SWB Low size register RegSWBSizeL
Bit
Name
Reset
3
Size[3]
0
2
Size[2]
0
1
Size[1]
0
0
Size[0]
0
R/W
R/W
R/W
R/W
R/W
Description
auto mode buffer size bit3
auto mode buffer size bit2
auto mode buffer size bit1
auto mode buffer size bit0
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EM6640
Table 8.3.8 SWB High size register RegSWBSizeH
Bit
Name
Reset
3
SWBAuto
0
2
SWBStart
0
1
Size[5]
0
0
Size[4]
0
R/W
R/W
R/W
R/W
R/W
Description
SWB Automatic mode select
SWB Start interactive mode
auto mode buffer size bit5
auto mode buffer size bit4
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EM6640
9. EEPROM
The EM6640’s EEPROM contains 32 words of 8 bits each. Addressing is done indirectly using 5 bits (32
addresses) defined in RegEEPAddr and RegEEPCntl registers.
Either in erase/write mode or in read mode, the EEPROM will be functional for all the standard operating
conditions. Refer to EM6640 Electrical specifications, on page 55.
In RegEEPCntl register, one can select EEPROM reading or writing operation by setting respectively to “0“ or “1“
the bit EEPRdWr.
How to read data from EEPROM :
1st instr.
: write EEPROM address (4 low bits) in RegEEPAddr register.
2nd instr.
: write the high address bit and select reading operation in RegEEPCntl register.
3rd instr.
: read EEPROM low data in RegEEPDataL register.
4th instr.
: read EEPROM high data in RegEEPDataH register.
The two last instructions can be executed in the reverse order.
How to write data in EEPROM :
1st instr.
: write EEPROM address (4 low bits) in RegEEPAddr register.
2nd instr.
: write EEPROM low data in RegEEPDataL register.
3rd instr.
: write EEPROM high data in RegEEPDataH register.
4th instr.
: write the high address bit and select writing operation in RegEEPCntl register.
The three first instructions can be executed in any order.
Writing to the RegEEPCntl register automatically starts the EEPROM reading or writing operation according to
the bit EEPRdWr. To guarantee correct functionality when the EEPROM is being used, one should never modify
the EEPROM’s registers.
EEPROM reading operation lasts 10µs : then, data are available in RegEEPDataL and RegEEPDataH registers.
The flag EEPRdBusy in RegEEPCntl register stays high until the reading operation is finished.
EEPROM writing operation lasts 20200µs : 10000µs for erase process, 10000µs for effective write process and
200µs between these two processes. The flag EEPWrBusy in RegEEPCntl register stays high until the writing
operation is finished. An interrupt request IRQEEP is generated at the end of each writing operation. This interrupt
request can be masked (default, MaskIRQEEP bit). See also the interrupt handling section 10 for further
information.
During reading operation, the device will drawn an additional 60µA of Ivdd current and during erasing/writing
operation an additional 45µA of Ivdd current (typical, @ 3V, 600kHz, 25°C).
N.B. : During a EEPROM writing operation, all the peripherals of the EM6640 can be used but one
should never put the circuit in SLEEP mode or execute a RESET.
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EM6640
9.1
EEPROM registers
Table 9.1.1 EEPROM control register RegEEPCntl
Bit
Name
Reset
R/W
Description
3
EEPRdBusy
0
R
EEPROM reading operation busy flag
2
EEPWrBusy
0
R
EEPROM writing operation busy flag
1
EEPRdWr
0
R/W
EEPROM operation read=0 / write=1
0
Addr[4]
0
R/W
EEPROM address bit 4
Writing this register starts automatically EEPROM reading or writing operation
Table 9.1.2 EEPROM address register RegEEPAddr
Bit
Name
Reset
3
Addr[3]
0
2
Addr[2]
0
1
Addr[1]
0
0
Addr[0]
0
R/W
R/W
R/W
R/W
R/W
Description
EEPROM address bit 3
EEPROM address bit 2
EEPROM address bit 1
EEPROM address bit 0
Table 9.1.3 EEPROM data low register RegEEPDataL
Bit
Name
Reset
3
EEPdata[3]
0
2
EEPdata[2]
0
1
EEPdata[1]
0
0
EEPdata[0]
0
R/W
R/W
R/W
R/W
R/W
Description
EEPROM data bit 3
EEPROM data bit 2
EEPROM data bit 1
EEPROM data bit 0
Table 9.1.4 EEPROM data high register RegEEPDataH
Bit
Name
Reset
R/W
3
EEPdata[7]
0
R/W
2
EEPdata[6]
0
R/W
1
EEPdata[5]
0
R/W
0
EEPdata[4]
0
R/W
Description
EEPROM data bit 7
EEPROM data bit 6
EEPROM data bit 5
EEPROM data bit 4
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EM6640
10. Interrupt Controller
The EM6640 has 12 different interrupt request sources individually maskable. These are :
External(4)
- PortA(4)
PA[3] .. PA[0] inputs
Internal(8)
- Prescaler(3)
- 10-bit Counter(2)
-SWB(1)
-SVLD(1)
-EEPROM(1)
9.4kHz, 586Hz, 1Hz
Count0, CountComp
SWBuff empty in interactive mode
End of measure
End of writing operation
To be able to send an interrupt to the CPU, at least one of the interrupt request flags must be set (IRQxx) and the
general interrupt enable bit IntEn located in the register RegSysCntl1 must be set to 1. The interrupt request
flags can only be set by a positive edge of IRQxx with the corresponding mask register bit (MaskIRQxx) set to 1.
Figure 26. Interrupt Controller Block Diagram
Halt
One of these blocks for each IRQ input
DB
Mask
Interrupt request
capture register
Write
SET
General
INT En
DB
Writ
AutoSWB
IRQ
INT to µP
Read
ClrIntBit
Reset
12 In-OR
SWBempty
At power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any
interrupt request to be stored. Also the general interrupt enable IntEn is set to 0 (No IRQ to CPU) by reset.
After each read operation on the interrupt request registers RegIRQ1, RegIRQ2 or RegIRQ3 the contents of the
addressed register are reset. Therefore one has to make a copy of the interrupt request register if there was more
than one interrupt to treat. Each interrupt request flag may also be reset individually by writing 1 into it (ClrIntBit).
Interrupt handling priority must be resolved through software by deciding which register and which flag inside the
register need to be serviced first.
Since the CPU has only one interrupt subroutine and because the IRQxx registers are cleared after reading, the
CPU does not miss any interrupt request which come during the interrupt service routine. If any occurs during this
time a new interrupt will be generated as soon as the software comes out of the current interrupt subroutine.
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their
corresponding mask setting and not on the general interrupt enable status.
Whenever the EM6640 goes into HALT Mode the IntEn bit is automatically set to 1, thus allowing to resume from
Halt Mode with an interrupt.
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EM6640
10.1 Interrupt control registers
Table 10.1.1 register RegIRQ1
Bit
Name
Reset
R/W
3
IRQPA[3]
0
R/W*
2
IRQPA[2]
0
R/W*
1
IRQPA[1]
0
R/W*
0
IRQPA[0]
0
R/W*
W* ; Writing of 1 clears the corresponding bit.
Description
PortA PA[3] interrupt request
PortA PA[2] interrupt request
PortA PA[1] interrupt request
PortA PA[0] interrupt request
Table 10.1.2 register RegIRQ2
Bit
Name
Reset
R/W
3
IRQ1Hz
0
R/W*
2
IRQ586Hz
0
R/W*
1
IRQ9k4Hz
0
R/W*
0
IRQEE
0
R/W*
W* ; Writing of 1 clears the corresponding bit.
Description
Prescaler interrupt request
Prescaler interrupt request
Prescaler interrupt request
EEPROM interrupt request
Table 10.1.3 register RegIRQ3
Bit
Name
Reset
R/W
3
--2
IRQVLD
0
R/W*
1
IRQCount0
0
R/W*
0
IRQCntComp
0
R/W*
W* ; Writing of 1 clears the corresponding bit.
Description
SVLD interrupt request
Counter interrupt request
Counter interrupt request
Table 10.1.4 register RegIRQMask1
Bit
Name
Reset
3
MaskIRQPA[3]
0
2
MaskIRQPA[2]
0
1
MaskIRQPA[1]
0
0
MaskIRQPA[0]
0
Interrupt is not stored if the mask bit is 0.
R/W
R/W
R/W
R/W
R/W
Description
PortA PA[3] interrupt mask
PortA PA[2] interrupt mask
PortA PA[1] interrupt mask
PortA PA[0] interrupt mask
Table 10.1.5 register RegIRQMask2
Bit
Name
Reset
3
IRQ1Hz
0
2
IRQ586Hz
0
1
IRQ9k4Hz
0
0
IRQEE
0
Interrupt is not stored if the mask bit is 0.
R/W
R/W
R/W
R/W
R/W
Description
Prescaler interrupt mask
Prescaler interrupt mask
Prescaler interrupt mask
EEPROM interrupt request
R/W
Description
R/W
R/W
R/W
SVLD interrupt mask
Counter interrupt mask
Counter interrupt mask
Table 10.1.6 register RegIRQMask3
Bit
Name
Reset
3
--2
MaskIRQVLD
0
1
MaskIRQCount0
0
0
MaskIRQCntComp
0
Interrupt is not stored if the mask bit is 0
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EM6640
11. Supply Voltage Level Detector
The EM6640 has a built-in Supply Voltage Level Detector (SVLD), such that the CPU can compare the supply
voltage against a pre-selected value (default is 2.2V or 2.5V, register selectable). The pre-selected values can be
adjusted by metal mask options. During Sleep Mode this function is inhibited.
The CPU activates the supply voltage level Figure 27. SVLD Timing Diagram
detector by writing VldStart=1 in the register
SVLD <VBAT
SVLD >VBAT
RegVldCntl. The actual measurement starts on
VBAT =VDD
the next ck[9] rising edge and lasts during the
compare level
ck[9] high period (1.7ms at 600kHz). The busy
flag VldBusy stays high from Start set until the
ck[9] (293Hz)
measurement is finished. The worst case time
CPU
CPU
until the result is available is 1.5 x ck[9]
starts
starts
prescaler clock periods (600kHz -> 5.1ms).
Busy Flag
The detection level must be defined in register
RegVldCntl before the Start bit is set.
measure
During the actual measurement the device will
0
draw an additional 5uA of IVDD current. After the
1
Result
end of the measure an interrupt request
Read Result
IRQVLD is generated and the result is available
by inspection of the bit VLDResult. If the result
is read 0, then the power supply voltage was greater than the detection level value. If read 1, the power supply
voltage was lower than the detection level value. During each read while Busy=1 the VLDResult is not defined.
11.1 Supply Voltage Level Detector Register
Table 11.1.1 register RegVldCntl
Bit
Name
Reset
R/W
3
VLDResult
0
R*
2
VLDStart
0
W
2
VLDBusy
0
R
1
0
0
R
0
VLDlevel
0
R/W
R* ; VLDResult is not guaranteed while VLDBusy=1
Description
VLD result flag
VLD start
VLD busy flag
VLD level selection
Table 11.1.2 Voltage detector value selecting
VLDlevel
typical voltage level
0
2.5V
1
2.2V
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EM6640
12. RAM
The EM6640 has one 80x4 bit RAM built-in located on addresses hex 0 to 4F. All the RAM nibbles are direct
addressable.
Figure 28. RAM Architecture
Address RAM
Bits Read/Write
79
78
77
76
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
03
02
01
00
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
80x4 directly addressable RAM
12.1 RAM Extension
Unused R/W Registers can often be used as possible RAM extension. Be careful not to use registers which start,
stop, or reset some functions.
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EM6640
13. PERIPHERAL MEMORY MAP
Reset values are valid after power up or after every system reset.
Register
name
Ram
add
hex
00
add
dec
00
reset
value
b’3210
read_bits
write_bits
Remarks
Read/Write_bits
xxxx
direct addressable Ram 80x4
0 : data0
1 : data1
2 : data2
3 : data3
.
.
.
.
.
.
4F
79
RegEEPDataL
50
80
0000
RegEEPDataH
51
81
0000
RegEEPAddr
52
82
0000
RegEEPCntl
53
83
0000
RegPA
54
84
xxxx
RegPBCntl
55
85
0000
RegPBData
56
86
0000
RegPCCntl
57
87
0000
RegPCData
58
88
0000
RegSWBCntl
59
89
0000
0 : EEPData[0]
1 : EEPDatal[1]
2 : EEPData[2]
3 : EEPDatal[3]
0 : EEPData[4]
1 : EEPDatal[5]
2 : EEPData[6]
3 : EEPDatal[7]
0 : Addr[0]
1 : Addr[1]
2 : Addr[2]
3 : Addr[3]
0 : Addr[4]
0 : Addr[4]
1 : EEPRdWr
1 : EEPRdWr
2 : EEPWrBusy
2 : -3 : EEPRdBusy
3 : -0 : PAData[0]
1 : PAData[1]
---2 : PAData[2]
3 : PAData[3]
0 : PBIOCntl[0]
1 : PBIOCntl[1]
2 : PBIOCntl[2]
3 : PBIOCntl[3]
0 : PB[0]
1 : PB[1]
2 : PB[2]
3 : PB[3]
0 : PBData[0]
1 : PBData[1]
2 : PBData[2]
3 : PBData[3]
0 : PCIOCntl[0]
1 : PCIOCntl[1]
2 : PCIOCntl[2]
3 : PCIOCntl[3]
0 : PC[0]
1 : PC[1]
2 : PC[2]
3 : PC[3]
0 : SWBFSel0
1 : SWBFSel1
2 : ‘0’
3 : EnSWB
0 : PCData[0]
1 : PCData[1]
2 : PCData[2]
3 : PCData[3]
0 : SWBFSel0
1 : SWBFSel1
2 : -3 : EnSWB
EEPROM data low bits
EEPROM data high bits
EEPROM address 4 first bits
EEPROM address 5th bit.
EEPROM control : Read/Write
EEPROM Write busy flag
EEPROM Read busy flag
read PortA directly
PortB Control
default : input mode
PortB data output.
Pin PortB read
default : 0
PortC Control
default : input mode
PortC data output.
Pin PortC read
default : 0
SWB control :
clock selection, enable SWB
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EM6640
Register
name
add
hex
add
dec
reset
value
b’3210
RegSWBuff
5A
90
1111
RegSWBSizeL
5B
91
0000
RegSWBSizeH
5C
92
0000
RegCCntl1
5D
93
0000
RegCCntl2
5E
94
0000
RegCDataL
5F
95
0000
RegCDataM
60
96
0000
RegCDataH
61
97
0000
RegIRQMask1
62
98
0000
RegIRQMask2
63
99
0000
RegIRQMask3
64
100
0000
RegIRQ1
65
101
0000
REgIRQ2
66
102
0000
RegIRQ3
67
103
0000
read_bits
write_bits
Read/Write_bits
0 : Buff[0]
1 : Buff[1]
2 : Buff[2]
3 : Buff[3]
0 : Size[0]
1 : Size[1]
2 : Size[2]
3 : Size[3]
0 : Size[4]
1 : Size(5]
2 : SWBStart
3 : SWBAuto
0 : CountFSel0
1 : CountFSel1
2 : CountFSel2
3 : UP/Down
0 : ‘0’
0 : Load
1 : EnComp
1 : EnComp
2 : EvCount
2 : EvCount
3 : Start
3 : Start
0 : Count[0]
0 : Creg[0]
1 : Count[1]
1 : Creg[1]
2 : Count[2]
2 : Creg[2]
3 : Count[3]
3 : Creg[3]
0 : Count[4]
0 : Creg[4]
1 : Count[5]
1 : Creg[5]
2 : Count[6]
2 : Creg[6]
3 : Count[7]
3 : Creg[7]
0 : Count[8]
0 : Creg[8]
1 : Count[9]
1 : Creg[9]
2 : BitSel[0]
2 : BitSel[0]
3 : BitSel[1]
3 : BitSel[1]
0 : MaskIRQPA[0]
1 : MaskIRQPA[1]
2 : MaskIRQPA[2]
3 : MaskIRQPA[3]
0 : MaskIRQEE
1 : MaskIRQ9k4Hz
2 : MaskIRQ586Hz
3 : MaskIRQ1Hz
0 : MaskIRQCntComp 0 :MaskIRQCntCom
1 : MaskIRQCount0
p
2 : MaskIRQVLD
1 : MaskIRQCount0
3 : ‘0’
2 : MaskIRQVLD
3 : -0 : IRQPA[0]
0 : RIRQPA[0]
1 : IRQPA[1]
1 : RIRQPA[1]
2 : IRQPA[2]
2 : RIRQPA[2]
3 :IRQPA[3]
3 : RIRQPA[3]
0 : IRQEE
0 : RIRQEE
1 : IRQ9k4Hz
1 : RIRQ9k4Hz
2 : IRQ586Hz
2 : RIRQ586Hz
3 : IRQ1Hz
3 : RIRQ1Hz
0 :IRQCntComp
0 : RIRQCntComp
1 : IRQCount0
1 : RIRQCount0
2 : IRQVLD
2 : RIRQVLD
3 : ‘0’
3 : --
Remarks
SWB buffer register
SWB size low bits
SWB size high bits.
Automatic/interactive mode
selection.
10 bit counter
control 1 ;
frequency and up/down
10 bit counter control 2 ;
comparison, event counter and
start
10 bit counter
data_low bits
10 bit counter
data_middle bits
10 bit counter
data_high bits
PortA interrupt mask ;
masking active low
prescaler interrupt mask ;
masking active low
10 bit counter, VLD interrupt
mask
masking active low
Read : PortA interrupt
Write : Reset IRQ if data bit = 1.
Read : prescaler IRQ , EEPROM
IRQ
Write : Reset IRQ if data bit = 1
Read : 10 bit counter, VLDl
interrupt
Write : Reset IRQ if data bit =1.
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EM6640
Register
name
RegSysCntl1
add
hex
68
add
dec
104
reset
value
b’3210
00x0
RegSysCntl2
69
105
0000
RegSysCntl3
6A
106
0000
RegPresc
6B
107
0000
RegVLDCntl
6C
108
0000
RegSWBCntl2
6D
109
0000
IXLow
6E
110
xxxx
IXHigh
6F
111
xxxx
read_bits
write_bits
Read/Write_bits
0 : ChTmDis
0 : ChTmDis
1 : SelintComp
1 : SelintComp
2 : ‘0’
2 : Sleep
3 : IntEn
3 : IntEn
0 : WDVal0
0 : -1 : WDVal1
1 : -2 : SleepEn
2 : SleepEn
3 : ‘0’
3 : WDReset
0 : NoLogicWD
0 : NoLogicWD
1 : NoOscWD
1 : NoOscWD
2 : ‘0’
2 : -3 : ‘0’
3 : -0 : DebSel
0 : DebSel
1 : ‘0’
1 : -2 : ‘0’
2 : ResPresc
3 : PWMOn
3 : PWMOn
0 : VLDlevel
0 : VLDlevel
1 : ‘0’
1 : -2 : VLDBusy
2 : VLDStart
3 : VLDResult
3 : -0 : DiscCk[0]
1 : DiscCk[1]
2 : CkExtDiv[0]
3 : CkExtDiv[1]
0 : IXLow[0]
1 : IXLow[1]
2 : IXLow[2]
3 : IXLow[3]
0 : IXHigh[4]
0 : IXHigh[4]
1 : IXHigh[5]
1 : IXHigh[5]
2 : IXHigh[6]
2 : IXHigh[6]
3 : ‘0’
3 : --
Remarks
system control 1
ChTmDis only usable for EM
test modes with Test=1
system control 2 ;
watchdog value and periodical
reset, enable sleep mode
system control 3 ;
watchdog control
prescaler control ;
debouncer and prescaler
interrupt selection
VLD control :
level detection, start (busy flag)
and result.
SWB control2 :
discard clock selection
external clock divider selection
internal µP index
register low nibble ;
internal µP index
register high nibble ;
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14. Option Register Memory Map
The values of the Option Registers are set only by initial reset on power up and through write operations. Other resets as
reset from watchdog, reset from input PortA, etc... do not change the Options Register value.
Register
add add
power up
read_bits
write_bits
Remarks
name
hex dec
value
b’3210
Read/Write_bits
0 : RstSlpTSel[0]
option register ;
OPTSlpCntRst
1 : RstSlpTSel[1]
Sleep Counter Reset
72
114
0000
2 : RstSlpTSel[2]
default : SCR disable
OPT[47 :44]
3 : EnSlpCntRst[3]
0 : NoDebIntPA[0]
option register ;
OPTDebIntPA
1 : NoDebIntPA[1]
debouncer on PortA
73
115
0000
2 : NoDebIntPA[2]
for interrupt gen.
OPT[3 :0]
3 : NoDebIntPA[3]
Default : debouncer on
0 : IntEdgPA[0]
option register ;
OPTIntEdgPA
1
:
IntEdgPA[1]
interrupt
edge select on PortA
74
116
0000
2 : IntEdgPA[2]
default : pos edge
OPT[7 :4]
3 : IntEdgPA[3]
0 : NoPdPA[0]
option register ;
OPTNoPullPA
1 : NoPdPA[1]
pull-up/down selection on PortA
75
117
0000
2 : NoPdPA[2]
default : pull-down
OPT[11 :8]
3 : NoPdPA[3]
0 : NoPdPB[0]
option register ;
OPTNoPdPB
1 : NoPdPB[1]
pulldown selection on PortB
76
118
0000
2 : NoPdPB[2]
default : pull-down
OPT[15 :12]
3 : NoPdPB[3]
0 : NoPdPC0]
option register ;
OPTNoPdPC
1
:
NoPdPC[1]
pulldown
selection on PortC
77
119
0000
2 : NoPdPC[2]
default : pull-down
OPT[19 :16]
3 : NoPdPC[3]
0 : NchOpDPB[0]
option register ;
OPTNchOpDPB
1 : NchOpDPB[1]
n-channel open drain
78
120
0000
2 : NchOpDPB[2]
output on PortB
OPT[23 :20]
3 : NchOpDPB[3]
default : CMOS output
0 : NchOpDPC[0]
option register ;
OPTNchOpDPC
1
:
NchOpDPC[1]
n-channel
open drain
79
121
0000
2 : NchOpDPC[2]
output on PortC
OPT[27 :24]
3 : NchOpDPC[3]
default : CMOS output
0 : NoInputReset
-PortA input reset option, input
1 : SelinpResMod
reset mode (Or or AND logic).
OPTPaRST
7A
122
0000
2 : OscAdj[4]
-Adjustment of RC oscillator
OPT[31 :28]
3 : OscAdj[5]
(2 MSB) in EEPROM
0 : OscAdj[0]
OPTOscAdj
option register ;
1 : OscAdj[1]
7B
123
0000
Adjustment
of RC oscillator
2 : OscAdj[2]
OPT[35 :32]
(4
LSB)
in
EEPROM
3 : OscAdj[3]
0 : PB600kHzOut
OPTFselPB
1 : PB37k5HzOut
option register ;
7C
124
0000
2 : PB2k3HzOut
frequency output on PortB
OPT[39 :36]
3 : -0 : InpRes1PA[0]
option register ;
7D
125
0000
1 : InpRes1PA[1]
reset through PortA inputs
OPTInpRSel1
2 : InpRes1PA[2]
selection,
3 : InpRes1PA[3]
refer to reset part
0 : InpRes2PA[0]
option register ;
7E
126
0000
1 : InpRes2PA[1]
reset through PortA inputs
OPTInpRSel2
2 : InpRes2PA[2]
selection,
3 : InpRes2PA[3]
refer to reset part
for EM test only ;
RegTestEM
7F
127
------accu
write accu on PortA
Test = 1
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EM6640
15. Test at EM - Active Supply Current Test
For this purpose, five instructions at the end of the ROM will be added.
Testloop:
STI
LDR
NXORX
JPZ
JMP
00H, 0AH
1BH
Testloop
00H
To stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop:
1BH:
32H:
6EH:
6FH:
0101b
1010b
0010b
0011b
Free space after last instruction: JMP 00H (0000)
Remark: empty space within the program are filled with NOP (FOFF).
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EM6640
16. Mask Options
Most options which in many µControllers are realized as metal mask options, are directly user selectable with the
option registers allowing a maximum freedom of choice .See chapter : Option Register Memory Map.
The following options can be selected at the time of programming the metal mask ROM.
16.1 Input / Output ports
16.1.1 PortA Metal Options
Pull-Up or No Pull-Up can be
selected for each PortA input. A Pullup selection is excluding a Pull-down
on the same input.
Pull-Down or No Pull-Down can be
selected for each PortA input. A Pulldown selection is excluding a Pull-up
on the same input.
The total pull value (pull-up or pulldown) is a series resistance out of
the resistance R1 and the switching
transistor. As a switching transistor,
the user can choose between a high
impedance (weak) or a low
impedance (strong) switch (one can
not choose both). Weak, strong or
none must be chosen. The default is
strong. The default resistor R1 value
is 85kOhm. The user may choose a
different value from 85kOhm down to
0 Ohm. However the value must first
be checked and agreed by EM
Microelectronic Marin SA.
Figure 29. PortA pull options
Input circuitry
PullUp Control
NoPullup
NoPulldown
MPAPDstrong[n]
strong pulldown
PullDown Control
weak
PullDown
R1
value
NO
PullDown
2
3
4
MPAPDweak[n]
weak pulldown
To select an option put a cross-X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : strong pulldown
with R1=85k.
Total value of typ. 100kOhm
PA3 input pull-down
PA2 input pull-down
PA1 input pull-down
PA0 input pull-down
Option
name
MPAPU[3]
MPAPU[2]
MPAPU[1]
MPAPU[0]
Resistor R1
85 kOhm
or
1
MPAPD[3]
MPAPD[2]
MPAPD[1]
MPAPD[0]
MPAPUstrong[n]
strong pullup
PA[n]
Terminal
strong
PullDown
Option
name
MPAPUweak[n]
weak pullup
strong
Pull-Up
weak
Pull-Up
R1
value
NO
Pull-Up
1
2
3
4
To select an option put a cross-X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : strong pull-up
with R1=85k
Total value of typ. 100kOhm
By default : no pull-up
PA3 input pull-up
PA2 input pull-up
PA1 input pull-up
PA0 input pull-up
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EM6640
16.1.2 PortB Metal Options
Pull-Up or No Pull-Up can be
selected for each PortB input. The
Pull-Up is only active in N-Channel
Open Drain Mode.
Pull-Down or No Pull-Down can be
selected for each PortB input.
Figure 30. PortB pull options
Input circuitry
PullUp Control
The total pull value (pull-up or
pulldown) is a series resistance out
of the resistance R1 and the
switching transistor. As a switching
transistor the user can choose
between a high impedance (weak)
or a low impedance (strong) switch
(one can not choose both). Weak,
strong or none must be chosen.
The default is Strong. The default
resistor R1 value is 85kOhm. The
user may choose a different value
from 85kOhm down to 0 Ohm.
However the value must first be
checked and agreed by EM
Microelectronic Marin SA.
PB[n]
Terminal
or
No Pullup
No Pulldown
PullDown Control
weak
PullDown
R1
value
NO
PullDown
2
3
4
MPBPDweak[n]
weak pulldown
To select an option put a cross-X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : strong pulldown
with R1=85k
Total value of typ. 100kOhm
PB3 input pull-down
PB2 input pull-down
PB1 input pull-down
PB0 input pull-down
Option
name
MPBPU[3]
MPBPU[2]
MPBPU[1]
MPBPU[0]
Resistor R1
85 kOhm
MPBPDstrong[n]
strong pulldown
1
MPBPD[3]
MPBPD[2]
MPBPD[1]
MPBPD[0]
MPBPUstrong[n]
strong pullup
Block
strong
PullDown
Option
name
MPBPUweak[n]
weak pullup
strong
Pull-Up
weak
Pull-Up
R1
value
NO
Pull-Up
1
2
3
4
PB3 input pull-up
PB2 input pull-up
PB1 input pull-up
PB0 input pull-up
To select an option put a cross-X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : strong pull-up
with R1=85k
Total value of typ. 100kOhm
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EM6640
16.1.3 PortC Metal Options
Pull-Up or No Pull-Up can be
selected for each PortC input. The Figure 31. PortC pull options
Pull-Up is only active in N-Channel
Open Drain Mode.
Input circuitry
Pull-Down or No Pull-Down can be
selected for each PortC input.
PullUp Control
The total pull value (pull-up or
pulldown) is a series resistance out
of the resistance R1 and the
switching transistor. As a switching
transistor the user can choose
between a high impedance (weak)
or a low impedance (strong) switch
(one can not choose both). Weak,
strong or none must be chosen.
The default is Strong. The default
resistor R1 value is 85kOhm. The
user may choose a different value
from 85kOhm down to 0 Ohm.
However the value must first be
checked and agreed by EM
Microelectronic Marin SA.
PC[n]
Terminal
or
No Pullup
No Pulldown
PullDown Control
weak
PullDown
R1
value
NO
PullDown
2
3
4
MPCPDweak[n]
weak pulldown
To select an option put a cross-X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : strong pulldown
with R1=85k
Total value of typ. 100kOhm
PB3 input pull-down
PB2 input pull-down
PB1 input pull-down
PB0 input pull-down
Option
name
MPBPU[3]
MPBPU[2]
MPBPU[1]
MPBPU[0]
Resistor R1
85 kOhm
MPCPDstrong[n]
strong pulldown
1
MPBPD[3]
MPBPD[2]
MPBPD[1]
MPBPD[0]
MPCPUstrong[n]
strong pullup
Block
strong
PullDown
Option
name
MPCPUweak[n]
weak pullup
strong
Pull-Up
weak
Pull-Up
R1
value
NO
Pull-Up
1
2
3
4
PB3 input pull-up
PB2 input pull-up
PB1 input pull-up
PB0 input pull-up
To select an option put a cross-X in
column 1,2 and 4 and reconfirm the
R1 value in column 3.
The default value is : strong pull-up
with R1=85k
Total value of typ. 100kOhm
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16.2 Digital Watchdog Option
Option name
MDigWD
Digital WatchDog
Default
value
A
YES
user
value
Default
value
A
VDD
user
value
B
By default the Digital Watchdog is software
controlled by the state of the bit NoLogicWD. With
option MDigWDB the bit NoLogicWD has no more
effect so the Digital Watchdog is always forced
active.
16.3 SWBdataLevel Option
Option name
MSWBdataLevel
level of SWB data
B
By default the SWB data level (on PPC[1]) will be
equal to VDD. With the option MSWBdataLevelB,
the level of PPC[1] will be selected as VregLogic
16.4 Remaining metal mask options
- For more detail about the mask options refer to the concerned chapters.
- The internal voltage regulators for the logic is adjustable to some extend.
- Different SVLD settings are possible.
- Other changes (functional or parametric) might also be possible using the metal mask.
- If you have a special request please contact EM Microelectronic Marin SA.
16.5 Metal mask ordering
The customer should specify the required options at the time of ordering.
A copy of the selected option sheet, as well as the « Software ROM characteristic file » generated by the
assembler (*.STA) should be attached to the order.
Software name is :
______________________.bin, dated ______________
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17. Temperature and Voltage Behaviors
17.1 RC oscillator (typical)
Temperature dependency relative to 25°C; VDD=3V
2.00
0.00
[%]
-30
-15
0
15
30
45
60
75
-2.00
-4.00
[°C]
17.2 IDD Current (typical)
IDD Standby Mode; VDD=3V
10
[ uA ]
9
8
7
-30
-15
0
15
30
45
60
[ °C ] 75
60
[ °C ] 75
IDD Active Mode; VDD=3V
50
[ uA ]
45
40
35
-30
-15
0
15
30
45
IDD Sleep Mode; VDD=3V
350.00
[ nA ]
300.00
250.00
-30
-15
0
15
30
45
60
[ °C ] 75
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17.3 Regulated Voltage (typical)
Regulated Voltage; VDD=3V
2.0
VReg=f(VDD) @ different temperatures
1.95
[V]
[V]
85°C
1.90
1.9
60°C
1.85
25°C
0°C
1.80
1.8
-20°C
1.75
1.7
-30
1.70
-15
0
15
30
45
60
1.5
[°C] 75
2.0
2.5
3.0
3.5
4.0
4.5
[V] 5.0
17.4 Output Currents (typical)
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-30
-15
I O H C u r r e n ts o f P B 0 , P B 3 , P C [3 :0 ]; V D D = 3 V ;
V D S = 0 .1 5 V /0 .3 V /0 .5 V /1 V
0
15
30
45
60
-30
[ °C ] 7 5
-15
I O H C u r r e n ts o f P B 1 , P B 2 ; V D D = 3 V ;
V D S = 0 .1 5 V /0 .3 V /0 .5 V /1 V
0
15
30
45
60
[ °C ]
75
0
0
0 .1 5 V
0 .1 5 V
-2
0 .3 V
-2
0 .3 V
0 .5 V
-4
-4
0 .5 V
[m A ]
[m A ]
1 .0 V
-6
-6
-8
-8
-10
-10
2
I O H C u r re n ts o f P B 0 , P B 3 , P C [3 :0 ]; V D S = 0 . 1 5 V / 0 . 3 V / 0 . 5 V / 1 V ;
Te m p= 25C
3
4
5
1 .0 V
2
[V ]
I O H C u r r e n ts o f P B 1 , P B 2 ; V D S = 0 . 1 5 V / 0 . 3 V / 0 . 5 V / 1 V ;
Te m p= 25C
3
4
5
[V ]
0
0
0 .1 5 V
[m A ]
0 .1 5 V
0 .3 V
-5
0 .3 V
-5
0 .5 V
[m A ]
0 .5 V
-10
1V
-15
-10
-15
I O L C u r r e n ts o f P B 0 , P B 3 , P C [3 :0 ]; V D D = 3 V ;
V D S = 0 .1 5 V /0 .3 V /0 .5 V /1 V
15
1V
I O L C u r r e n ts o f P B 1 , P B 2 ; V D D = 3 V ;
V D S = 0 .1 5 V /0 .3 V /0 .5 V /1 V
40
[m A ]
[m A ]
30
10
1 .0 V
1 .0 V
20
5
0 .5 V
0 .5 V
10
0 .3 V
0 .3 V
0 .1 5 V
0 .1 5 V
0
0
-30
-15
0
15
30
45
60
[ °C ]
75
-30
I O L C u rr e n ts o f P B 0 , P B 3 , P C [3 :0 ]; V D S = 0 . 1 5 V / 0 . 3 V / 0 . 5 V / 1 V ;
Te m p= 25C
20
-15
0
15
30
45
60
[ °C ]
75
I O L C u r r e n ts o f P B 1 , P B 2 ;
V D S = 0 .1 5 V /0 .3 V /0 .5 V /1 V ; T e m p = 2 5 C
50
[m A ]
[m A ]
1V
40
1V
15
30
10
0 .5 V
20
0 .5 V
5
0 .3 V
0 .3 V
10
0 .1 5 V
0 .1 5 V
0
2
3
4
[V ]
0
5
2
3
4
[V ]
5
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EM6640
17.5 Pull-up/down (typical)
P u l l d o w n S tr o n g w i th R 1 ty p ; V D D = 3 V
P u l l d o w n S tro n g w i th R 1 ty p ; T e m p = 2 5 ° C
1 0 0 .0
1 3 0 .0
[k o h m ]
[k o h m ]
1 1 0 .0
9 5 .0
9 0 .0
7 0 .0
9 0 .0
-30
-15
0
15
30
45
60
[ °C ]
75
2
3
4
V DD [V ]
5
P u l l u p S tr o n g w i th R 1 ty p ; T e m p = 2 5 ° C
P u l l u p S tr o n g w i th R 1 ty p ; V D D = 3 V
1 0 5 .0
1 3 0 .0
[k o h m ]
[k o h m ]
1 1 0 .0
1 0 0 .0
9 0 .0
7 0 .0
9 5 .0
-30
-15
0
15
30
45
60
[ °C ] 7 5
2
3
4
V DD [V ]
5
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18. EM6640 Electrical specifications
All electrical specifications written in this section are related to a typical system clock of 600 kHz.
18.1 Absolute maximum ratings
Min.
Max.
Unit
Power supply VDD-VSS
- 0.2
+ 5.7
V
Input voltage
VSS - 0,2
VDD+0,2
V
Storage temperature
- 40
+ 125
°C
Electrostatic discharge to
-2000
+2000
V
Mil-Std-883C Method 3015.7 with ref. to VSS
Maximum soldering conditions
10s x 250°C
Stresses above these listed maximum ratings may cause permanent damage to the device.
Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction.
18.2 Handling Procedures
This device has built-in protection against high static voltages or electric fields ; however, anti-static precautions
should be taken as for any other CMOS component.
Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply
voltage range.
18.3 Standard Operating Conditions
Parameter
Min.
Typ.
Max.
Unit
Description
Temperature
-30
25
85
°C
VDD
1.9
3
5.5
V
VSS
0
V
Reference terminal
regulated voltage capacitor
CVreg (note 1)
0.22
1
µF
fq
600
kHz
nominal frequency
Note 1: This capacitor filters switching noise from VDD to keep it away from the internal logic cells.
In noisy systems or if using the MSWBdataLevel metal option, the capacitor should be chosen bigger
than the typical value.
18.3.1 DC characteristics - Power Supply Pins
Conditions: VDD=3V, T=25°C, f=600kHz (unless otherwise specified)
Parameter
Conditions
Symbol
Min.
Typ.
Max. Unit
ACTIVE Supply Current
IVDDa
42
µA
(note 1)
-30 ... 85°C
IVDDa
55
µA
STANDBY Supply Current
IVDDh
8
µA
(in Halt mode)
-30 ... 85°C
IVDDh
12
µA
SLEEP Supply Current
IVDDs
0.3
µA
(SLEEP = 1)
-30 ... 85°C
IVDDs
0.4
µA
POR static level
25°C
VPOR
1.5
V
CVreg, no load
Regulated voltage
Vreg
1.85
V
-30 ... 85°C,CVreg, no load
1.75
2.1
V
Vreg
RAM data retention
Vrd
1.5
V
Note 1: For test reasons at EM, the user has to provide a test loop with successive writing and reading of two
different addresses (5 instructions should be reserved for this measurement).
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EM6640
18.4 Supply Voltage Level Detector
Conditions: Standard operating conditions (unless otherwise specified)
Parameter
Conditions
Symb.
Min.
Typ.
Max.
Unit
SVLD voltage Level
VSVLD
0.92 VSVLDNom
VSVLDNOM
1.08 VSVLDNom V
-10 ... 60°C
VSVLD
0.90 VSVLDNom
VSVLDNOM
1.10 VSVLDNom V
-30 ... 85°C
VSVLDNom = selected SVLD levels by customer (refer to Supply Voltage Level Detector chapter, on page 40)
18.5 Oscillator
Conditions: Vdd=3V, T=25°C, f=600kHz (unless otherwise specified), fο = f at 25°C
Parameter
Temperature stability
Temperature stability
Temperature stability
Adjustable frequency range
permitted
Delivery state
Oscillator start time
System start time
(oscillator + cold start + reset)
Oscillation detector frequency
Conditions
Symb.
-30°C ... +40°C
-30°C
85°C
df/fο
df/fο
df/fο
freq
Min.
Typ.
±1
+3
-6
510
600
690
610
tdosc
tdsys
600
50
1
fOD
100
590
VDD > VDDmin
VDD > VDDmin
Max.
5
Unit
%
%
%
kHz
kHz
µs
ms
kHz
18.6 Analogue filter on PortA
Conditions: Standard operating conditions (unless otherwise specified)
Parameter
Conditions
time Constant
Symb.
Min.
Typ.
Max.
Unit
anafltr
5
9
15
µs
18.7 Sleep counter reset (SCR)
Conditions: Standard operating conditions (unless otherwise specified)
Parameter
Conditions
time Constant
Symb.
Min.
Typ.
Max.
Unit
ctscr
7
10
13
ms
Typ.
Max.
Unit
5.5
µs
ms
V
18.8 EEPROM
Conditions: Standard operating conditions (unless otherwise specified)
Parameter
Conditions
Symb.
Min.
Read time (note 1)
-30 ... 85°C
EEPrd
Write time (note 1)
-30 ... 85°C
EEPwr
VDD during write and read
-30 ... 85°C
VEEP
2.0
operation
Note 1 : This values are guaranteed by design when using 600kHz.
13
20.2
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EM6640
18.9 DC characteristics - input / output Pins
Conditions: Standard operating conditions (unless otherwise specified)
Parameter
Input Low voltage
Ports A,B,C
TEST
Input High voltage
Ports A,B,C
TEST
Output Low current
Port B[3], Port B[0]
Port B[2], Port B[1]
Port C[3:0]
Port C[1] (note 1)
Conditions
Symb
Min.
Input Mode
VIL
Input Mode
VIH
VDD=1.9V , VOL=0.30V
IOL
VDD=3.0V , VOL=0.30V
IOL
VDD=5.0V , VOL=0.30V
Typ.
Max.
Unit
Vss
Vss
0.3VDD
0.3VDD
V
V
0.7VDD
0.7VDD
VDD
VDD
V
V
2.5
mA
3.6
mA
IOL
5
mA
VDD=1.9V , VOL=0.30V
IOL
7.5
mA
VDD=3.0V , VOL=0.30V
IOL
10.2
mA
2.6
6.4
VDD=5.0V , VOL=0.30V
IOL
13
mA
VDD=1.9V , VOL=0.30V
IOL
2.5
mA
VDD=3.0V , VOL=0.30V
IOL
3.6
mA
VDD=5.0V , VOL=0.30V
IOL
5
mA
VDD≥2.2V , VOL=0.10V
IOL
3.7
mA
VDD=1.9V, VOH= VDD-0.30V
IOH
-1.4
mA
VDD=3.0V, VOH= VDD-0.30V
IOH
-2.5
VDD=5.0V, VOH= VDD-0.30V
IOH
-3.3
mA
VDD=1.9V, VOH= VDD-0.30V
IOH
-1.8
mA
VDD=3.0V , VOH= VDD-0.30V
IOH
-3.3
VDD=5.0V , VOH= VDD-0.30V
IOH
-4.8
mA
VDD=1.9V , VOH= VDD-0.30V
IOH
-1.4
mA
VDD=3.0V , VOH= VDD-0.30V
IOH
-2.5
VDD=5.0V , VOH= VDD-0.30V
IOH
-3.3
VDD≥2.2V, VOH=VregLog-0.1v
IOH
-2
2.6
2.8
Output High current
Port B[3], Port B[0]
Port B[2], Port B[1]
Port C[3:0]
Port C[1] (note 1)
-1.9
-2.6
-1.9
mA
mA
mA
mA
-1.25
mA
Note 1 : Depending on the Mask Option sheet. By default the SWB data level (on PPC[1]) will be equal to
VDD. With option MSWBdataLevelB, the level of PPC[1] will be selected as VregLogic
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EM6640
18.10 DC characteristics - pull up/down
Conditions: T=25°C (unless otherwise specified)
Parameter
Conditions
Symb
Min.
Typ.
Max.
Unit
Input Pull-down
VDD=1.9V, Pin at 1.9V
RPD
15k
Test
VDD=3.0V, Pin at 3.0V
RPD
VDD=5.0V, Pin at 5.0V
RPD
15k
Ohm
Input Pull-down
VDD=1.9V, Pin at 1.9V, weak
RPD
200k
Ohm
Port A,B,C (note 1)
VDD=3.0V, Pin at 3.0V, weak
RPD
300k
Ohm
VDD=5.0V, Pin at 5.0V, weak
RPD
450k
Ohm
Input Pull-up
VDD=1.9V, Pin at 0.0V, weak
RPU
350k
Ohm
Port A,B,C (note 1)
VDD=3.0V, Pin at 0.0V, weak
RPU
200k
Ohm
VDD=5.0V, Pin at 0.0V, weak
RPU
150k
Ohm
Input Pull-down
VDD=1.9V, Pin at 1.9V, strong
RPD
97k
Ohm
Port A,B,C (note 1)
VDD=3.0V, Pin at 3.0V, strong
RPD
VDD=5.0V, Pin at 5.0V, strong
RPD
98k
Ohm
Input Pull-up
VDD=1.9V, Pin at 0.0V, strong
RPU
102
Ohm
Port A,B,C (note 1)
VDD=3.0V, Pin at 0.0V, strong
RPU
VDD=5.0V, Pin at 0.0V, strong
RPU
9K
70k
70k
15k
96k
97k
Ohm
22K
Ohm
130k
Ohm
130k
Ohm
96k
Ohm
Note 1 : Weak or strong are standing for weak or strong pull transistor. Values are for R1typ=85kOhm.
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EM6640
n`P
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19. Pad Location Diagram
w [P PQ N
EM 6640
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20. PACKAGE & Ordering Information
TSSOP 16
TSSOP16 (0.65mm pitch, 4.4mm body width)
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EM6640
SOP 16
SOP-16(1.27mm pitch, 300mils body width)
SOP 18
SOP-18 (1.27mm pitch, 300mils body width)
NB : Pin N°17 & N°18 are not connected.
This package is fully compatible with the MFP version (EM6540)
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EM6640
20.1 Ordering Information
Packaged Device:
Device in DIE Form:
EM6640 %%% TP16 B
EM6640 %%% WS 11
Customer Version:
customer-specific number
given by EM Microelectronic
Customer Version:
customer-specific number
given by EM Microelectronic
Package:
SO16, SO18 = 16/18 pin SOIC
TP16 = 16 pin TSSOP
Die form:
WW = Wafer
WS = Sawn Wafer/Frame
WP = Waffle Pack
Thickness:
11 = 11 mils (280um), by default
27 = 27 mils (686um), not backlapped
(for other thickness, contact EM)
Delivery Form:
A = Stick
B = Tape&Reel
Ordering Part Number (selected examples)
Part Number
Package/Die Form
EM6640%%%TP16A
EM6640%%%TP16B
EM6640%%%SO18B
EM6640%%%WS11
EM6640%%%WP11
16 pin TSSOP
16 pin TSSOP
18 pin SOIC
Sawn wafer
Die in waffle pack
Delivery Form/
Thickness
Stick
Tape&Reel
Tape&Reel
11 mils
11 mils
Please make sure to give the complete Part Number when ordering, including the 3-digit version. The version is made of 3
digits %%%: the first one is a letter and the last two are numbers, e.g. P04 , P12, etc.
20.2 Package Marking
SOIC marking:
First line:
Second line:
Third line:
TSSOP marking:
E M 6 6 4 0
0 % % Y
P P P P P P P P P P P
C C C C C C C C C C C
6
P
6
P
4
P
P
0 % %
P P P
P P Y
Where: %% = last two-digits of the customer-specific number given by EM (e.g. 04, 12, etc.)
Y = Year of assembly
PP…P = Production identification (date & lot number) of EM Microelectronic
CC…C = Customer specific package marking on third line, selected by customer
20.3 Customer Marking
There are 11 digits available for customer marking on SO16/18.
There are no digits available for customer marking on TSSOP16.
Please specify below the desired customer marking.
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21. Updates of specifications
Revision Date of Update
Name
A/220
16.6.98
B/391
C/446
Chapter
concerned
ALL
01/11/01 PERT All
24/03/02 PERT 62/64
Old Version (Text, Figure, etc.)
New Version (Text, Figure, etc.)
Spelling Corrections, Figure
updates, added Die size and
Package drawings, added graphs
Change heater & footer Add URL.
Change Pad Loc. Diagram &
ordering information
-
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