EM MICROELECTRONIC - MARIN SA
EM6635
Low Power Microcontroller with RC and 32kHz oscillators
and 9 high drive outputs
Features
Figure 1. Architecture
32’768Hz crystal oscillator
500kHz RC Oscillator (no external component)
External clock (metal option)
9 High drive outputs: up to 20mA
Melody generator with 255 programmable
frequencies
True Low Power: 1.5uA active mode
0.4uA halt mode
Crystal
Oscillator
32kHz
External
clock
or
ROM
4096 x 16Bits
Watch Dog
timer
RAM
256 x 4Bits
RC Oscillator
500kHz
Timer 1
VLD 3levels
Timer 2
Core
EM6600
Frequency
Doubler
B CD
Counter
@ 1.55V, 32kHz, 25°C
Low Supply Voltage 1.2V to 3.6V
Max. 14 Inputs with selectable debouncers; Port P1,
P2, P6, P70, P71
Max. 15 outputs (9 I/O High drive outputs); Port P3,
P4, P6, P70, P71, P72
Mask ROM 4096 x 16bits
RAM 256 x 4bits
2 clocks per instruction cycle
72 basic instructions
2 outputs; Reset OUT, Buzzer OUT
2 timers 8bits
2 x 4 bits BCD counters
Event counter 3bits
Prescaler down to 1Hz (crystal =32kHz), readable by
CPU in 2 ranges
Serial Port as selectable configuration of Port 5
18 Interrupts: 12 internal, 6 external
Voltage Level Detector, 3 levels software selectable
Die form and MLF2, 40 pin (Micro Lead Frame)
package
Power Supply
Voltage reg.
Frequency
Generator
Reset
Logic
Interrupt
Controller
Port 1
0 1 2 3
Port 2
0 1 2 3
Port 3
0 1 2 3
Port 4
0 1 2 3
Port 5
0 1 2 3
Serial or
parallel port
High Drive Output
Port 7
0 1 2 3
2 : High Drive Output
3 : Buzzer out
Figure 2. Typical application
Stepping Motors
P4
SIO
P3
PI E Z O
V BAT
P72
P5
BZ
P1
CENV
EM6635
P2
P6
+V BAT
P70,P71
+VBAT
Reset Out
Reset IN
QIN
Description
The EM6635 is a low voltage, low power microcontroller
containing 9 integrated high-drive outputs able to provide
up to 20mA. It is ideal for use in applications in which one
must drive devices such as motor drivers, small stepping
motors, LEDs, triacs, external EEPROM or other ICs in
the system.
EM6635 has both a 32kHz crystal oscillator and a
500kHz RC oscillator without external component, as well
as an external clock to be driven up to 4MHz.
The CPU operating clock can be switched from crystal to
RC oscillator for high-speed operation.
It has a frequency/melody generator with 255
programmable frequencies for quality buzzer.
Port 6
0 1 2 3
QOUT
VSS
VRR
C VRR
32kHz Xtal
Applications
Watch & clock
Timer / sports timing devices
Security / industrial
Toys
Sensor interface
The EM6635 contains the equivalent of 8kB mask ROM
and the RAM has a capacity of 256x4 bits.
It also has a power-on reset, watchdog timer, 2 timers
8bits, 2 BCD counters, 3bits event counter, 4 wire serial
port 8bits and several clock functions.
03/03 REV. B
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EM6635
EM6635 at a glance
Power Supply
Low voltage low power architecture
including internal voltage regulator
1.2 to 3.6 V battery voltage
1.5µA in active mode (Xtal, 25°C)
0.4 µA in HALT mode (Xtal, 25°C)
32’768Hz Crystal Oscillator
500kHz RC oscillator (no external component)
External clock (metal option)
-
RAM
- 4 pages of 64 x 4bits, page 0 is direct addressable
ROM
- 4096 x 16bits, metal mask programmable
CPU
4-bits RISC architecture
2 clock cycles per instruction (CPI=2)
72 basic instructions
operating frequency selectable by SW
-
Main Operating Modes and Resets
Active mode, CPU is running
Halt mode, CPU in halt, peripheral are running
Initial reset on power on (POR)
Watchdog reset (logic)
Reset terminal with Schmitt Trigger
Reset with input combination on Port P1 & Port P2
(register selectable)
-
Prescaler
15 stage system clock divider from 32kHz down to 1Hz
4 Interrupt requests; 128Hz, 64Hz, 32Hz and 1Hz or
64Hz, 16Hz, 8Hz and 1Hz
Prescaler state readable to CPU from 128Hz to 16Hz
and from 8Hz to 1Hz
Prescaler reset (32Hz to 1Hz)
-
-
8bit Serial Interface at Port 5
4 wire (serial clock In/Out, serial output, serial status
In/Out (RDY), serial input)
Master mode: 32kHz, 16kHz or 4kHz serial clock
Slave mode: external clock from P33
Selectable word length: 8 - 7 - 6 - 5 bit
Selectable synchronized or direct output
Selectable positive or negative active clock edge by
direct or inverted serial clock SCK
Special ready output mode when port is in master mode
RDY can be set by SW
-
-
Frequency Generator with 255 output frequencies
8bit programmable frequency divider
50% duty cycle output signal
Clock frequency is 65536Hz (doubled 32768Hz)
SW activated
-
Watchdog Timer
- Creates watchdog reset after time-out
- Can be disabled by SW and mask option
Interrupt Controller
- 12 internal, 6 external interrupt request sources
- Individually maskable, individually resettable
- Global interrupts disable,with auto-enable at HALT mode
Voltage Level Detector (SVLD)
- 3 software selectable levels
- Busy flag during measure
- Active only on request during measurement to reduce
power consumption
Timer 1
- 8bits timer with 3 modes: Zero Stop, Synchron Mode
and Auto Reload Mode
- Timer clock selectable 4kHz-2kHz-1kHz-512Hz by SW
- Zero Stop: Timer starts counting down when loaded from
CPU with data (> 0). When at zero, an interrupt is
generated.
- Synchron Mode: After loading by CPU, timer starts
synchronized by the positive edge of the prescaler 64Hz
signal. An interrupt is generated when timer reaches
zero. During timer count down, Port P3 and P4 are
outputting their data, otherwise P3 and P4 are at high
level (acc. to selected port configuration).
- Auto Reload Mode: (see text at Timer 2)
Timer 2
- 8bits timer with 2 modes: Zero Stop and Auto Reload
- Zero Stop as timer1
- Auto Reload mode: Timer starts when a non-zero data is
loaded by CPU and counts down to zero. Then the
loaded data (internally stored) is automatically reload to
the timer counter and the sequence starts again. Each
time when zero is reached, an interrupt is generated.
- Timer clock selectable 256Hz-64Hz-16Hz-4Hz by SW
CHRONO 2x4bits BCD counters
- Start, stop, reset by SW
- 1/100th second resolution
- CARRY flag can be read by SW when the counter
changes from 99 to 0
Event Counter 3bits
- Associated to input port P10, P11; readable to CPU
- Counter counts up to 7 and stays there
- Counter reset by CPU-write
Buzzer Output
- Piezo driver via external NPN transistor
- Activated together with frequency generator
Input Ports P1, P2
- Direct or debounced input read selectable by SW for
each port
- Clocked pulldown or no pulldown by mask option
- P1: Edge detector at P10, P11 (both edges) to generate
pulse for event counter
- Interrupt by P12: both edges, by P13: both edges
- Interrupt by positive edge (debounced) of any P2 input
- Reset by debounced input combination: P13, P22, P23 =
high, enabled by SW
Input / Output Ports P3, P4, P5, P6, P7
- High current drive capability at P3, P4 and P72
- P3, P4: Common direction select P30-P32, P40-P42;
P33 and P43 are individually selectable
- P5: individual direction select, debouncer when input
- As input: direct read of terminal data, as output: register
data
- P3,P4,P72: selectable 9,8,7,6,5,4 or 3 high drive output
in combination with special synchron mode of timer 1
- P5: pull down / pull up according to mask option
- P6: As input: Direct or debounced input read selectable by
SW
- Interrupt by positive edge (debounced) of any P6 input
- Common direction select P60-P61, P62-P63
- P70, P71: As input: Direct or debounced input read
selectable by SW for each port
- Interrupt by positive edge (debounced) of P70, P71 input
- Common direction select P70, P71
03/03 REV.B
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EM6635
1. Pin Description
Package
MLF2
Function
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Ports
P23
P22
P21
P20
BZ
RESET OUT
VSS
TCK
TESTRC
QOUT
QIN
System
Power Supply
Test
Oscillator
Test
System
Power Supply
System
Ports
Power Supply
Ports
TEST
CENV
VRR
RESET IN
P71
P70
P63
P62
P61
P60
P53
P52
P51
P50
VBAT (VDD)
P13
P12
P11
P10
P72
P43
P42
P41
P40
P33
P32
P31
P30
NC/P63
Type Description
I
I
I
I
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input port with selectable debouncer
Input port with selectable debouncer
Input port with selectable debouncer
Input port with selectable debouncer
Buzzer output
Reset output
negative supply, substrate
EM test access, must be without any connection
EM test access, must be without any connection
32 kHz quartz connection, input or External clock (metal option)
32 kHz quartz connection, output
Not connected
EM test access, must be without any connection
Capacitor connection for envelop control tw. VSS
Regulated supply voltage, capacitor connection tw. VSS
active high reset input
Input/output; low current drive
Input/output; low current drive
Input/output; low current drive
Input/output; low current drive
Input/output; low current drive
Input/output; low current drive
Input/output: configurable as serial clock I/O: SCK
Input/output: configurable as serial output:
SOUT
Input/output: configurable as serial status I/O: RDY
Input/output: configurable as serial input:
SIN
Positive supply, capacitor tw. VSS (C depends on VBAT noise)
Input port with selectable debouncer and edge detector
Input port with selectable debouncer and edge detector
Input port with selectable debouncer and edge detector
Input port with selectable debouncer and edge detector
Input/output; high current drive
Input/output; high current drive
Input/output; high current drive
Input/output; high current drive
Input/output; high current drive
Input/output; high current drive, P33 configurable as Fout
Input/output; high current drive
Input/output; high current drive
Input/output; high current drive
Not connected
03/03 REV. B
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EM6635
2. Peripheral Memory Allocation
Address HEX
0 - 3F
40 - 46
47 – 4C
4D - 4F
50 - 55
56 – 5E
5F
60 – 6B
6C
6D
6E
6F
70 - 74
75, 76
77
78
79 – 7D
7E
7F
Peripheral Function
Data RAM page 0, 1, 2, 3
HW Control, Configuration
Input/output Ports
Free
Input/output Ports
Timer1, Timer2, BCD counter
Free
Event Counter, Freq. Generator
Interrupt Controller
Supply voltage level detector
RC-Oscillator
CPU Index Reg. Low
CPU Index Reg. Hi
Serial Interface
EM Test
RAM Page Register
Reserved
Free
EM Test
EM Test
Special Access Modes for HW-Control 1 and -2:
There are two HW-Control registers (HW-Ctl-1, HW-Ctl-2) with different access modes. Each of these two registers can be
accessed by two different addresses. The access by address H40 for HW-Ctl-1 (H42 for HW-Ctl-2) is the normal access
method as every other register in the EM6635: The corresponding data bus value is written into the register bit.
Using address H41 (HW-Ctl-1) or address H43 (HW-Ctl-2) allows a bitwise access to the register. The CPU has not to care
about the states of the register bits which must not be modified.
With a high level at bits 0 to 2, the corresponding bits in the register are selected, while a low level unselects the register
bits. The level of bit 3 defines the action on the selected bits: a high level will set and a low level will clear the selected
register bits. Read access is done in the normal way.
If bits 0, 1, 2 are not selected (at Low level), the register at bit 3 is set if bit 3 is high or reset if it is low.
This concerns SelTBCapHi at HW-Ctl-2, address H43.
2.1 RAM Address Modes
The EM6635 has 4 pages of 64x4bits RAM’s built-in. The page number is coded on 2 bits, there are 4 pages.
The page number is stored on RAM index register at address H77.
The RAM is directly addressable on addresses decimal (0 to 63), and it is paged adressable.
To write or read the RAM page1, 2, 3 the user has first to set the offset value in the RAM Index register.
RAM index
PageSel[0]
0
1
0
Page
PageSel[1]
0
0
1
1
0
1
2
1
3
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EM6635
Ram Architecture
Add
Page
0
64x4 direct addressable
RAM
RAM_0
4 bit R/W
RAM_1
4 bit R/W
RAM_2
4 bit R/W
RAM_3
4 bit R/W
•
•
•
•
•
•
•
•
RAM_60
4 bit R/W
RAM_61
RAM_62
RAM_63
4 bit R/W
4 bit R/W
4 bit R/W
Add
Page
64x4 indirect addressable
RAM
RAM_0
4 bit R/W
1
•
•
•
•
•
•
RAM_63
Add
Page
64x4 indirect addressable
RAM
RAM_0
4 bit R/W
•
•
•
•
•
•
•
•
2
4 bit R/W
RAM_63
Add
Page
64x4 indirect addressable
RAM
RAM_0
4 bit R/W
•
•
•
•
•
•
•
•
•
•
3
4 bit R/W
RAM_63
4 bit R/W
CPU Access Format:
Register
RAM index
Add Hex
77
Add Dec
119
W
R
bit3
x
0
bit2
x
0
bit1
PageSel[1]
PageSel[1]
bit0
PageSel[0]
PageSel[0]
3. Operating Modes
The EM6635 has two low power operating modes, the active and the halt mode. The oscillator is always active in both
modes, whereas the RC-Oscillator is controlled by the CPU.
3.1 Active Mode:
The CPU is running. Instructions are read from the internal ROM and executed by the CPU.
After a system reset, the EM6635 is in active mode at ROM-address H000.
The active mode is stopped by executing the HALT instruction.
3.2 HALT Mode:
After a HALT instruction, the EM6635 is in HALT mode. The CPU is stopped. The 32kHz-oscillator, the prescaler are
running, whereas the timers, the watchdog timer, the BCD counters and the frequency generator are only working, if
activated before.
The RC-oscillator is stopped.
All registers, RAM and output buffers retain their states prior to HALT mode.
The HALT mode is left by an interrupt occurence or by a system reset.
The HALT command enables the global interrupt, i.e. DisINT=0.
Note: HALT mode is activated and XTAL Oscillator is not running. Only a system reset allows to go back in Active mode.
4. Power Supply
The EM6635 is supplied by a single external power supply between VDD (VBAT) and VSS (Ground).
A built-in voltage regulator generates VRR providing regulated voltage for the oscillator and the internal logic. The output
drivers are supplied directly from the external supply VDD. The internal power configuration is shown below in figure 3.
To supply the internal core logic it is possible to use either the internal voltage regulator (VRR < VDD) or VBAT directly (VRR =
VDD). The selection is done by mask option. By default the voltage regulator is used. Refer to chapter 17 for the mask
options.
The internal voltage regulator is chosen for high voltage systems. It saves power by reducing the internal core logic’s power
supply to an optimum value. However, due to the inherent voltage drop over the regulator the minimal VDD is restricted to
1.4V.
A direct VBAT connection can be selected for systems running on a 1.5V battery. The internal RFIL 1kOhm resistor
together with the external capacitor on VRR is filtering the VDD supply to the internal logic (as a low pass filter to protect the
logic against parasitic over- and under-voltages, e.g. created by piezo shocks).
In this case the minimum VDD can be as low as 1.2V.
The output buffers are directly supplied from the external power supply.
Note: State of I/O pads may not be defined until VRR reaches typ. 0.8V and Power-On-Reset supplied by VRR clears them
to inputs.
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EM6635
MVreg
Terminal
VBAT
OP16B
_
OP16A
+
All Pad
input &
output
buffers,
SVLD
Terminal
VRR
RFIL
Ref.
Logic
CPU, ROM, RAM
Peripheral Logic,
Oscillator, POR
Fig.3: Power Supply Principle
5. Reset
The EM6635 has 4 reset sources:
- the Power On Reset
- external reset input
- reset by input combination
- watchdog timer reset
If one of these reset sources becomes active, a system reset is generated. All registers are set to their corresponding initial
values and the program counter of the CPU is set to H000.
If the EM6635 is in HALT mode, it is reset to active mode.
An internal Cold Start delay is triggered from the system reset, which holds the CPU in reset state until its time out. This
ensures that the crystal oscillator can settle to stable oscillation.
The Cold Start delay time can be selected by mask option OP-2.
The Cold Start can be disabled by input P22 AND P23 = 1, if this input combination is applied longer than the duration of
SYSRES signal (SYSRES terminates after the oscillator start time plus 10 valid clock time periods.) If this condition
becomes active after the SYSRES has changed to low, but during an active Cold Start, the Cold Start will be stopped
immediately. During the CPURES (corresponds to the Cold Start, after system starts on Xtal oscillator), pull down
transistors are active at all port inputs.
Note that all 4 reset sources are triggering the Cold Start delay.
Schmitt Trigger
RESETIN
DisInpResN
P13
P22
P23
Ck1Hz
DisWD
Debouncer
Watch Dog Timer
System
Reset
OP1A
Set
OP1B
CkCS
Power On
Reset
SYSRES
OP3A
OP2ABCD
Cold Start
Timer
OP2E
CPURES
Reset
OP3B
OP9A
OP9B
Fig.4: Reset Structure
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EM6635
5.1 Power On Reset
The Power on Reset can be activated by mask option OP-3A.
When the positive power supply VBAT is applied, the internal logic supply voltage VRR rises to the VBAT value with a time
constant given by the filter resistor RFIL and the external capacitor CVRR. The POR cell is active until VRR becomes
higher than the trigger voltage VPOR of the POR cell. The output signal of the POR cell triggers the system reset.
The EM6635 has two oscillation circuits (refer to chapter 6 for the oscillators).
With the metal option OP-20A, the oscillation circuit starts the operating clocks from RC oscillator.
With the metal option OP-20B, the oscillation circuit starts the operating clocks from XTAL oscillator.
With the metal option OP-20C, the input P50 selects the RC oscillator or XTAL oscillator during SYSRES.
A high level at P50 terminal activates the RC oscillator, a low level activates XTAL oscillator.
VBAT
VRR
POROut
P50
Cold start delay
SYSRES
Reset OUT
CPURES
Cold Start flag
EnRc
OscSwitch
10 Valid Clocks
RC-Osc
CPUclk
Xtal32k
CkPerif
Fig.5: Power On Reset Timing and Clock Generation after System starts on the RC Oscillator
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EM6635
VBAT
VRR
POROut
P50
Cold start delay
SYSRES
CPURES
Reset OUT
Cold Start flag
EnRc
OscSwitch
RC Osc
CPUclk
10 Valid Clocks
Xtal32k
CkPerif
Fig.6: Power On Reset Timing and Clock Generation after System starts on Xtal Oscillator
5.2 External Reset Input
A high level on the reset input "RESET" creates a system reset as long as it is applied. The reset input has an internal pull
down resistor RRES, and includes a Schmitt Trigger circuit. The reset input creates the system reset in the same way as
the POR signal, both are triggering the Cold Start delay for oscillator stabilisation.
5.3 Input Reset
If input reset is enabled by bit 3 of Config-2 register (at "0" level, address H45, in "DisInpRes"), a high level at input port P13
together with high levels at port P22 and P23 is creating a system reset after a debouncing time of 1.95ms (1 period of
512Hz). This reset is maintained as long as this input condition is applied.
5.4 Watchdog Timer Reset
The watchdog timer is a 2bits timer counting on rising edges of Ck1Hz. It generates a system reset if it is not cleared by the
CPU periodically (writing "1" to HW-Ctl-1, bit 0, address H41).
This resets the watchdog timer to zero and timer operation restarts by counting up. Writing "0" has no effect.
The watchdog timer counts also in halt mode, therefore the standby duration must not exceed the watchdog time out tWD =
3-4sec to avoid a system reset.
Note: a prescaler reset is shortening the watchdog time out.
It is recommended to reset the watchdog timer periodically with the 1Hz interrupt.
The watchdog timer function is inhibited, if the input ports P22 and P23 are at high level, if this is enabled by mask option
OP-9A.
The watchdog timer can be disabled by Config-1 register, bit 2 at high level (H44), or by mask option OP-1B.
CPU Access Format:
Register
HW-Ctl-1
bit access
Config-1
Config-2
Add Hex
41
Add Dec
65
44
68
45
69
W
R
W
R
W
R
bit3
bit2
0
(Mot3Mode)
(Mot3Mode)
DisInpRes
DisInpRes
0
DisWD
DisWD
P5DebOn
P5DebOn
bit1
(DisINT)
(DisINT)
(EnFOut)
(EnFOut)
P2DebOn
P2DebOn
bit0
ResetWD
0
(SellINT8)
(SellINT8)
P1DebOn
P1DebOn
5.5 Reset Output
The Reset output outputs the CPU-reset signal. This signal is triggered by a system reset and its duration is the oscillator
start time plus the cold start delay time.
The output buffer has the same electrical parameters as the port P5 output buffers.
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EM6635
6. Oscillators
By metal option the 32kHz quartz oscillator can be replaced by external clock coming from QOUT terminal.
When external clock is used Xtal oscillator can not work.
6.1 32kHz Oscillator
The 32768Hz quartz oscillator of the EM6635 is working and supplies the timing functions with precise clock frequencies.
The necessary oscillator capacitors are integrated within the EM6635, therefore the only external element needed is the
32kHz quartz.
The external impedance between QOUT and QIN terminal must be higher than 10MOhm.
As this type of oscillator has a relatively slow start-up behavior, precautions are necessary to make sure, that always
corrects 32Khz clock signals are provided at the system start. The flag ColdStart in “RCOSC” to high level (bit2, address
H6D) indicates an active Quartz Oscillator ColdStart delay when circuit starts to run under RC oscillator and ColdStart is not
finished yet.
The 32kHz signal can be used to clock the µProcessor. This selection is done by setting OscSwitch in “RCOSC” to low level
(bit 0, address H6D). The default selection at system start is the RC oscillator (metal option OP-20 A) or the Quartz
oscillator (metal option OP-20 B).
6.2 RC Oscillator
The EM6635 has an internal RC oscillator, which delivers a fast clock for the µProcessor. This RC oscillator can be
switched On or Off by the CPU with EnRC in “RCOSC” (bit 1, address H6D). A high level activates the RC oscillator. After a
system start, the RC oscillator is active (metal option OP-20 A is selected).
The µProcessor can be configured to run with the 32kHz clock of the Quartz Oscillator. In this case, the RC oscillator can
be set inactive. This selection is done by setting OscSwitch in “RCOSC” to low level.
CPU Access Format:
Register
RCOSC
Add Hex
6D
Add Dec
109
bit3
bit2
bit1
bit0
W
x
x
EnRC
OscSwitch
R
0
ColdStart
EnRC
OscSwitch
Note1: “RCOSC” register value is depending on supply voltage and metal option. With the metal option: OP-20B,
Init=0100 and OP-20A, Init=0111. When 3.00V range is operating, register value can be set to 0111. When very
low voltage e.g.1.2V is operating, register value must be set to 0000.
6.3 External Clock Input
RC and/or external clock where external clock replaces the Xtal frequency and supplies the main prescaler.
These inputs must be specified according to mask option OP-19 and OP-20. See chapter 17.
QOUT terminal becomes the external clock.
6.4 Clock Switching Notes
When switching the CPU from Quartz Oscillator to RC Oscillator, it’s start-up time of max. 1ms must be respected. First
EnRC must be set to 1 and after 1ms also OscSwitch can be set to 1. In order to synchronise the internal logic a Xtal clock
of 32kHz is taken into account, then the RC Oscillator delivers fast clocks to the µProcessor.
The internal voltage regulator at VRR terminal increases of 280mV typically. The stabilisation is depending of external loads
(CVRR minimum = 100nF).
When switching off the RC Oscillator, first OscSwitch must be set to 0 and earliest in the following instruction EnRC can be
cleared to 0. The internal voltage regulator decreases to its initial value.
An error in the CPU operation can result if the 2 sequences are not performed correctly.
EnRC
OscSwitch
RC-Osc
CPUclk
Xtal32k
CkPerif
Fig.7: Clock Switching from RC-Oscillator to 32kHz and back
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EM6635
7. Prescaler
The prescaler is a 15 stages divider chain, which delivers clock signals for the peripheral circuits such as timer, frequency
generator, debouncer, etc. The input is the 32768Hz system clock from Quartz Oscillator or external clock.
Note: if external clock is applied it should be also 32768Hz to keep timing specified in this specification, in other case all
timing change relative to external clock compared to 32768Hz.
The system reset initialises the prescaler to all 0, except the 1s stage, which is set to 1.
The prescaler generates four interrupt requests: INT-TB1, INT-TB2, INT-TB3, INT-TB4.
The source is selected by Sel/INT8.
Sel/INT8
Interrupt
TB1
TB2
0
1Hz
64Hz
1
1Hz
8Hz
TB3
32Hz
16Hz
TB4
128Hz
64Hz
Both interrupts appear at the positive edge of the corresponding signal.
The first INT_TB1 occurs 1 sec after the end of the system reset.
The prescaler can be reset partially from 32Hz to 1Hz by writing "1" to "ResetCK" of HW-Ctl-2 (bit 0 at address H43). A read
access to that bit gives always "0".
Note: this prescaler reset shortens the watchdog time out tWD.
The prescaler creates a clock signal for the clocked pull down at inputs, e.g. at port P1. This is a 512Hz signal with an
active time of 31µs if OP-6A is chosen or 64µs at OP-6B.
7.1 Time Base Capture
The state of the prescaler stages 128Hz to 16Hz and 8Hz to 1Hz can be read by the CPU by a read access to address H55
(a write has no effect). The range selection is done by bit 3 of HW-Ctl-2, address H42 or H43. A "1" at this "SelTBCapHi"
selects the range from 128Hz to 16Hz for read.
This time base capture capability is mostly designed for 4 bits application. The corresponding data are directly read from the
prescaler. If two consecutive capture accesses are made to read the two ranges, the resulting data representation (8 bits)
may not be coherent, due to a possible prescaler update event occuring to the 128 Hz stage plus its correlated carry to the
following stages.
8. EM6635 Input / Output Ports
8.1 Input Port P1
The port P1 is a 4bits input port used to read the terminal logic levels P10 to P13 into the CPU.
The port is equipped with 4 debouncers, which can be enabled by signal "P1DebOn", commonly for all 4 bits. With
debouncers active, any input level must be present glitch free for at least the debounce time tDEB=1.95ms, to be
transferred to the debouncer output, which can be read by the CPU.
When "P1DebOn" is at "0" level, the port P1 inputs are directly passed to the debouncer outputs.
DEBOUNCER function (signal must be stable during two Deb Clk rising edges)
Debouncer
Clock 512Hz
1
1
1
2
1
2
1
2
1
Reset System
glitch between two clocks
Fig.8: Debouncer function
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The port P1 has several special functions assigned to its inputs:
8.1.1 Edge Detector
The port input P10 and P11 have edge detectors connected to the corresponding debouncer outputs. Both edge detectors
create output signals of 488us at positive and negative edges. Each edge detector pulse from P10 or P11 input creates a
pulse "M", which is the clock input for the event counter. Every change at P10 or P11 creates an "M" pulse.
Also, an interrupt "M" is generated by this signal
The P13 input is logically combined as "AND" with P22 and P23 input, then input into a debouncer, whose output creates an
Input Reset if enabled.
8.1.2 Input Interrupt
The port P12 input (after debouncer) is connected to an edge detector, active at positive and negative edges. Its 488us
output signal creates an interrupt P12 in register INT-Stat-2 (bit 0, address H66).
The port P13 input (after debouncer) is connected to an edge detector, active at positive and negative edges. Its 488us
output signal creates an interrupt P13 in register INT-Stat-2 (bit 1, address H66).
8.1.3 Input Pull Down
Each P1 input has associated pulldown transistors. These NMOS transistors are activated with a 512Hz signal with the
duration of 31us (OP-6A) or 62us (OP-6B). A "0" input level is additionally hold by the circuitry shown in fig.8:
P1
to Port Logic
512Hz PD_Control
Fig.9: Port P1, P2 Input Pull Down
The pull down elements at port 1 can globally be disactivated by mask option OP-7B.
Note: Extra pull down transistors are active at this port during the CPURES signal.
CPU Access Format:
Register
Config2
Port P1
Add Hex
45
Add Dec
69
47
71
W
R
R
bit3
(DisInpRes)
(DisInpRes)
P13
bit2
(P5DebOn)
(P5DebOn)
P12
bit1
(P2DebOn)
(P2DebOn)
P11
bit0
P1DebOn
P1DebOn
P10
8.2 Input Port 2
The port P2 is a 4bits input port used to read the terminal logic levels P20 to P23 into the CPU.
The port is equipped with 4 debouncers, which can be enabled by signal "P2DebOn" commonly for all 4 inputs. With
debouncers active, any input level must be present glitchfree for at least the debouncer time tDEB =1.95ms, to be
transferred to the debouncer output, which can be read by the CPU.
When "P2DebOn" is at "0" level, the port P2 input is directly passed to the debouncer outputs.
Port 2 Interrupt:
Each debouncer output of port 2 is connected to the input of a positive edge dedector. The 4 edge detector outputs are
logically combined as OR to create the P2 interrupt signal INT-P2 (bit 1, address H68).
In this way, any valid positive transition at P2 input can create an interrupt if not masked.
The P22 and P23 inputs are combined logically as "AND" with P13 input and applied to a debouncer. The debounced signal
can create an Input Reset if not disabled by "DisInpRes".
Each P2 input has associated pull down transistors. These NMOS transistors are activated with a 512 Hz signal with the
duration of 31µs (OP-6A) or 62µs (OP-6B). A "0" input level is additionally hold by the circuitry shown in Fig. 8.
The pull down elements at port P2 can globally be disactivated by mask option OP-14B.
Note: Extra pull down transistors are active at this port during the CPURES signal.
CPU Access Format:
Register
Config2
Port 2
Add Hex
45
Add Dec
69
48
72
W
R
R
bit3
DisInpRes
DisInpRes
P23
bit2
(P5DebOn)
(P5DebOn)
P22
bit1
P2DebOn
P2DebOn
P21
bit0
(P1DebOn)
(P1DebOn)
P20
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8.3 Input/Output Port P3
The port P3 is a 4bit input/output port with high current drive capability, e.g. for watch motor driver.
The port direction is controlled by the "PIO43 Ctl" register at address H52. The bit "P3-Dir" (bit 0, address H52) defines the
direction of P30 to P32 commonly, whereas "P33-Dir" (bit 2, address H52) defines the individual direction of P33. A "1" level
of the direction bit configures the corresponding port to be output, a "0" level defines it as input.
If the port P3 is configured as output, a write access to the P3 data register (address H50) stores the data into the internal
port data register and the data appear at the corresponding port terminals. The port data register is only written when the
port bit is output.
If a port P3 bit is read when the port is output, the data comes from the port output register. When the port is input, the data
is read from the port terminal (output buffer in high impedance). The data LSB is at bit 0, the MSB at bit 3.
After system reset, the direction is input, the output data register contains "0000".
At port P3, no pull up or pull down element is available during normal operation.
Note: Extra pull down transistors are active at this port during the CPURES signal.
8.3.1 Frequency Output
With mask option OP-18, the function of the output P33 can be modified directly or under CPU control. If OP-18A is chosen,
the CPU can select with “ENFOut” set to “1”, that the port P33 is set to output, but disconnected from its data register.
Instead, it is configured as frequency output.
The output frequency is defined by the serial clock selection bits "SelSIOClk0, “1" in SIO-Ctl1(bit 3, address H72),
independent of the "EnSIO" state, which enables the serial interface, configurated at port P5.
If the frequency output is set to 32 kHz, the output signal is the system clock from the quartz oscillator. In this case, the
duty cycle is subject to higher tolerances than in case of the other possible output frequencies. If option OP-18B is chosen,
the output P33 is always output for Fout, independently of the setting “ENFOut”.
SelSIOClk1
0
0
1
1
SelSIOClk0
0
1
0
1
Frequency at Fout = P33
according to OP-8: 1kHz - 512Hz - 128Hz - 32Hz
32kHz
16kHz
4kHz
8.3.2 Synchron Mode (Special Motor Mode)
If timer 1 is set to Synchron Mode by "SynMode" = "1", the port P3 operates in a special way, optimised to facilitate driving
of watch motors.
The port must be set to output by the "PIO43-Ctl" register bits "P3-Dir" and/or "P33-Dir". An eventually "EnFOut"
configuration has priority over Synchron Mode setting for port P33.
The Synchron Mode can work with the P30 to P32 bits alone or together with P33, if this port is also set to output and not
frequency output.
Function:
As long as timer1 is not actively counting (its "TimerOn" signal is "0"), all the selected port P3 outputs are in "1" state.
During active timer 1 counting, the selected P3 outputs correspond to the content of the port P3 output data register. The
port state returns to all "1" after timer 1 has finished.
In this way, a predefined pattern loaded in the data output register appears synchronously with the timer 1 action for the
programmed time at the P3 output, driving e.g. a stepper motor. (See also timer 1 description, Synchron Mode).
CPU Access Format:
Register
Port P3
Add Hex
50
Add Dec
80
PIO43 Ctl
52
82
W
R
W
R
bit3
P33 (Fout)
P33 (Fout)
(P43-Dir)
(P43-Dir)
bit2
P32
P32
P33-Dir
P33-Dir
bit1
P31
P31
(P4-Dir)
(P4-Dir)
bit0
P30
P30
P3-Dir
P3-Dir
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8.4 Input / Output Port P4
The port P4 is similar to port P3: it is also a 4bits input/output port with high current drive capability, e.g. for watch motor
driver.
The port direction is controlled by the "PIO43 Ctl" register at address H52. The bit "P4-Dir" (bit 1 of address H52) defines
the direction of P40 to P42 commonly, whereas "P43-Dir" (bit 3 of address H52) defines the individual direction of P43. A
"1" level of the direction bit configures the corresponding port to be output, a "0" level defines it as input.
If the port P4 is configured as output, a write access to the P4 data register (address H51) stores the data into the internal
port data register and the data appear at the corresponding port terminals.
The port data register is only written when the port bit is output.
If a port P4 bit is read when the port is output, the data comes from the port output register. When the port is input, the data
is read from the port terminal (output buffer in high impedance). The data LSB is at bit 0, the MSB at bit 3.
After system reset, the direction is input, the output data register contains "0000".
At port P4, no pull up or pull down element is available during normal operation.
Note: Extra pull down transistors are active at this port during the CPURES signal.
8.4.1 Synchron Mode
As port P3, port P4 can be configured in Synchron Mode. But additionally to the setting of timer 1 in "SynMode", the bit
"Mot3Mode" in "Config1" register (bit 3, address H44) must be set to "0".
In this configuration, the selected number of port outputs can apply the loaded data pattern during timer 1 action to the
output terminals, as explained in port P3 description.
The maximum number of outputs is 9 (included P72), other possible configurations are 8, 7, 6, or 4, 3 using P3 only.
If "Mot3Mode" is set to "1", only port P3 is configured from "SynMode" of timer 1 as Synchron Mode output and P4 is normal
input/output.
CPU Access Format:
Register
Config-1
Add Hex
44
Add Dec
68
Port P4
51
81
PIO43 Ctl
52
82
W
R
W
R
W
R
bit3
Mot3Mode
Mot3Mode
P43
P43
P43-Dir
P43-Dir
bit2
(DisWD)
(DisWD)
P42
P42
(P33-Dir)
(P33-Dir)
bit1
(EnFOut)
(EnFOut)
P41
P41
P4-Dir
P4-Dir
bit0
SelINT8
SelINT8
P40
P40
(P3-Dir)
(P3-Dir)
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8.5 Input / Output Port P5
The port P5 is a 4bits input/output port with normal current drive capability outputs. It can be configured as a serial interface.
8.5.1 Parallel Mode
The direction of each port bit can be defined individually by the "PIO5 Ctl " register (address H54). A bit of this register set to
"1" defines the corresponding port terminal as output.
If the port P5 is configured as output, a write access to the P5 data register (address H53) stores the data into the internal
port data register and the data appear at the corresponding port terminals.
The port data register is only written when the port bit is output.
If a port P5 bit is read when the port is output, the data comes from the port output register. When the port is input, the data
is read from the port terminal (output buffer in high impedance). The data LSB is at bit 0, the MSB at bit 3.
After system reset, the direction is input, the output data register contains "0000".
Note: Extra pull down transistors are active at this port during the CPURES signal.
As input, the port P5 is equipped with 4 debouncers, which can be enabled by signal "P5DebOn" (bit 2, address H45)
commonly for all 4 bits. With debouncers active, the input level must be present glitch free for at least the debouncer time
tDEB=1.95ms, to be transferred to the debouncer output, which can be read by the CPU.
When "P5DebOn" is at "0" level, the port P5 inputs are directly passed to the debouncer outputs.
CPU Access Format:
Register
Port P5
Add Hex
53
Add Dec
83
PIO5 Ctl
54
84
W
R
W
R
bit3
P53
P53
P53-Dir
P53-Dir
bit2
P52
P52
P52-Dir
P52-Dir
bit1
P51
P51
P51-Dir
P51-Dir
bit0
P50
P50
P50-Dir
P50-Dir
8.5.2 Serial Interface Mode
The port P5 is configured as 4 wire serial port, if "EnSIO" (bit 1, address H73) is set to "1".
In this serial mode, the port P5 bits have following functions:
P53: serial clock input/output:
SCK
P52: serial output:
SOUT
P51: serial status input/output:
RDY
P50: serial input:
SIN
It is possible, to select by SW the serial clock frequency, the serial word length, the active clock edge, the output mode and
RDY function. Pull down or pull up resistors can be activated by mask option OP-10.
General Description
For data input, a 5 to 8bit shift register converts the serial input data from the SIN terminal to a parallel format, which can be
read by the CPU. The low nibble is accessible at address H70: "SIO Low-Data" (LSB at bit0) and the high nibble is at "SIO
Hi-Data" at address H71.
For data output, the CPU loads data into the shift register in two steps (SIO Low-Data and SIO Hi-Data), which is then
output serially to SOUT terminal.
It is possible to simultaneously shift data out to SOUT and to shift data in from SIN.
In the master mode, the serial clock is generated internally, corresponding to the selection done by "SIO-Ctl1" (address
H72) and output to SCK.
In slave mode, an external clock is input to SCK.
The active clock edge is selected in "SIO Ctl2" by "NegEdg" bit 2, address H73.
The shift direction is always MSB-first.
The RDY signal controls the serial transmission or indicates to an external circuit, if the serial interface is ready for a new
transmission. RDY is input in master mode and output in slave mode, if not otherwise configured by "SIO Ctl3" register.
As output, RDY can also be set to "1" by the CPU.
After data nibbles are loaded in " SIO Low-Data " and " SIO Hi-Data " registers, the CPU can start a serial transmission by
setting the "RUN" bit3 at "SIO-Ctl2" (address H73) to "1". (By writing "0" to "RUN", a current transmission is stopped without
interrupt.)
In slave mode, the RDY output becomes "1" until the transmission is completed. In master mode, the RDY is input. The
serial interface waits until the RDY input becomes "1" and starts then the transmission. (All RDY level indications are given
for direct input/output selection done in "SIO Ctl3" by SelRDYPol1, -0)
The CPU can read the "RUN" status (bit3 at SIO Ctl2), which is cleared to "0" by the serial port logic when the transmission
has finished.
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As master, the serial port logic generates the number of serial clocks SCK according to the selected word length (in SIO
Ctl1: SelWL1, 0, address H72).
After the last serial clock SCK, an interrupt INT_SIO is generated (bit 0, address H68).
When slave, the external clocks applied to SCK are counted. When the defined number is reached, the transmission is
stopped and interrupt INT-SIO is generated.
With "NegEdg" = "0" ("SIO Ctl2", bit2, address H73) the active SCK clock edge is positive, the shift register shifts at the
negative edge. If "SelSynOut" is set to "1" (synchronised output mode), the output synchronisation is done with the positive
clock edge. If "SelSynOut" is "0", the output SOUT is in direct output mode and changes with the negative clock edge as the
shift register.
When "NegEdg" is set to "1", all above mentioned clock edges are inverted.
The SIO Low-Data and SIO High-Data register can only be read, if EnSIO is set to Hi.
Internal
Clock
uP : Write
Run
Input : RDY
Output : SCK
Shift
Register
eg. 1 0 0 1 0 0 1 1
Direct
SOUT
0100 1100
0
1
Synchr.
SOUT
1
SIN
0
0
0
0
1
1
0
0
1
0
0
1
1
1
0
0
1
1
0
0
INT_SIO
Fig.10A: Serial Interface Operation Timing in Master Mode, 8bit, positive clock
Internal
Clock
uP : Write
Run
Input : RDY
Output : SCK
Shift
Register
Direct
SOUT
eg. 0 1 0 0 1 0 (0 0)
0 0 1 1 1 0(0 1 )
0
0
1
0
1
Synchr.
SOUT
0
1
0
0
SIN
0
0
1
1
(0)
0
1
1
0
0
INT_SIO
Fig. 10B: Serial Interface Timing in Master Mode, 6 bit, negative clock
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EM6635
Internal
Clock
uP : Write
Run
Output : RDY
Input : SCK
Shift
Register
1 0 1 1 0(1 1 1)
Direct
SOUT
Synchr.
SOUT
0
1
1
1
SIN
1
1
0
0
1
1
0
1
1
0
0
INT_SIO
Fig. 10C: Serial Interface Timing in Slave Mode, 5 bit, positive clock
The register "SIO Ctl1" defines the serial clock frequency with "SelSIOClk1, 0" at bit 3, 2 and the serial word length with
"SelWL1, 0" at bit 1, 0.
SelSIOClk1
0
0
1
1
SelSIOClk0
0
1
0
1
SelWL1
0
0
1
1
SelWL0
0
1
0
1
SCK Frequency
ext. clock: Slave Mode
32kHz internal: Master Mode
16kHz internal: Master Mode
4kHz internal: Master Mode
RDY
Output
Input
Input
Input
Fout
acc. Option
CK32K
CK16K
CK4K
Serial Word Length
8 bit
7 bit
6 bit
5 bit
The mode of port P5 and output mode of serial mode are defined by "SIO Ctl2", "EnSIO" and "SelSynOut" according to
following table:
EnSIO
0
1
1
SelSynOut
x
0
1
Port 5 Mode
Parallel Input/output
Serial Port, direct Output
Serial Port, synchronized Output
With "SIO Ctl3", the mode of the RDY signal can be defined in multiple ways. The polarity of RDY output and input is
selected with "SelRDYPol1, -0" (bit 1, 0 of address H74) according to following table:
SelRDYPol1
0
0
1
1
SelRDYPol0
0
1
0
1
RDY Polarity
RDY is direct input
RDY is inverted input
RDY is direct input
RDY is inverted input
or direct output
or direct output
or inverted output
or inverted output
The bit "RDYisOutput" (bit2 of SIO Ctl3) forces the RDY-terminal to be output, regardless of master- or slave mode, when
set to "1" level.
The "RDYactive" (bit3 of SIO Ctl3) allows the CPU to set RDY-output directly to "1". The RDY output is then a logical OR
function of this bit and the value delivered from the serial logic control. RDY must be set to output by RDYisOutput = Hi.
If port P33 is configured as frequency output by "EnFOut" = "1", its frequency is the same as the serial clock in master
mode and has the same polarity, if "NegEdg"is at "0".
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8.5.3 Pull Down / Up Resistors at Port P5
For each port P5 terminal, a pull down or a pull up resistor can be activated by mask option OP-10 to OP-13.
Activated resistors are only connected if the port terminal is input.
Activation is valid for parallel and serial mode of the port P5.
Each mask option offers 3 choices: A: no resistor
B: pull up resistor C: pull down resistor
The options can be individually defined for each terminal.
CPU Access Format:
Register
SIO Low-Data
Add Hex Add Dec
70
112
SIO Hi-Data
71
113
SIO Ctl1
72
114
SIO Ctl2
73
115
SIO Ctl3
74
116
bit3
MSB Low Nibble
MSB Low Nibble
MSB Hi Nibble
MSB Hi Nibble
SelSIOClk1
SelSIOClk1
RUN
RUN
RDYactive
RDYactive
W
R
W
R
W
R
W
R
W
R
bit2
bit1
bit0
<---------------------------------------------------> LSB Low Nibble
<---------------------------------------------------> LSB Low Nibble
<---------------------------------------------------> LSB Hi Nibble
<---------------------------------------------------> LSB Hi Nibble
SelSIOClk0
SelWL1
SelWL0
SelSIOClk0
SelWL1
SelWL0
NegEdg
EnSIO
SelSynOut
NegEdg
EnSIO
SelSynOut
RDYisOutput
SelRDYPol1
SelRDYPol0
RDYisOutput
SelRDYPol1
SelRDYPol0
8.6 Input / Output Port P6
With the metal option OP-22B, the port P6 is a 4bits input/output port with normal current drive capability outputs.
The port direction is controlled by the "PIO67 Ctl" register at address H4C. The bit "P601-Dir" (bit 0, address H4C) defines
the direction of P60, P61 and the bit "P623-Dir" (bit 1, address H4C) defines the direction of P62, P63. A "1" level of the
direction bit configures the corresponding port to be output, a "0" level defines it as input.
If the port P6 is configured as output, a write access to the P6 data register (address H4A) stores the data into the internal
port data register and the data appear at the corresponding port terminals. The port data register is only written when the
port bit is output.
If a port P6 bit is read when the port is output, the data comes from the port output register. When the port is input, the data
is read from the port terminal (output buffer in high impedance). The data LSB is at bit 0, the MSB at bit 3.
After system reset, the direction is input, the output data register contains "0000".
As input, the port P6 is equipped with 4 debouncers, which can be enabled by signal "P6DebOn" (bit 0, address H46)
commonly for all 4 bits. With debouncers active, the input level must be present glitch free for at least the debouncer time
tDEB = 1.95ms, to be transferred to the debouncer output, which can be read by the CPU.
When "P6DebOn" is at "0" level, the port P6 inputs are directly passed to the debouncer outputs.
The port P6 input (after debouncer) is connected to an edge detector, active at positive edges. The 4 edge detector outputs
are logically combined as OR to create the P6 interrupt signal INT-Stat-4 (bit 1, address H6A).
In this way, any valid positive transition at P6 input can create an interrupt if not masked.
Note: Extra pull down transistors are active at this port during the CPURES signal.
For each port P6 terminal, a pull down or a pull up resistor can be activated by mask option OP-24 to OP-27.
Activated resistors are only connected if the port terminal is input.
Each mask option offers 3 choices: A: no resistor
B: pull up resistor C: pull down resistor
The options can be individually defined for each terminal.
CPU Access Format:
Register
Config3
Add Hex
46
Add Dec
70
Port 6
PIO67 Ctl
4A
4C
75
76
W
R
R
W
R
bit3
x
0
P63
(P72-Dir)
(P72-Dir)
bit2
x
0
P62
(P7-Dir)
(P7-Dir)
bit1
(P7DebOn)
(P7DebOn)
P61
P623-Dir
P623-Dir
bit0
P6DebOn
P6DebOn
P60
P601-Dir
P601-Dir
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8.7 Input / Output Port P7
With the metal option OP-23B, the port P7 is a 2bits input/output port P70, P71 with normal current drive capability outputs.
P72 input/output is high current drive capability for watch motor driver (metal option OP-21A), 5mA led driver (metal option
OP-21B, OP-21C) or only high current drive capability (metal option OP-21D).
As port P3 or P4, P72 can be configured in Synchron Mode. But additionally to the setting of timer 1 in "SynMode", the bit
"Mot3Mode" in "Config1" register (bit 3, address H44) must be set to "0". For more details refer to chapter 8.3 and 8.4
The port direction is controlled by the "PIO67 Ctl" register at address H4C. The bit "P701-Dir" (bit 2, address H4C) defines
the direction of P70 to P71 commonly. A "1" level of the direction bit configures the corresponding port to be output, a "0"
level defines it as input.
The bit "P72-Dir" (bit 3, address H4C) defines the direction of P72.
If P70, P71and P72 are configured as output, a write access to the P7 data register (address H4B) stores the data into the
internal port data register and the data appear at the corresponding port terminals. The port data register is only written
when the port bit is output.
If P70, P71 and P72 bits are read when the port is output, the data comes from the port output register. When the port is
input, the data is read from the port terminal (output buffer in high impedance). The data LSB is at bit 0, the MSB at bit 2.
After system reset, the direction is input, the output data register contains "0000".
As input, P70 and P71 are equipped with 2 debouncers, which can be enabled by signal "P7DebOn" (bit 1, address H46)
commonly for 2 bits. With debouncers active, the input level must be present glitch free for at least the debouncer time tDEB
= 1.95ms, to be transferred to the debouncer output, which can be read by the CPU.
When "P7DebOn" is at "0" level, P70 and P71 inputs are directly passed to the debouncer outputs.
P70, P71 inputs (after debouncer) are connected to an edge detector, active at positive edges. The 2 edge detector outputs
are logically combined as OR to create the P7 interrupt signal INT-Stat-4 (bit 2, address H6A).
In this way, any valid positive transition at P70 or P71 input can create an interrupt if not masked.
Note: Extra pull down transistors are active at this port during the CPURES signal.
For P70, P71 terminal, a pull down or a pull up resistor can be activated by mask option OP-28 and OP-29.
Activated resistors are only connected if the port terminal is input.
Each mask option offers 3 choices: A: no resistor
B: pull up resistor C: pull down resistor
The options can be individually defined for each terminal.
At P72, no pull up or pull down element is available during normal operation.
CPU Access Format:
Register
Config3
Add Hex
46
Add Dec
70
Port 7
PIO67 Ctl
4B
4C
75
76
W
R
R
W
R
bit3
x
0
0
P72-Dir
P72-Dir
bit2
x
0
P72
P701-Dir
P701-Dir
bit1
P7DebOn
P7DebOn
P71
(P623-Dir)
(P623-Dir)
bit0
(P6DebOn)
(P6DebOn)
P70
(P601-Dir)
(P601-Dir)
Note: If the terminal P72 is not connected or not used, it must be an output.
A "1" level of the direction bit "P72-Dir" (bit 3, address H4C) configures as output.
In other case an over consumption will occur.
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EM6635
8.7.1 Back Light function on P70 and P71
A special function of generating ELC and ELP clock can be attributed to P70 and P71 when selected and declared as
outputs. Control bits for this function are in register Backlit.
CPU Access Format:
Register
Backlit
Add Hex
78
Add Dec
120
bit3
Blout
BLout
W
R
bit2
StartBL
startBL
bit1
ELPcksel
ELPcksel
bit0
ELCcksel
ELCcksel
ELC is a signal of 256 Hz or 512 Hz with 25 % duty cycle. Selection is done by bit ELCcksel.
ELP is a signal of 8.192 kHz or 16.384 kHz with 75% duty cycle which is inserted between ELC signal when ELC is low.
Frequency selection is done by ELPcksel.
Function is initiated by writing StartBL control bit to 1 and Blout must be set to 1 to dedicate P70 when declared as output
to ELC output and P71 to ELP output. Start of a sequence is synchronized by 512 or 1024 Hz signal from prescaler and
repeats until StartBL bit is cleared to 0 while Blout is still set to 1. For proper sequence end first StartBL must be cleared to
0 and only when sequence finish – final ELC positive pulse following the end of StartBL, Blout can be cleared to 0 or port
changed to input.
Note: when StartBL is cleared to end the sequence with the next positive ELC pulse, ELPcksel and ELCcksel selection bits
must not be cleared but must keep the same value as when StartBL was set. If not the rest of the sequence will have
default timing 256Hz for ELC and 8192Hz for ELP signal !!
By default this function is not selected and P70, P71 are general I/O pins as described in chapter 8.7.
ELPcksel
0
0
1
1
ELCcksel
0
1
0
1
ELP freq [Hz]
8192
8192
16384
16384
ELC freq [Hz]
256
512
256
512
Table showing ELP and ELC frequency selection
Blout
0
0
1
1
P701-Dir
0
1
0
1
P70
General Input
General Output
General Input
Back light ELC Output
P71
General input
General Output
General Input
Back light ELP Output
Table showing P70, P71 function depending on Blout and P701-Dir control bits
StartBL
ck256Hz
ELC
ELP
25% duty cycle of 512 Hz or 256 Hz
75% duty cycle of 16384 Hz or
8192 Hz
Fig. 10D: Back Light ELC and ELP signals in case where ELC is 256 Hz based.
In above picture it is shown that the sequence is started by setting StartBL to 1, together with ELPcksel and ELCcksel clock
selection. Than it is synchronized to first rising edge of doubled frequency clock coming from the prescaler, that it starts with
ELC 25% duty cycle signal and stops with one ELC positive pulse following the StartBL cleared to 0. Between ELC positive
pulses (when ELC is low) is inserted ELP with 75% duty cycle of selected 16384 or 8192 Hz.
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EM6635
9. Timer 1
The timer 1 can operate in three modes: the Zero Stop, the Synchron Mode and the Auto Reload Mode.
The clock frequency can be selected by "SelT1F2" and "SelT1F1" control bits in "Timer1 Ctl" at address H56:
SelT1F2
SelT1F1
0
0
Timer 1 Clock Frequency
512 Hz
0
1
1024 Hz
1
0
2048 Hz
1
1
4096 Hz
During active counting down, in all modes, the CPU can change the timer clock frequency. The new frequency is
immediately applied, so the remaining timer counts until zero will be generated according to the new frequency selection.
Inaccuracy is added, because the transitory counter cycle is generated with parts from two different clock periods.
Additionally, a parasitic clock transition may be generated depending on the actual prescaler clock signal levels.
The CPU writes divider data in two steps, first the higher 4bits into “Timer1 Hi-Data" (address H57) and then the lower 4bits
into "Timer1 Low-Data" (address H58). This corresponds to an 8bit-timer.
The CPU can also write divider data in one step, only the lower 4 bits into "Timer1 Low-Data" (address H58). This
corresponds to a 4bit-timer.
The timer contains an 8bits or a 4bits down counter, which can be loaded by the CPU via an autoreload register with
“Timer1 Hi-Data" at address H57 (MSB at bit 3) and "Timer1 Low-Data" at address H58 (LSB at bit 0). The timer generates
a “Timer1” interrupt (bit2, address H64) when it arrives at the all-zero-state of its counter. When a zero is loaded as data
into the timer, and the timer is actively counting down, it is stopped, but no interrupt will occur.
9.1 Zero Stop Mode
If "SynMode" and "ARMode" are at "0", the timer1 is in Zero Stop Mode.
As soon as the CPU has written a non-zero value into “Timer1Hi-Data" and "Timer1 Low-Data", the timer1 starts counting
down from this value with the selected clock frequency. When arrived at zero, the interrupt "Timer1" is generated.
The timer remains at the zero state until it is loaded again with data.
The timer period from CPU write access to "Timer1" interrupt is:
Load Value*Timer Clock Period - (0...1) Timer Clock Period
After a system reset, the timer is in Zero Stop Mode and in zero state.
If the timer 1 is reloaded by the CPU in Zero Stop mode, while it is counting, the actual counter state will be overwritten and
a new counting down cycle starts with the new value loaded. No interrupt will be generated.
Hi Low
Hi Low
CPU Write
Timer
Clock
Timer
Counter
Timer
Interrupt
0
3
2
1
0
8
7
6
Fig.11: Timer 1 Timing in Zero Stop Mode
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EM6635
9.2 Synchron Mode
The timer 1 works in this special mode, when the "SynMode", bit3 of "Timer1 Ctl" is set to "1".
When the CPU has loaded non-zero data into the timer, the counter is not starting immediately. It waits to be triggered by
the positive edge of the prescaler 64Hz signal. From this event on, it is counting down to zero and stops there.
When arrived at zero, the interrupt "Timer1" is generated.
During its counting down action, the timer generates a "TimerOn" signal, which is used in port P3, P4 and P72 (metal option
OP21-A) to enable data output (see description of ports P3, P4 and P7).
The timer period from positive edge of 64 Hz signal to timer1 interrupt is:
Load Value*Timer Clock Period - 1/2 Timer Clock Period
Hi Low
CPU Write
CK64
Timer Clock
Timer
Counter
Timer
Interrupt
5
0
4
3
2
1
0
Timer On
Fig.12: Timer 1 Timing in Synchron Mode
9.3 Auto Reload Mode
The timer 1 works in Auto Reload Mode, if the "ARMode", bit 2 of "Timer1 Ctl", address H56 is set to "1". The timer starts
counting down, when a non-zero data is loaded into its 2 reload registers (address H57, "Timer1 Hi-Data" and address H58,
"Timer1 Low-Data"). When the counter has arrived at zero state, a "Timer1" interrupt is generated. The counter is then
automatically reloaded with the data stored in the reload register (previously written there by the CPU), and starts again to
count down.
This sequence is repeated until the Auto Reload Mode is stopped by setting the "ARMode" bit to "0".
If the CPU reloads the timer while counting in Auto Reload mode, the actual sequence will be terminated normally. At the
start of the next cycle, the new value is loaded into the counter and all following cycles are executed according to the new
value loaded.
After setting "ARMode" to "0", the timer counts down to zero, generating an interrupt and stays then at zero. The Auto
Reload Mode is only held by writing "0000" into the "Timer1 HI-Data" and the "Timer1Low-Data" reload registers.
The timer1 period in the Auto Reload Mode is (1+Load Value) * Clock Period, from interrupt to interrupt. The duration from
CPU writes access to 1. Timer1 interrupt is LoadValue*Timer Clock Period - (0...1) Timer Clock Period
If an all-zero data is written into the reload register, no interrupt will be generated and the timer1 remains at this state until a
non zero data is written into the reload register. Then, the described sequence starts again.
The "ARMode" and the "SynMode" can be combined: the two control bits "ARMode" and the "SynMode" (bits 2 and 3 of
address H56) are set to "1". The timer 1 starts then synchronised by the 64Hz signal in Auto Reload Mode and ports P3, P4
and P72 (metal option OP21-A) are outputting data as described in 8.3, 8.4 and 8.7.
CPU Access Format:
Register
Timer1 Ctl
Add Hex
56
Add Dec
86
Timer1 HI-Data
57
87
Timer1 Low-Data
58
88
W
R
W
R
W
R
bit3
SynMode
SynMode
MSB
MSB
bit2
ARMode
ARMode
(hi nibble)
(low nibble)
bit1
SelT1F2
SelT1F2
bit0
SelT1F1
SelT1F1
LSB
LSB
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EM6635
10. Timer 2
The timer 2 can operate in two modes: The Zero Stop Mode as explained in timer1 description and the Auto Reload Mode.
The clock frequency can be selected by "SelT2F2" and "SelT2F1" control bits in "Timer2 Ctl" at address H59:
SelT2F2
0
0
1
1
SelT2F1
0
1
0
1
Timer 2 Clock Frequency
4 Hz
16 Hz
64 Hz
256 Hz
The timer 2 has the same general structure as timer 1, see description there.
10.1 Zero Stop Mode
The operation in this mode is the same as for timer 1, only the CPU access address is H5A for "Timer2 Hi-Data", H5B for
"Timer2 Low-Data" and H59 for "Timer2 Ctl".
10.2 Auto Reload Mode
This mode of timer2 is enabled, if the "ARMode", bit2 of "Timer2 Ctl", address H59 is set to "1".
The timer starts counting down, when a non-zero data is loaded into its 2 reload registers (address H5A, "Timer2 Hi-Data"
and address H5B, "Timer2 Low-Data"). When the counter has arrived at zero state, a "Timer2" interrupt is generated (bit 3,
address H64).
The counter is then automatically reload with the data stored in the reload register (previously written there by the CPU),
and starts again to count down.
This sequence is repeated until the Auto Reload Mode is stopped by setting the "ARMode" bit to "0". The Auto Reload
Mode is only hold by writing "0000" into the "Timer2 Hi-Data" and "Timer2 Low-Data" reload registers.
The timer 2 period in the Auto Reload Mode is the same as defined for timer1 in Auto Reload Mode, see there.
If an all-zero data is written into the 2 reload registers, no interrupt will be generated and the timer 2 remains at this state
until a non-zero data is written into the 2 reload registers. Then, the described sequence starts again.
Ctl
Hi
Low
CPU Write
AR Mode
Timer Clock
Timer
Counter
Timer
Interrupt
0
3
1
2
0
3
2
1
0
3
Fig.13: Timer 2 Timing in Auto Reload Mode
CPU Access Format:
Register
Timer2 Ctl
Add Hex
59
Add Dec
89
Timer2 Hi-Data
5A
90
Timer2 Low-Data
5B
91
W
R
W
R
W
R
bit3
x
0
MSB
MSB
bit2
ARMode
ARMode
(hi nibble)
(low nibble)
bit1
SelT2F2
SelT2F2
bit0
SelT2F1
SelT2F1
LSB
LSB
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EM6635
11. BCD counter/CHRONO
The EM6635 has an 8bits BCD counter or Chrono Block.
It contains a 100Hz generator, clocked from Prescaler, and a cascade of 2 BCD counters, which generate BCD-data for
1/100s and 1/10s digits.
The Chrono Block generates an interrupt BCD in register INT-Stat-4 (bit0, address H6A). The source of the interrupt is the
1/10s BCD counter overflow (transition from state “9” to “0”) or the corresponding transition of 1/100s BCD counter.
The mask bit BCD in register INT-Stat-4 can be reset by the CPU. A corresponding mask bit at high will enable the
corresponding interrupt, a low level disables this interrupt (bit0, address H6B).
The CPU can start the chrono function by setting BCDRun in “BCDCtl” to high level (bit0, address H5C). This enables the
100Hz chrono clock and the BCD counters.
The CPU can stop the chrono counter by resetting this BCDRun to low level. By this, the clock of the counters is stopped,
but the state of the counters is maintained, e.g. to be read later.
The CPU can reset the BCD counters by writing high to BCDRes in “BCD Ctl” (bit1, address H5C), independently of the
actual mode of the BCD counters (counting or stopped).
The BCDRes is automatically reset after it has cleared the counters; a read access gives always a low level.
The CPU can read the state of the BCD counters in register BCD 1/100 while the counters are counting or
when stopped. The 4bits of “BCD 1/100” register represent the 1/100s digit data and the 4 bits of “BCD 1/10”
register represent the 1/10s digit data in BCD format.
The MSB’s of this data are at bit3 of “BCD 1/100” register (address H5D), respectively at bit3 of “ BCD 1/10”
(address H5E).
The CPU can select an event each 100ms by setting this BCDEvent to high level in “BCD Ctl” (bit2, address H5C) or each
second BCDEvent to low level.
The Chrono Block generates a carry flag when the counter changes from 99 to 00. The CPU can read the flag in register
“BCD Ctl” (bit3, address H6B). State “1” indicates an increment of 1s. State “0” indicates no increment. When “1” is written,
the BCDCarry is cleared. When “0” is written, no change occurs.
CPU Access Format:
Register
BCD Ctl
Add Hex
5C
Add Dec
92
BCD 1/100
5D
93
BCD 1/10
5E
94
W
R
R
R
bit3
BCDCarry
BCDCarry
bit2
BCDEvent
BCDEvent
bit1
BCDRes
0
bit0
BCDRun
BCDRun
MSB <----------------- BCD 1/100 ------------------> LSB
MSB <----------------- BCD 1/10 ------------------> LSB
12. Event Counter
The EM6635 has a 3bits event counter, capable to count the "M" pulses, which are generated by input port P1 (see
description of port P1). The counting direction is upwards. When the event counter arrives at "111" (= decimal 7), it stops
counting and remains at this state.
The state of the event counter can be read by the CPU at any time by reading "Event Counter" at address H60, bits 2, 1 and
0; The bit3 is always read as "0".
A write access to this address H60 clears the event counter to "000", independent of the data value written.
After a system reset, the event counter is in state "000".
CPU Access Format:
Register
Event Counter
Add Hex
60
Add Dec
92
bit3
W
R
0
bit2
(Clear
Counter)
MSB
bit1
bit0
LSB
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EM6635
13. Buzzer Output / Frequency Generator
The EM6635 is equipped with a buzzer output, which can drive a piezo buzzer via an external NPN transistor. An envelop
control terminal allows to create a decay shape of the buzzer output signal.
The buzzer output is driven by a frequency generator, which consists of an 8bits programmable divider. The output signal
has always a duty cycle of 50%. The input clock frequency of the programmable divider is the doubled system clock, i.e.
65536 Hz (with 32768Hz crystal). The settling time after the activation of the cell is typically 500us.
13.1 Functional Description
By system reset, "EnFGen" and "EnEnvelop" and the programmable divider data are cleared to zero.
The 8bits programmable divider and the buzzer output are enabled together by "EnFGen" set to "1" in "FGen Ctl" at
address H63, bit 0.
The CPU writes divider data in two steps, first the lower 4bits into "FGen Low-Data" (address H61) and then the higher 4bits
into "FGen Hi-Data" (address H62).
This 8bits data word is stored in an internal synchronisation register and transferred into the programmable divider if a
current output signal period has finished, or directly when no output is generated until then. This is the case, if the frequency
generator is loaded with H00. (This is a possibility to program a pause or "silence" without disabling the generator with
"EnFGen".)
The lower 4bits have to be written first, because the write access to the higher 4bits (to "FGen Hi-Data") enables also the
transfer of the 8bits data from the internal synchronisation register into the programmable divider.
The generated output frequency is CK / (data + 1) with CK = 65536Hz.
The frequency doubler is switched on with EnFGen of FGen Ctl at address H63, bit 0.
The divider range is from 2 to 256. As mentioned above, a H00 data produces no output frequency.
13.2 Envelop Control
An external capacitor CENV must be connected to the pad CENV to implement the envelop function.
The envelop function is activated by setting "EnEnvelop" to "1" (bit 1, address H63).
When set to "1", the capacitor starts to be charged from VSS to VBAT level.
The CENV terminal voltage controls an internal amplitude attenuator at the BZ output in such a way, that the BZ level is
maximum (full swing) when CENV is at VSS level and at minimum (no output signal) when at VBAT level.
The attenuator response is non-linear. Therefore, after setting "EnEnvelop" to "1", a delay time tDDEC without attenuation is
followed by the real decay time tDEC, during which the output amplitude is modulated to decay to zero.
(if CENV=330nF, tDDEC may be 5…30ms, tDEC may be 20…60ms, depending on external circuitry)
The capacitor CENV can be loaded with two different speeds. Bit 2 of FGen Ctl, "SelShort", if set to "1", selects the faster
charge of capacitor CENV.
The impedance of the externally connected circuit at BZ output has an influence on the decay time tDEC. A lower
impedance makes a longer decay time tDEC.
The generation of an output tone with envelop control is completely under SW control, with support of a timer 2 function. A
possible sequence is shown in Fig.14:
FGen:
Low
Hi
Timer2
Timer2
FGen:
Silence EnEnvelop
EnEnvelop
FGen:
Low
Hi
Timer2
CPU Write
Timer 2
Interrupt
EnEnvelop
CENV
tDDEC
tDEC
BZ
EnFgen = 1
Fig.14: Example of BZ Output Tone Generation with Envelop Control
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EM6635
CPU Access Format:
Register
FGen Low-Data
Add Hex
61
Add Dec
97
62
98
63
99
FGen Hi-Data
FGen Ctl
bit3
W
R
W
R
W
R
bit2
bit1
bit0
LSB
LSB
EnEnvelop
EnEnvelop
EnFGen
EnFGen
(low nibble)
MSB
MSB
x
0
(high nibble)
SelShort
SelShort
14. Supply Voltage Level Detector
The EM6635 has a software configurable built-in Supply Voltage Level Detector (SVLD). Three levels can be defined
between VDDmin+100mV and VDDmax-600mV.
The CPU can compare the supply voltage against a pre-selected value by writing the 2 bits VLC0 and VLC1 in the SVLD
control register which also activates the compare measurement. Since the measurement is not immediate the busy flag
remains high during the measurement and is automatically cleared low when the measurement is finished.
The actual measurement starts with the rising 256Hz
edge following the SVLD command.
During the actual measurement (2 ms) the device
will draw an additional 5 µA of IVDD current. After the
end of the measures the result is available by
inspection of the bit VldResult.
If the result is read 0, then the power supply voltage
was greater than the detection level value. If read 1,
the power supply voltage was lower than the
detection level value. During each read while
VldBusy=1 the VldResult is not guaranteed.
SVLD level selection
Evaluation voltage
not active
VL1
VL2
VL3
SVLD Timing Diagram
SVLD < VBAT
VBAT =VDD
SVLD > VBAT
Compare Level
256 Hz
CPU starts
measure
CPU starts
measure
Busy Flag
Measure
VLC1
0
0
1
1
VLC0
0
1
0
1
Result
0
1
Read Result
CPU Access Format:
Register
Add Hex
Add Dec
bit3
bit2
W
SVLD
6C
108
R
VldResult
VldBusy*
VldBusy*; Read value of VldResult is not guaranteed while VldBusy=1.
bit1
VLC1
VLC1
bit0
VLC0
VLC0
15. Interrupt Control
The EM6635 interrupt controller can handle 16 interrupt requests: 10 internal and 6 external.
The controller is organized in four 4bits parts: "INT-Stat1' to "INT-Stat4" and the corresponding mask control "INT-Msk1" to
"INT-Msk4".
The assignment of the individual interrupt requests is shown in the CPU Access Format. ("INT-Stat4" and "INT-Msk4"
contain really only hardware for 3 used interrupt requests, the BCD counter, the P6 interrupt and the P7 interrupt.
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15.1 Functional Description
A positive edge of an interrupt source signal sets the corresponding status bit in the interrupt controller. All status flags are
logically combined as "OR" to generate the CPU main interrupt request.
The status flags are readable to the CPU and can be cleared individually by writing "1" to the corresponding bit of "INTStat". The status flags are automatically reset by the read access.
After a system reset, all flags are at "0".
The CPU main interrupt request can be disabled by DisINT in "HW-Ctl-1" (bit1, address H40 or H41), when this bit is set to
"1".
All interrupt requests can be masked by the "INT-Msk" register.
A "0" level at an interrupt mask bit inhibits the propagation of an interrupt request to the interrupt status register, so that the
corresponding interrupt status bit is not set.
If a mask bit is set to "1" when the interrupt source signal is "1", the corresponding status bit will not be set.
Only a positive edge of an interrupt source can set the interrupt status.
If DisINT (bit 1, address H40 or H41) is reset to "0" (CPU main interrupt enabled) when an interrupt status bit is "1", a CPU
interrupt will be generated.
CPU Access Format:
Register
HW-Ctl-1
INT-Stat1
INT-Msk1
INT-Stat2
INT-Msk2
INT-Stat3
INT-Msk3
INT-Stat4
INT-Msk4
Add Hex
40
(41)
64
Add Dec
64
(65)
100
65
101
102
66
67
103
68
104
69
105
6A
106
6B
107
bit3
bit2
bit1
bit0
W
x
SelINH
DisINT
x
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
Clear
Timer2
Timer2
Timer2
0
x
0
x
Clear
INT_TB4
INT_TB4
INT_TB4
X
0
X
0
Clear
Timer1
Timer1
Timer1
Clear
M
M
M
Clear
INT_TB3
INT_TB3
INT_TB3
Clear
INT-P7
INT-P7
INT-P7
Clear
INT-TB2
INT-TB2
INT-TB2
Clear
P13
P13
P13
Clear
INT-P2
INT-P2
INT-P2
Clear
INT-P6
INT-P6
INT-P6
Clear
INT-TB1
INT-TB1
INT-TB1
Clear
P12
P12
P12
Clear
INT-SIO
INT-SIO
INT-SIO
Clear
BCD
BCD
BCD
Read
Status
INT-Msk
INT Source
D
to CPU
via Data Bus
Q
CLR
Clear
INT Status
from other
INT Status
bits
CPU Interrupt
Input
DisINT
Fig.15: Interrupt Controller Principle
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EM6635
16. Peripheral Memory Map
Function
Add Hex
Add Dec
00…3F
0…63
HW-Ctl-1
40
64
HW-Ctl-1
Bit Access
HW-Ctl-2
41
65
42
66
HW-Ctl-2
Bit Access
Config-1
43
67
44
68
Config-2
45
69
Config-3
46
70
Port P1
47
71
Port P2
48
72
Special Data
49
73
Port P6
( if NO INH-Low)
Port P7
(if NO INH-Hi)
(if INH_Hi, only
P72)
PIO67 Ctl
4A
74
4B
75
4C
76
Port P3
50
80
Port P4
51
81
PIO43 Ctl
52
82
Port P5
53
83
as Serial IO:
PIO5 Ctl
54
84
TB Capture
55
85
Timer1 Ctl
(Mot)
Timer1 Hi-Data
56
86
57
87
Timer1 Low-Data
58
88
Timer2 Ctl
(Buzzer)
Timer2 Hi-Data
59
89
5A
90
Timer2 Low-Data
5B
91
RAM0,1,2,3
Init.
b’3210
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
R
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
R
W
R
W
R
W
R
W
R
W
R
W
Bit 3
Bit 2
Bit 1
Bit 0
Data3
Data3
0
x
0
Set: 1/Clear: 0
SelTBCapHi
SelTBCapHi
SelTBCapHi
Set: 1/Clear: 0
Mot3Mode
Mot3Mode
DisInpRes
DisInpRes
0
x
Data2
Data2
0
x
0
x
0
x
0
x
DisWD
DisWD
P5DebOn
P5DebOn
0
x
Data1
Data1
DisINT
DisINT
DisINT
DisINT
0
x
0
x
EnFOut
EnFOut
P2DebOn
P2DebOn
P7DebOn
P7DebOn
Data0
Data0
0
x
0
Reset WD
0
x
0
Reset CK
SelINT8
SelINT8
P1DebOn
P1DebOn
P6DebOn
P6DebOn
0000
P13
P12
P11
P10
0000
P23
P22
P21
P20
0
x
P63
P63
0
x
P62
P62
0
x
P61
P61
0
x
P60
P60
0
x
P72
P72
P71
P71
P70
P70
P72-Dir
P72-Dir
P33
P33
P43
P43
P43-Dir
P43-Dir
P53
P53
SCK
P53-Dir
P53-Dir
P701-Dir
P701-Dir
P32
P32
P42
P42
P33-Dir
P33-Dir
P52
P52
SOUT
P52-Dir
P52-Dir
P623-Dir
P623-Dir
P31
P31
P41
P41
P4-Dir
P4-Dir
P51
P51
RDY
P51-Dir
P51-Dir
P601-Dir
P601-Dir
P30
P30
P40
P40
P3-Dir
P3-Dir
P50
P50
SIN
P50-Dir
P50-Dir
T1 (T16)
T2 (T32)
T4 (T64)
T8 (T128)
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
SynMode
ARMode
SelT1F2
SelT1F1
SynMode
ARMode
SelT1F2
SelT1F1
MSB <--------------- Timer 1 Data, Hi Nibble -----------------> LSB
MSB <--------------- Timer 1 Data, Hi Nibble -----------------> LSB
MSB <------------- Timer 1 Data, Low Nibble ----------------> LSB
MSB <------------- Timer 1 Data, Low Nibble ----------------> LSB
0
ARMode
SelT2F2
SelT2F1
x
ARMode
SelT2F2
SelT2F1
MSB <--------------- Timer 2 Data, Hi Nibble -----------------> LSB
MSB <--------------- Timer 2 Data, Hi Nibble -----------------> LSB
MSB <------------- Timer 2 Data, Low Nibble ----------------> LSB
MSB <------------- Timer 2 Data, Low Nibble ----------------> LSB
03/03 REV. B
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EM6635
Function
Add Hex
Add Dec
BCD Ctl
5C
92
BCD 1/100
5D
93
BCD 1/10
5E
94
Event Counter
60
96
FGen Low-Data
61
97
FGen Hi-Data
62
98
FGen Ctl
63
99
INT-Stat-1
INT-Msk-1
64
65
100
101
INT-Stat-2
66
102
INT-Msk-2
67
103
INT-Stat-3
68
104
INT-Msk-3
69
105
INT-Stat-4
6A
106
INT-Msk-4
6B
107
SVLD
6C
108
RCOSC
6D
109
Index Low
6E
110
Index Hi
6F
111
SIO Low-Data
70
112
SIO Hi-Data
71
113
SIO Ctl1
72
114
SIO Ctl2
73
115
SIO Ctl3
74
116
RAM Index
77
119
Backlit
78
120
Init.
b’3210
R
W
R
R
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
0000
Bit 3
Bit 2
Bit 1
Bit 0
BCDCarry
BCDCarry
BCDEvent
BCDEvent
0
BCDRes
BCDRun
BCDRun
0000
MSB <------------------------- BCD 1/100 ------------------------> LSB
0000
MSB <-------------------------- BCD 1/10 -------------------------> LSB
0
MSB <------- Ev Counter Data ----------> LSB
<-------------- Write Access: Clear Event Counter ----------> LSB
MSB <-------------- FGen Data, Low Nibble ------------------> LSB
0000
MSB <-------------- FGen Data, Low Nibble ------------------> LSB
MSB <-------------- FGen Data, Hi Nibble -------------------> LSB
0000
MSB <-------------- FGen Data, Hi Nibble --------------------> LSB
0
SelShort
EnEnvelop
EnFGen
0000
x
SelShort
EnEnvelop
EnFGen
Timer2
Timer1
INT_TB2
INT_TB1
0000
Clear
Clear
Clear
Clear
Timer2
Timer1
INT_TB2
INT_TB1
0000
Timer2
Timer1
INT_TB2
INT_TB1
0
M
P13
P12
0000
x
Clear
Clear
Clear
0
M
P13
P12
0000
x
M
P13
P12
INT_TB4
INT_TB3
INT_P2
INT-SIO
0000
Clear
Clear
Clear
Clear
INT_TB4
INT_TB3
INT_P2
INT-SIO
0000
INT_TB4
INT_TB3
INT_P2
INT-SIO
0
INT_P7
INT_P6
BCD
0000
x
Clear
Clear
Clear
0
INT_P7
INT_P6
BCD
0000
x
INT_P7
INT_P6
BCD
RESULT
BUSY
VLC1
VLC0
0000
x
x
VLC1
VLC0
0
ColdStart
En RC
Osc switch
(Note1)
x
x
En RC
Osc switch
IXLow[3]
IXLow[2]
IXLow[1]
IXLow[0]
xxxx
IXLow[3]
IXLow[2]
IXLow[1]
IXLow[0]
0
IXHi[2]
IXHi[1]
IXHi[0]
xxxx
x
IXHi[2]
IXHi[1]
IXHi[0]
MSB of Low Nibble <---------------------------> LSB of Low Nibble
0000
MSB of Low Nibble <---------------------------> LSB of Low Nibble
MSB of Hi Nibble <---------------------------------> LSB of Hi Nibble
0000
MSB of Hi Nibble <---------------------------------> LSB of Hi Nibble
SelSIOClk1
SelSIOClk0
SelWL1
SelWL0
0000
SelSIOClk1
SelSIOClk0
SelWL1
SelWL0
RUN
NegEdg
EnSIO
SelSynOut
0000
RUN
NegEdg
EnSIO
SelSynOut
RDYactive
RDYisOutput
SelRDYPol1 SelRDYPol0
0000
RDYactive
RDYisOutput
SelRDYPol1 SelRDYPol0
0000
0, 1
0, 1
PageSel[1]
PageSel[0]
0, 1
0, 1
PageSel[1]
PageSel[0]
0000
Blout
StartBL
ELPcksel
ELCcksel
Blout
StartBL
ELPcksel
ELCcksel
0000
Add 75, 76, 7E and 7F are used for EM test.
Note 1: the initialisation of the “RCOSC” register is depending on metal option (see chapter 6.2)
03/03 REV. B
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EM6635
17. Mask Options of EM6635
Option
OP-1
OP-2
OP-3
OP-4
OP-5
OP-6
OP-7
OP-8
OP-9
OP-10
OP-11
OP-12
OP-13
OP-14
OP-15
OP-16
OP-17
OP-18
OP-19
OP-20
OP-21
OP-22
OP-23
OP-24
OP-25
OP-26
OP-27
OP-28
OP-29
Function
A: Watchdog timer available
B: no watchdog timer
A: 1s
Cold Start Delay
B: 0.75sCold Start Delay
C: 0.5s
Cold Start Delay
D: 0.25s
Cold Start Delay
E: no
Cold Start Delay
A: POR available
B: no POR
A: For EM only
B: For EM only
A: For EM only
B: For EM only
A: 31us Port P1 and P2 active Pulldown Time
B: 62us Port P1 and P2 active Pulldown Time
A: Port P1 Pulldown is clocked B: no Port P1 Pulldown
A: 1024 Hz Fout Frequency when SIO in Slave Mode
B: 512 Hz Fout Frequency when SIO in Slave Mode
C: 128 Hz Fout Frequency when SIO in Slave Mode
D: 32 Hz Fout Frequency when SIO in Slave Mode
A: Watchdog disabled by P22 AND P23
B: Watchdog independant of P22 AND P23
A: no Pull Down / Up at P50 = SIN
B: Pull Up at P50 = SIN
C: Pull Down at P50 = SIN (obligatory if OP-20 C is selected)
A: no Pull Down / Up at P51 = RDY
B: Pull Up at P51 = RDY
C: Pull Down at P51 = RDY
A: no Pull Down / Up at P52 = SOUT
B: Pull Up at P52 = SOUT
C: Pull Down at P52 = SOUT
A: no Pull Down / Up at P53 = SCK
B: Pull Up at P53 = SCK
C: Pull Down at P53 = SCK
A: Port 2: Pulldown is clocked
B: Port 2: no Pulldown
A: Port P6 & P70, P71: Pulldown is clocked
B: Port P6 & P70, P71: no clocked Pulldown
A: Voltage regulator is active
B: no voltage regulator (VBAT = VRR)
A: Buzzer envelop control is enabled
B: Buzzer envelop control is disabled
A: CPU controlled P33 function (with EnFOut)
B: P33 is always FOut
A: Xtal Oscillator and RC Oscillator
B: External clock and RC Oscillator
A: RC Oscillator active at system reset
B: RC Oscillator not active at system reset
C: Set P50 to high activate RC Oscillator at system reset
A: P72 output is High drive buffer for motor (Timer1)
B: P72 output is 5mA (PMOS, LED connected to VSS)
C: P72 output is 5mA (NMOS, LED connected to VDD)
D: P72 output is High drive I/O
A: For EM only
B: 4 I/O port 6
A: For EM only
B: 2 I/O port P70 and P71
A: no Pull Down / Up at P60 B: Pull Up at P60 C: Pull Down at P60
A: no Pull Down / Up at P61 B: Pull Up at P61 C: Pull Down at P61
A: no Pull Down / Up at P62 B: Pull Up at P62 C: Pull Down at P62
A: no Pull Down / Up at P63 B: Pull Up at P63 C: Pull Down at P63
A: no Pull Down / Up at P70 B: Pull Up at P70 C: Pull Down at P70
A: no Pull Down / Up at P71 B: Pull Up at P71 C: Pull Down at P71
Select option
D: For EM only
D: For EM only
D: For EM only
D: For EM only
D: For EM only
D: For EM only
To select an option put a letter A, B, C, D or E in column Select Option.
03/03 REV. B
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EM6635
18. Temperature and Voltage Behaviors
18.1 IDD Current (Typical)
[nA]
800
[ nA]
1000
IDD Halt M ode; No Regulator; VDD=1.55V
IDD Halt M ode; Regulator; VDD=3.0V
900
700
800
600
700
600
500
500
400
400
300
300
-20
[ nA]
2000
0
20
40
60
[ °C]
-20
80
[nA]
2000
IDD Run M ode; No Regulator ; VDD=1.55V
1800
1800
1600
1600
1400
1400
1200
1200
1000
0
20
40
60
[°C]
80
60
[°C]
80
IDD Run M ode; Regulator; VDD=3.0V
1000
-20
0
20
40
60
[°C]
80
-20
0
20
40
18.2 Pull-down Resistance (Typical)
[ kohm]
370
[ kohms]
200
Pulldown; No Regulator; Temp=25°C
365
195
360
190
355
185
Pulldown; Regulat or ; Temp=25°C
180
350
1.2
1.3
1.4
1.5
1.6
1.7
[ V]
Pulldown; No Regulat or; V DD =1.55V
[ kohm]
600
1.4
1.8
1.8
[ kohms]
300
500
250
400
200
300
150
200
100
100
50
2.2
2.6
3.0
[V]
3.4
Pulldown; Regulat or ; V DD =3.00V
0
0
-20
0
20
40
60
[ °C]
80
-20
0
20
40
60
[ °C]
80
03/03 REV. B
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EM6635
18.3 Output Currents (Typical)
18.3.1 Port P5, P6, P70, P71 & P72 (OP-21B), Reset OUT
IOL Currents[mA];VDD=3V; VDS=0.15/0.3/0.5V; Temp=25°C
IOL Currents[mA];VDD=1.55V; VDS=0.15/0.3/0.5V; Temp=25°C
5.0
0.5
4.0
8.0
0.5
7.0
6.0
3.0
0.3
2.0
0.15
1.0
5.0
0.3
4.0
3.0
0.15
2.0
1.0
0.0
0.0
1.2
1.2
1.3
1.4
1.5
1.6
1.7
[V]
IOH Currents[mA]; Vdd=1.55V;VDS=0.15/0.3/0.5V; Temp=25°C
1.3
1.4
1.5
1.6
1.7[V]
1.8
1.4
1.4
1.8
1.8
2.2
2.6
3.0
3.4
[V]
IOH Currents[mA]; Vdd=3V;VDS=0.15/0.3/0.5V; Temp=25°C
1.8
2.2
2.6
3.0
3.4 [V]
0.0
0.0
-1.0
-1.0
0.15
-2.0
0.3
0.15
-2.0
-3.0
0.3
-4.0
-3.0
0.5
-4.0
-5.0
0.5
-6.0
IOL Currents[mA]; VDD=1.55V; VDS=0.15/0.3/0.5V
IOL Currents[mA]; VDD=3V; VDS=0.15/0.3/0.5V
5.0
8.0
7.0
4.0
0.5
3.0
0.3
2.0
0.15
1.0
0.0
-20
-20
0
20
40
60
[°C]
IOH Currents[mA]; VDD=1.55V; VDS=0.15/0.3/0.5V
0
20
40
60
[°C]
80
80
-3.0
0.3
2.0
1.0
0.0
-20
0.15
0
20
40
60
[°C]
IOH Currents[mA]; VDD=3V; VDS=0.15/0.3/0.5V
0
20
40
60
[°C]
80
80
0.0
0.15
0.3
-2.0
0.5
-20
0.0
-1.0
6.0
5.0
4.0
3.0
0.5
-1.0
0.1
-2.0
-3.0
-4.0
0.3
0.5
-5.0
-4.0
-6.0
03/03 REV. B
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EM6635
18.3.2 Port P3, P4 & P72 (OP-21A)
IOL Currents[mA];VDD=3V; VDS=0.15/0.3/0.5V; Temp=25°C
IOL Currents[mA];VDD=1.55V; VDS=0.15/0.3/0.5V; Temp=25°C
20.0
20.0
0.5
16.0
0.5
16.0
12.0
12.0
0.3
8.0
0.15
4.0
0.3
8.0
0.0
0.15
4.0
0.0
1.2
1.3
1.4
1.5
1.6
1.7
[V]
1.8
1.4
IOH Currents[mA]; Vdd=1.55V;VDS=0.15/0.3/0.5V; Temp=25°C
1.2
1.3
1.4
1.5
1.6
1.7[V]
1.4
1.8
1.8
2.2
2.6
3.0
3.4 [V]
IOH Currents[mA]; Vdd=3V;VDS=0.15/0.3/0.5V; Temp=25°C
1.8
2.2
2.6
3.0
3.4 [V]
0.0
0.0
-2.0
-4.0
-4.0
0.15
-6.0
0.15
-8.0
0.3
-8.0
0.3
-12.0
-10.0
-12.0
-16.0
0.5
-14.0
-16.0
0.5
-20.0
IOL Currents[mA]; VDD=1.55V; VDS=0.15/0.3/0.5V
IOL Currents[mA]; VDD=3V; VDS=0.15/0.3/0.5V
20.0
20.0
16.0
16.0
12.0
0.5
8.0
0.3
8.0
4.0
0.15
4.0
0.0
-20
-20
0
20
40
60
[°C]
IOH Currents[mA]; VDD=1.55V; VDS=0.15/0.3/0.5V
0
20
40
60
[°C]
80
80
-10.0
-12.5
-15.0
0.15
-20
0
20
40
60
IOH Currents[mA]; VDD=3V; VDS=0.15/0.3/0.5V
0
20
40
60
[°C]
[°C]
80
80
0.0
0
0.1
-5.0
-7.5
0.3
0.0
-20
0.0
-2.5
0.5
12.0
0.3
0.5
-5.0
0.1
-10.0
0.3
-15.0
0.5
-20.0
03/03 REV. B
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EM6635
19. Electrical Specifications
19.1 Absolute maximum Ratings
Min.
Max.
Unit
Power supply VDD-VSS
-0.2
+3.6
V
Input Voltage
VSS -0.2
VDD +0.2
V
Storage Temperature
-40
+125
°C
Electrostatic discharge to
-2000
+2000
V
Mil-Std-883C method 3015.7 with ref. to VSS
Maximum soldering conditions
10s x 250°C
Stresses above these maximum ratings may cause permanent damage to the device. Exposure beyond specified electrical
characteristics may affect device reliability or cause malfunction.
19.2 Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be
taken as for any other CMOS component.
Unless otherwise specified, correct operation can only occur when all terminal voltages are kept within the supply voltage
range.
19.3 Standard Operating Conditions
Parameter
MIN
TYP
MAX
Unit
Description
Temperature
-20
25
85
°C
VDD _Range1
1.6
3.0
3.6
V
with
internal voltage regulator
VDD _Range2
1.2
1.5
1.8
V
without internal voltage regulator
IVSS max
300
mA
Maximum current out of VSS Pin
IVDD max
300
mA
Maximum current into VDD Pin
VSS
0
V
Reference terminal
CVRR (Note2)
100
nF
regulated voltage capacitor
fQ
32768
Hz
nominal frequency
RQS
35
kOhm
typical quartz serial resistance
CL
8.2
pF
typical quartz load capacitance
df/f
ppm
quartz frequency tolerance
± 30
Note 2: This capacitor filters switching noise from VDD to keep it away from the internal logic cells.
In noisy systems the capacitor should be chosen bigger than minimum value.
19.4 DC Characteristics - Power Supply
Conditions: VDD =1.55V, T=+25°C, without internal voltage regulator (unless otherwise specified)
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
ACTIVE supply current
(Note3,4)
IVDDA
1.5
2.5
µA
-20°C to +85°C (Note3,4)
3.5
ACTIVE supply current
at 250kHz (Note4)
IVDDA2
29
45
µA
at 250kHz, -20°C to +85°C (Note4)
60
HALT supply current
(Note3)
IVDDH
0.4
0.8
µA
-20°C to +85°C (Note3)
1.0
POR static level
VPOR
0.7
1.01
1.2
V
RAM data retention
VRD1
1.0
V
Note 3: Active and standby current measurements are made with oscillator driven by an external square wave signal of
32.768kHz and an amplitude of VDD voltage.
Note 4: For well defined current measurement, a special test-loop is installed in SW with successive write and read of
two addresses. For this, 5 instructions must be reserved in the ROM code. This will be done at
EM Microelectronic-Marin.
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EM6635
Conditions: VDD =3.00V, T=+25°C, with internal voltage regulator (unless otherwise specified)
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
ACTIVE supply current (Note3,4)
IVDDA
1.6
2.6
µA
-20°C to +85°C (Note3,4)
3.6
ACTIVE supply current at 500kHz (Note4)
IVDDA2
50
75
µA
at 500kHz, -20°C to +85°C (Note4)
100
HALT supply current
(Note3)
IVDDH
0.4
0.8
µA
-20°C to +85°C (Note3)
1.0
POR static level
VPOR
0.75
1.04
1.25
V
RAM data retention
-20°C to +85°C
VRD2
1.2
V
Regulated voltage
Halt mode, no load
VREG
1.2
1.4
1.7
V
Note 3: Active and standby current measurements are made with oscillator driven by an external square wave signal of
32.768kHz and an amplitude of VREG voltage.
Note 4: For well defined current measurement, a special test-loop is installed in SW with successive write and read of
two addresses. For this, 5 instructions must be reserved at the end of the ROM. This will be done at
EM Microelectronic-Marin.
TESTLOOP:
STI
LDR
NXORX
JPZ
JMP 0
00H,
0AH
1BH
FFH
TESTLOOP
;TEST LOOP
To stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop.
This is done at EM Microelectronic-Marin.
1BH: 0101b
32H: 1010b
6EH: 0010b
6FH: 0011b
Free space after last instruction: JMP 00H (0000)
Remark: empty space within the program are filled with NOP (FOFF).
19.5 Oscillator
Conditions: T=+25°C, (unless otherwise specified), 32kHz oscillator
Parameter
Conditions
Symbol
Temperature Stability
+15°C to +35°C
df/f x dT
Voltage Stability (note 5)
VDD = 1.4 to 1.6V
df/f x dU
Input Capacitor
Ref. on VSS
CIN
Output Capacitor
Ref. on VSS
COUT
Transconductance
VDdmin, sinus 50mVpp gm
Oscillator start voltage
TSTART < 10s
VSTART
Oscillator start time
VDD = 1.55V
TSTART
Note5: Applicable only for the versions without the internal voltage regulator
Min.
Typ.
5.8
10.7
2.5
VDDmin
7
12.5
2
Conditions: VDD =1.55V, T=+25°C, (unless otherwise specified), 250kHz RC-Oscillator
Parameter
Conditions
Symbol
Min.
Oscillation frequency
fRC
-30%
Oscillation start voltage
TSTART < 1ms
VRCSTART
1.2
Oscillation start time
Oscillation stop voltage
Conditions: VDD =3.00V, T=+25°C, (unless otherwise specified), 500kHz RC-Oscillator
Parameter
Conditions
Symbol
Min.
Oscillation frequency
fRC
-30%
Oscillation start voltage
TSTART < 1ms
VRCSTART
1.4
Oscillation start time
Oscillation stop voltage
External clock on Qout terminal (metal option OP-19 B)
Conditions: T=+25°C, (unless otherwise specified)
Parameter
Conditions
External frequency
Pulldown active
VIN=VDD=3.00V
Pulldown active
VIN =VDD=1.55V
Symbol
IPD
IPD
Max.
0.3
5
8.2
14.3
15
Min.
2
0.5
Typ.
250
Max.
+30%
1
0.9
Typ.
500
Max.
+30%
1
1.1
Typ.
32.768
Max.
650
8
2
Unit
ppm/°C
ppm /V
pF
pF
µA/V
V
sec
Unit
kHz
V
ms
V
Unit
kHz
V
ms
V
Unit
kHz
µA
µA
03/03 REV. B
Copyright 2002, EM Microelectronic-Marin SA
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EM6635
19.6 Supply Voltage Level Detector
Parameter
SVLD voltage Level1
SVLD voltage Level1
SVLD voltage Level2
SVLD voltage Level3
Temperature coefficient
Conditions
VDD = 1.55V
mask option, -10 to +60°C
VDD = 3.00V
mask option, -10 to +60°C
mask option, -10 to +60°C
mask option, -10 to +60°C
0 to +50°C
Symbol
Min.
Typ.
Max.
Unit
VSVLD1
1.24
1.38
1.52
V
VSVLD1
VSVLD2
VSVLD3
2.55
2.28
1.46
2.80
2.50
1.60
< ± 0.1
3.05
2.72
1.74
V
V
V
mV/°C
19.7 DC Characteristics Input / Output
Conditions: -20°C to +85°C (unless otherwise specified)
VDD =1.55V means; measures without voltage regulator, VDD =3.00V means; measures with voltage regulator
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Input Low Voltage
Port in Input Mode
Port P1, P2, P3, P4, P5
VIL
VSS
0.2VDD
P6 & P70, P71
VIL
VSS
0.2VDD
RESETIN
VIL
VSS
0.1VDD
QIN with Regulator
VIL
VSS
0.1VREG
QIN without Regulator
VIL
VSS
0.1VDD
QOUT (note 6) (OP-19A)
Input High Voltage
Port in Input Mode
Port P1, P2, P3, P4, P5
VIH
0.8VDD
VDD
P6 & P70, P71
VIH
0.8VDD
VDD
RESETIN
VIH
0.9VDD
VDD
QIN with Regulator
VIH
0.9VREG
VREG
QIN without Regulator
VIH
0.9VDD
VDD
QOUT (note 6) (OP-19A)
Input Current
VDD = 1.55V
P1, P2
Pull Down activated, 25°C IPD
0.5
2
P5
if Pull Down, VIN = VDD, 25°C IPD
2
10
25°C IPU
Rpull=330k,metal option (note 7)
if Pull Up, VIN = VSS,
-10
-2
P6 & P7 (OP-22B)
if Pull Down, VIN = VDD, 25°C IPD
2
10
Rpull=330k,metal option (note 7)
if Pull Up, VIN = VSS,
-10
-2
25°C IPU
RESETIN (Rpulldown=20k)
VIN = VDD, 25°C
75
TEST, TCK, TESTRC
VIN = VDD, 25°C
340
Cold Start Pull Down Input Current P1 Reset Out is active,
25°C IPD
0.5
1
to P5
Input Current
VDD = 3.00V
P1, P2
Pull Down activated, 25°C IPD
2
8
P5
if Pull Down, VIN = VDD, 25°C IPD
8
40
25°C IPU
Rpull=160k,metal option (note 7)
if Pull Up, VIN = VSS,
-40
-8
P6 & P7 (OP-22B)
if Pull Down, VIN = VDD, 25°C IPD
8
40
Rpull=160k,metal option (note 7)
if Pull Up, VIN = VSS,
25°C IPU
-40
-8
RESETIN (Rpulldown=20k)
VIN = VDD
150
TEST, TCK, TESTRC
VIN = VDD
340
Cold Start Pull Down Input Current P1 Reset Out is active,
25°C IPD
0.5
1.5
to P5
Output Low Current
VDD = 1.55V
Ports P3, P4, P72(OP-21 A, D)
VOL = 0.08V
IOL
-2.4
-1.0
Ports P3, P4, P72(OP-21 A, D)
VOL = 0.15V
IOL
-4.5
Ports P3, P4, P72(OP-21 A, D)
VOL = 0.3V
IOL
-9
Ports P3, P4, P72(OP-21 A, D)
VOL = 0.5V
IOL
-14
Port P5, P6 & P7(OP-22B), ResetOut
VOL = 0.15V
IOL
-1.3
Port P5, P6 & P7(OP-22B), ResetOut
VOL = 0.3V
IOL
-2.5
Port P5, P6 & P7(OP-22B), ResetOut
VOL = 0.5V
IOL
-3.8
BZ
VOL = 0.15V
IOL
-140
-75
Unit
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
µA
03/03 REV. B
Copyright 2002, EM Microelectronic-Marin SA
35
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EM6635
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Output Low Current
VDD =3.00V
Ports P3, P4, P72(OP-21 A, D)
VOL = 0.08V
IOL
-2.8
-1.0
Ports P3, P4, P72(OP-21 A, D)
VOL = 0.15V
IOL
-5
Ports P3, P4, P72(OP-21 A, D)
VOL = 0.3V
IOL
-10
Ports P3, P4, P72(OP-21 A, D)
VOL = 0.5V
IOL
-17
Port P5, P6 & P7(OP-22B), ResetOut
VOL = 0.15V
IOL
-2
Port P5, P6 & P7(OP-22B), ResetOut
VOL = 0.3V
IOL
-4
Port P5, P6 & P7(OP-22B), ResetOut
VOL = 0.5V
IOL
-6.5
BZ
VOL = 0.15V
IOL
200
-75
Output High Current
VDD = 1.55V
Ports P3, P4, P72(OP-21A, D)
VOH = VDD–0.12V
IOH
1.0
3.3
Ports P3, P4, P72(OP-21A, D)
VOH = VDD–0.15V
IOH
4
Ports P3, P4, P72(OP-21A, D)
VOH = VDD–0.3V
IOH
7.7
Ports P3, P4, P72(OP-21A, D)
VOH = VDD–0.5V
IOH
12
Port P5, P6 & P7(OP-22B) , ResetOut VOH = VDD–0.15V
IOH
0.9
Port P5, P6 & P7(OP-22B) , ResetOut VOH = VDD–0.3V
IOH
1.7
Port P5, P6 & P7(OP-22B) , ResetOut VOH = VDD–0.5V
IOH
2.5
BZ
VOH = VDD–0.15V
IOH
100
200
Output High Current
VDD = 3.00V
Ports P3, P4, P72(OP-21A, D)
VOH = VDD–0.12V
IOH
1.0
4.2
Ports P3, P4, P72(OP-21A, D)
VOH = VDD–0.15V
IOH
5.3
Ports P3, P4, P72(OP-21A, D)
VOH = VDD–0.3V
IOH
10
Ports P3, P4, P72(OP-21A, D)
VOH = VDD–0.5V
IOH
17
Port P5, P6 & P7(OP-22B), ResetOut VOH = VDD–0.15V
IOH
1.45
Port P5, P6 & P7(OP-22B), ResetOut VOH = VDD–0.3V
IOH
2.9
Port P5, P6 & P7(OP-22B), ResetOut VOH = VDD–0.5V
IOH
0.1
4.7
BZ
VOH = VDD–0.15V
IOH
100
250
Output current
VDD = 2.40V
P72 (OP-21 C)
VOL = 0.13V
IOL
-8
-5
P72 (OP-21 B)
VOH = VDD–0.15V
IOH
5
9
Note 6: QOUT (OSC2) is used only with Quartz
Note 7: The resistor value can be programmable by metal mask (20k to 360k by step of 20k). The value must
be checked and agreed by EM Microelectronic-Marin.
Unit
mA
mA
mA
mA
mA
mA
mA
µA
mA
mA
mA
mA
mA
mA
mA
µA
mA
mA
mA
mA
mA
mA
mA
µA
mA
mA
19.8 AC Characteristics at Inputs
Conditions: T= +25°C (unless otherwise specified), fOSC = 32768 Hz
VDD =1.55V means; measures without voltage regulator
VDD=3.00V means; measures with voltage regulator
Parameter
Conditions
Input Pull-down activation
Time at P1, P2
mask option
frequency
Input Pull-down Current
VDD = 1.55V
Pull Down Mean Input Current at P1, P2 tPD = 30.5µs
Pull Down Mean Input Current at P1, P2 tPD = 61µs
NMOS-Holder Low Current at P1, P2
VIN = 0.3V
External contact resistance
(to fight pull down)
Input Pull-down Current
VDD = 3.00V
Pull Down Mean Input Current at P1, P2 tPD = 30.5µs
Pull Down Mean Input Current at P1, P2 tPD = 61µs
NMOS-Holder Low Current at P1, P2
External contact resistance
Duty cycle at FOUT
Frequency SCL
VIN = 0.3V
(to fight pull down)
Slave Mode
Symbol
Min.
tPD
tPD
31
IPD
IPD
IHLO
RCO
Typ.
Max.
Unit
62
µs
Hz
8
16
10
32
64
50
20
nA
nA
µA
kΩ
IPD
32
128
nA
IPD
64
256
nA
IHLO
RCO
DCFO
fSCL
5
70
60
µA
kΩ
%
kHz
512
50
100
03/03 REV. B
Copyright 2002, EM Microelectronic-Marin SA
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EM6635
20. Pad Location Diagram
X=-209
Y=-196
X = 3.00mm
Y = 2.77mm
03/03 REV. B
Copyright 2002, EM Microelectronic-Marin SA
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EM6635
21. Package Information
MLF2, 40 LEAD, 6 x 6 mm BODY
03/03 REV. A/
Copyright 2003, EM Microelectronic-Marin SA
38
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EM6635
22. Ordering Information
Packaged Device:
EM6635 LF A - %%%
Device in DIE Form:
EM6635 WS 11 - %%%
P ackage:
Die form:
LF = 40 pin Micro Lead Fra me
WW = Wafer
WS = Sawn Wafer/Frame
WP = Waffle Pack
Delivery Form :
A = Stick
Thickness:
11 = 11 mils (280um), by default
27 = 27 mils (686um), not backlapped
Cus tomer Version:
customer -specific number
given by EM Microelectronic
(for oth er thickness, contact EM)
Custom er Version:
customer-specific number
given by EM Microelectronic
Please contact EM Microelectronic-Marin S.A. for availability of MLF2 package.
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM
Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice
at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
© EM Microelectronic-Marin SA, 03/03, Rev. B
03/03 REV. A/
Copyright 2003, EM Microelectronic-Marin SA
39
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