FREESCALE DSP56F826E

56F827
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F827
Rev. 12
01/2007
freescale.com
56F827 General Description
•
MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
Hardware DO and REP loops
•
8-channel Programmable Chip Select
•
64K × 16-bit words (128KB) Program Flash
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10-channel, 12-bit ADC
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1K × 16-bit words (2KB) Program RAM
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Synchronous Serial Interface (SSI)
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4K × 16-bit words (8KB) Data Flash
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Serial Port Interface (SPI)
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4K × 16-bit words (8KB) Data RAM
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Serial Communications Interface (SCI)
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Up to 64K × 16-bit words (128KB) external memory
expansion each for Program and Data memory
•
Time-of-Day (TOD) Timer
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128-pin LQFP Package
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JTAG/OnCE™ for debugging
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16-dedicated and 48 shared GPIO
•
General Purpose Quad Timer
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Up to 40 MIPS at 80MHz core frequency
•
DSP and MCU functionality in a unified,
C-efficient architecture
•
EXTBOOT
RESET
DEBUG
IRQB
IRQA
inputs
ADC
Interrupt
Controller
VREFHI
4
Quad Timer A/
or GPIO
Program Controller
and Hardware
Looping Unit
Program and Boot
Memory
64512 x 16 Flash
1024 x 16 SRAM
2
6
SSI 0 or
GPI0
4
SCI 0 &1 or
SPI 0
4
SPI 1 or
GPIO
6
Programmable
Chip Select
16
Dedicated
GPIO
PCS [2:7}
ApplicationSpecific
Memory &
Peripherals
TOD
Timer
4
2
VSSA
2
Analog Reg
Data ALU
Bit
16 x 16 + 36 → 36-Bit MAC Manipulation
Three 16-bit Input Registers
Unit
Two 36-bit Accumulators
16-Bit
56800
Core
PLL
CLKO
Clock
Gen
XTAL
EXTAL
IPBB
CONTROLS
16
COP
RESET
MODULE
CONTROLS
VSS VDDA
VDD
3
Low Voltage Supervisor
Address
Generation
Unit
XDB2
CGDB
XAB1
XAB2
INTERRUPT
CONTROLS
16
Data Memory
4096 x 16 Flash
4096 x 16 SRAM
COP/
Watchdog
5
PAB
PDB
VPP
SCI 2 or
GPIO
5
JTAG/
OnCE
Port
10
VREFP, VREFMID,
VREFIN
3
VREFLO
VDDIO VSSIO
6
IPBus Bridge
(IPBB)
ADDRESS
BUS [8:0]
DATA
BUS [15:0]
External
Bus
Interface
Unit
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
16
A[00:15]
or
GPIOA16[00:16]
16
D[00:15]
or
GPIOG16[00:16]
PS or PCS[0]
DS or PCS[1]
WR
RD
56F827 Block Diagram
56F827 Technical Data, Rev. 12
Freescale Semiconductor
3
Part 1 Overview
1.1 56F827 Features
1.1.1
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1.1.2
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Processing Core
Efficient 16-bit 56800 family processor engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE Debug Programming Interface
Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 64K words of Program Flash
— 1K words of Program RAM
— 4K words of Data RAM
— 4K words of Data Flash
•
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64 K × 16 Data memory
— As much as 64 K × 16 Program memory
1.1.3
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•
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Peripheral Circuits for 56F827
One 10 channel, 12-bit, Analog-to-Digital Converter (ADC)
One General Purpose Quad Timer totaling 4 pins
One Serial Peripheral Interface with configurable four-pin port multiplexed with two Serial
Communications Interfaces totalling 4 pins or 4 GPIO pins
Three Serial Communication Interfaces with 2 pins each (or 6 additional GPIO pins)
Two Serial Peripheral Interface with configurable four-pin port (or 4 additional GPIO pins)
56F827 Technical Data, Rev. 12
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Freescale Semiconductor
56F827 Description
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•
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1.1.4
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One Synchronous Serial Interface with 6 pins (or 6 additional GPIO pins)
One 8-channel Programmable Chip Select
Sixteen dedicated and forty eight multiplexed GPIO pins (64 total)
Computer-Operating Properly (COP) Watchdog timer
Two external interrupt pins
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the core clock
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
One Time of Day (TOD) Timer
Power Information
Dual power supply, 3.3V and 2.5V
Wait and Multiple Stop modes available
1.2 56F827 Description
The 56F827 is a member of the 56800 core-based family of controllers. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F827 is well-suited for many applications.
The 56F827 includes many peripherals that are especially useful for applications such as: noise
suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, and telephony.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable
rapid development of optimized control applications.
The 56F827 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also provides two external
dedicated interrupt lines, and up to 64 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F827 controller includes 64K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 1K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory. The 56800 core is capable of accessing two data
operands from the on-chip Data RAM per instruction cycle.
This controller also provides a full set of standard programmable peripherals that include one 10-input,
12-bit Analog-to-Digital Converters (ADC), one Synchronous Serial Interface (SSI), two Serial Peripheral
Interfaces (SPI), three Serial Communications Interfaces (SCI). (Note: The second SPI is multiplexed with
56F827 Technical Data, Rev. 12
Freescale Semiconductor
5
the second and third SCIs, giving the option to select a second SPI or two additional SCIs.) This controller
also provides one Programmable Chip Select (PCS), and one Quad Timer. The SCI, SSI, SPI, Quad Timer
A, and select address and data lines can be used as General Purpose Input/Outputs (GPIOs) if those
functions are not required.
1.3 Award-Winning Development Environment
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Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 2-1 are required for a complete description and proper design with the
56F827. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56F827 Chip Documentation
Topic
Description
Order Number
56800E
Family Manual
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
56800EFM
DSP56F826/F827
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56F826 and 56F827
DSP56F826-827UM
56F827
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
DSP56F827
56F827
Errata
Details any chip issues that might be present
DSP56F827E
56F827 Technical Data, Rev. 12
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Freescale Semiconductor
Data Sheet Conventions
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F827 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. Table 2-2 describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins
Power (VDD, VDDIO, VDDA or VDDA_ADC)
(3,5,1,1)
Ground (VSS, VSSIO, VSSA, orVSSA_ADC)
(3,5,1,1)
VPP
1
PLL and Clock
3
Address Bus1
16
Data Bus1
16
Bus Control
4
Quad Timer Module Ports1
4
JTAG/On-Chip Emulation (OnCE)
6
Dedicated General Purpose Input/Output
16
Synchronous Serial Interface (SSI) Port1
6
Serial Peripheral Interface (SPI) Port1
4
Serial Communications Interface1 (SCI0, SCI1) Port2
4
Serial Communications Interface2 (SCI2) Port1
2
Analog to Digital Converter (ADC)
15
Programmable Chip Select (PCS)3
6
Interrupt and Program Control
5
1. Alternately, GPIO pins
2. Alternately, SPI pins
3. In addition, 2 Bus Control pins can be programmed as PCS[0-1].
56F827 Technical Data, Rev. 12
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Freescale Semiconductor
Introduction
2.5V Power
VDD
3.3V Analog Power
VDDA
3.3V Analog Power
VDDA_ADC
3.3V Power
VDDIO
Ground
VSS
Analog Ground
VSSA
Analog Ground
VSSA_ADC
Ground
VSSIO
VPP
Other
Supply Port
EXTAL
PLL
and
Clock
XTAL(CLOCKIN)
CLKO
External
Address Bus or
GPIO
A0-A15(GPIOA0–15)
External Data
Bus or GPIO
D0–D15(GPIOG0-15)
PS (PCS0)
DS (PCS1)
External
Bus Control
RD
WR
TA0 (GPIOF0)
TA1 (GPIOF1)
Quad Timer A
or GPIO
TA2 (GPIOF2)
TA3 (GPIOF3)
TCK
TMS
TDI
JTAG/OnCE™
Port
TDO
TRST
DE
3
8
GPIOB0–7
1
8
GPIOD0–7
5
1
SRD (GPIOC0)
4*
1
SRFS (GPIOC1)
1
1
SRCK (GPIOC2)
1
1
STD (GPIOC3)
5
1
STFS (GPIOC4)
1
STCK (GPIOC5)
1
SCLK (GPIOF4)
1
1
MOSI (GPIOF5)
1
1
MISO (GPIOF6)
1
1
SS (GPIOF7)
16
1
TXD0 (SCLK0)
1
RXD0 (MOSI0)
1
TXD1 (MISO0)
1
RXD1 (SS0)
1
1
TXD2 (GPIOC6)
1
1
RXD2 (GPIOC7)
6
PCS2-7
1
10
ANA0–9
1
1
VREFN
1
1
VREFP
1
VREFMID
1
1
VREFLO
1
1
VREFHI
1
1
IRQA
1
1
IRQB
1
RESET
1
EXTBOOT
1
1
16
Dedicated
GPIO
SSI Port
or GPIO
56F827
1
1
1
SPI1 Port
or GPIO
SCI0,SCI1
Port or
SPI0 Port
SCI2 Port
or GPIO
Programmable
Chip Select
ADC
Port
1
1
Interrupt/
Program
Control
*Includes TCS pin, which is reserved for factory use and is tied to VSS
Figure 2-1 56F827 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parenthesis.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
9
2.2 Signals and Package Information
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always
enabled. Exceptions:
1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP
Signal Name
Pin No.
Type
Description
VDD
116
VDD
VDD
81
VDD
VDD
19
VDD
VDDA
62
VDDA
Analog Power—This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low-noise 3.3V supply.
VDDA_ADC
69
VDDA
Analog Power—This pin is a dedicated power pin for the analog portion of the
ADC module and should be connected to a low-noise 3.3V supply.
VDDIO
113
VDDIO
VDDIO
82
VDDIO
Power In/Out—These pins provide power to the I/O structures of the chip, and
are generally connected to a 3.3V supply.
VDDIO
56
VDDIO
VDDIO
29
VDDIO
VDDIO
4
VDDIO
VSS
115
VSS
VSS
80
VSS
VSS
20
VSS
VSSA
61
VSSA
Analog Ground—This pin supplies an analog ground.
VSSA_ADC
63
VSSA
Analog Ground—This pin is a dedicated ground pin for the analog portion of
the ADC module.
VSSIO
114
VSSIO
GND In/Out—These pins provide grounding for the I/O ring on the chip.
VSSIO
83
VSSIO
All should be attached to VSS.
VSSIO
58
VSSIO
VSSIO
30
VSSIO
VSSIO
5
VSSIO
TCS
43
Input/Output
(Schmitt)
Power—These pins provide power to the internal structures of the chip, and
are generally connected to a 2.5V supply.
GND—These pins provide grounding for the internal structures of the chip. All
should be attached to VSS.
TCS—This pin is reserved for factory use. It must be tied to VSS for normal
use. In block diagrams, this pin is considered an additional VSS.
56F827 Technical Data, Rev. 12
10
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
VPP
90
Input
VPP—This pin should be left unconnected as an open circuit for normal
functionality.
EXTAL
59
Input
External Crystal Oscillator Input—This input should be connected to a
4MHz external crystal or ceramic resonator. For more information, please refer
to Section 3.6.
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.6.3.
XTAL
60
(CLOCKIN)
CLKO
Output
Input
57
Output
Crystal Oscillator Output—This output connects the internal crystal oscillator
output to an external crystal or ceramic resonator. If an external clock source
over 4MHz is used, XTAL must be used as the input and EXTAL connected to
VSS. For more information, please refer to Section 3.6.3.
External Clock Input—This input should be used when using an external
clock or ceramic resonator.
Clock Output—This pin outputs a buffered clock signal. By programming the
CLKO Select Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the device master clock
at the output of the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
56F827 Technical Data, Rev. 12
Freescale Semiconductor
11
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
A0
21
Output
(GPIOA0)
Input/Output
A1
(GPIOA1)
22
A2
(GPIOA2)
23
A3
(GPIOA3)
24
A4
(GPIOA4)
25
A5
(GPIOA5)
26
A6
(GPIOA6)
27
A7
(GPIOA7)
28
A8
(GPIOA8)
31
A9
(GPIOA9)
32
A10
(GPIOA10)
33
A11
(GPIOA11)
34
A12
(GPIOA12)
35
A13
(GPIOA13)
36
A14
(GPIOA14)
37
A15
(GPIOA15)
38
Description
Address Bus—A0–A15 specify the address for external Program or Data
memory accesses.
Port A GPIO—These 16 General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
56F827 Technical Data, Rev. 12
12
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
D0
125
Input/Output
(GPIOG0)
Input/Output
D1
(GPIOG1)
126
D2
(GPIOG2)
127
D3
(GPIOG3)
128
D4
(GPIOG4)
1
D5
(GPIOG5)
2
D6
(GPIOG6)
3
D7
(GPIOG7)
6
D8
(GPIOG8)
7
D9
(GPIOG9)
8
D10
(GPIOG10)
9
D11
(GPIOG11)
10
D12
(GPIOG12)
11
D13
(GPIOG13)
12
D14
(GPIOG14)
13
D15
14
Description
Data Bus—D0–D15 specify the data for external Program or Data memory
accesses. D0-D15 are tri-stated when the external bus is inactive.
Port G GPIO—These 16 General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
(GPIOG15)
PS
(PCS0)
18
Output
Program Memory Select—PS is asserted low for external program memory
access. This pin can also be programmed as a programmable chip select.
DS
(PCS1)
17
Output
Data Memory Select—DS is asserted low for external Data memory access.
This pin can also be programmed as a programmable chip select.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
13
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
RD
15
Output
Read Enable—RD is asserted during external memory read cycles. When RD
is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device data bus. When RD is deasserted high, the external
data is latched inside the device. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
WR
16
Output
Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the device puts data on
the bus. When WR is deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS
pins. WR can be connected directly to the WE pin of a Static RAM.
TA0
112
Input/Output
TA0–3—Timer A Channels 0, 1, 2, and 3
Input/Output
Port F GPIO—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
(GPIOF0)
TA1
(GPIOF1)
111
TA2
(GPIOF2)
110
TA3
(GPIOF3)
109
TCK
44
Input
(Schmitt)
Test Clock Input—This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
TMS
46
Input
(Schmitt)
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
After reset, the default state is Quad Timer.
Note:
TDI
48
Input
(Schmitt)
TDO
47
Input/Output
TRST
45
Input
(Schmitt)
Always tie the TMS pin to VDD through a 2.2K resistor.
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Test Reset—As an input, a low signal on this pin provides a reset signal to the
JTAG TAP controller. To ensure complete hardware reset, TRST should be
asserted whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware device reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET,
but do not assert TRST. TRST must always be asserted at power-up.
Note: For normal operation, connect TRST directly to VSS. If the design is to be
used in a debugging environment, TRST may be tied to VSS through a 1K resistor.
DE
41
Output
Debug Event—DE provides a low pulse on recognized debug events.
56F827 Technical Data, Rev. 12
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Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
GPIOB0
124
Input/Output
GPIOB1
123
GPIOB2
122
GPIOB3
121
GPIOB4
120
GPIOB5
119
GPIOB6
118
GPIOB7
117
GPIOD0
98
GPIOD1
97
GPIOD2
96
GPIOD3
95
GPIOD4
94
GPIOD5
93
GPIOD6
92
GPIOD7
91
SRD
55
(GPIOC0)
Description
Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can
be individually programmed as input or output pins.
After reset, the default state is GPIO input.
Input/ Output
Port D GPIO—These eight dedicated GPIO pins can be individually
programmed as an input or output pins.
After reset, the default state is GPIO input.
Input/Output
SSI Receive Data (SRD)—This input pin receives serial data and transfers the
data to the SSI Receive Shift Receiver.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SRFS
54
(GPIOC1)
Input/Output
SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the
receive section of the SSI as frame sync I/O or flag I/O. The STFS can be
used only by the receiver. It is used to synchronize data transfer and can be an
input or an output.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SRCK
53
(GPIOC2)
Input/Output
SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial
bit rate clock for the Receive section of the SSI. The clock signal can be
continuous or gated and can be used by both the transmitter and receiver in
synchronous mode.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
15
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
STD
52
Output
SSI Transmit Data (STD)—This output pin transmits serial data from the SSI
Transmitter Shift Register.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
(GPIOC3)
After reset, the default state is GPIO input.
STFS
51
(GPIOC4)
Input
Input/Output
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by
the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be
used by both the transmitter and receiver in synchronous mode. It is used to
synchronize data transfer and can be an input or output pin.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
STCK
50
(GPIOC5)
Input/ Output
SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial
bit rate clock for the transmit section of the SSI. The clock signal can be
continuous or gated. It can be used by both the transmitter and receiver in
synchronous mode.
Input/Output
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SCLK
102
(GPIOF4)
Input/Output
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SCLK.
MOSI
101
(GPIOF5)
MISO
(GPIOF6)
100
Input/Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device uses
to latch the data.
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if the slave device is not selected.
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is MISO.
56F827 Technical Data, Rev. 12
16
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
SS
99
Input/Output
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
Input/Output
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
(GPIOF7)
Description
After reset, the default state is SS.
TXD0
108
(SCLK0)
Output
Input/Output
Transmit Data (TXD0)—transmit data output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
RXD0
107
(MOSI0)
TXD1
Input
Input/Output
106
(MISO0)
Output
Input/Output
Receive Data (RXD0)—receive data input
SPI Master Out/Slave In—This serial data pin is an input to a master device
and an output from a slave device. The MISO line of a slave device is placed
in the high-impedance state if the slave device is not selected.
Transmit Data (TXD1)—transmit data output
SPI Master In/Slave Out—This serial data pin is an output to a master device
and an input from a slave device. The master device places data on the MOSI
line one half-cycle before the clock edge the slave device uses to latch the
data.
After reset, the default state is SCI input.
RXD1
105
Input
(Schmitt)
Input
(SS0)
Receive Data (RXD1)— receive data input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple
masters. In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
TXD2
104
(GPIOC6)
Output
Input/Output
Transmit Data (TXD2)—transmit data output
Port C GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is GPIO output.
RXD2
103
(GPIOC7)
Input/Output
Receive Data (RXD2)— receive data input
Input/Output
Port C GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is GPIO input.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
17
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
PCS2
84
Input/Output
PCS3
85
Input/Output
Programmable Chip Select - PCS 2-7 is asserted low for external peripheral
chip select.
PCS4
86
Input/Output
PCS5
87
Input/Output
PCS6
88
Input/Output
PCS7
89
Input/Output
ANA0
70
Input
ANA1
71
Input
ANA2
72
Input
ANA3
73
Input
ANA4
74
Input
ANA5
75
Input
ANA6
76
Input
ANA7
77
Input
ANA8
78
Input
ANA9
79
Input
VREFN
66
Input
ADC Reference—This pin is connected to the negative side of the ADC input
range. This pin requires a 0.1μF ceramic capacitor to VSSA and a start-up time
of 25ms, prior to beginning conversions.
VREFP
65
Input
ADC Reference—This pin is connected to the positive side of the ADC input
range. This pin requires a 0.1μF ceramic capacitor to VSSA and a start-up time
of 25ms, prior to beginning conversions.
VREFMID
68
Input
ADC Reference—This pin isconnected to the center of the ADC input range.
This pin requires a 0.1μF ceramic capacitor to VSSA and a start-up time of
25ms, prior to beginning conversions.
VREFLO
64
Input
ADC Reference—These pins are Negative Reference for ADC and are
generally connected to a VSSA.
VREFHI
67
Input
ADC Reference—These pins are Positive Reference for ADC and are
generally connected to a 3.3V Analog (VDDA_ADC) supply.
IRQA
40
Input
(Schmitt)
ANA0–9—Analog inputs to ADC
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor will
exit the Stop state.
56F827 Technical Data, Rev. 12
18
Freescale Semiconductor
Signals and Package Information
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
IRQB
49
Input
(Schmitt)
External Interrupt Request B—The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for wired-OR
operation.
RESET
42
Input
(Schmitt)
Reset—This input is a direct hardware reset on the processor. When RESET
is asserted low, the device is initialized and placed in the Reset state. A
Schmitt trigger input is used for noise immunity. When the RESET pin is
deasserted, the initial chip operating mode is latched from the external boot
pin. The internal reset signal will be deasserted synchronous with the internal
clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be asserted
together. The only exception occurs in a debugging environment when a
hardware device reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.
EXTBOOT
39
Input
(Schmitt)
External Boot—This input is tied to VDD to force device to boot from off-chip
memory. Otherwise, it is tied to VSS.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
19
Part 3 Specifications
3.1 General Characteristics
The 56F827 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F827 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum-rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
56F827 Technical Data, Rev. 12
20
Freescale Semiconductor
General Characteristics
Table 3-1 Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
VDD1
VSS - 0.3
VSS + 3.0
V
Supply voltage, IO
VDDIO2
VDDA2
VSSIO + 4.0
VSSA + 4.0
VSSA_ADC+0.3
V
Supply voltage, Analog
VSSIO - 0.3
VSSA - 0.3
VSSA_ADC-0.3
VSSIO + 5.5
VDDA + 0.3
VSSA_ADC+0.3
V
VIN_ADC
VSSIO - 0.3
VSSA - 0.3
VSSA_ADC-0.3
Voltage difference VDD to VDD_IO, VDDA
ΔVDD
- 0.3
0.3
V
Voltage difference VSS to VSS _IO, VSSA
ΔVSS
- 0.3
0.3
V
I
—
10
mA
TJ
—
150
°C
TSTG
-55
150
°C
Supply voltage, core
Supply voltage, ADC
VDDA_ADC
Digital input voltages
Analog input voltages (XTAL, EXTAL)
Analog input voltages (ANA0-7, VREF)
VIN
VINA
Current drain per pin excluding VDD, VSS, VDDA,
VSSA,VDDIO, VSSIO
Junction temperature
Storage temperature range
1. VDD must not exceed VDDIO
2. VDDIO and VDDA must not differ by more that 0.5V
Table 3-2 Recommended Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Unit
VDD
2.5
2.5
2.75
V
VDDIO,VDDA
3.0
3.3
3.6
V
Voltage difference VDD to VDD_IO, VDDA
ΔVDD
-0.1
-
0.1
V
Voltage difference VSS to VSS _IO, VSSA
ΔVSS
-0.1
-
0.1
V
ADC reference voltage, positive
VREFHI
2.7
—
VDD_ADC
V
ADC reference voltage, negative
VREFLO
VSSA
—
VREFHI
V
TA
–40
—
85
°C
Supply voltage, core
Supply Voltage, IO and analog
Ambient operating temperature
56F827 Technical Data, Rev. 12
Freescale Semiconductor
21
Table 3-3 Thermal Characteristics6
Value
Characteristic
Comments
Symbol
Unit
Notes
128-pin LQFP
Junction to ambient
Natural convection
Junction to ambient (@1m/sec)
RθJA
50.8
°C/W
2
RθJMA
46.5
°C/W
2
Junction to ambient
Natural convection
Four layer board
(2s2p)
RθJMA
(2s2p)
43.9
°C/W
1,2
Junction to ambient (@1m/sec)
Four layer board
(2s2p)
RθJMA
41.7
°C/W
1,2
Junction to case
RθJC
13.9
°C/W
3
Junction to center of case
ΨJT
1.2
°C/W
4
I/O pin power dissipation
P I/O
User Determined
W
Power dissipation
PD
P D = (IDD x VDD + P I/O)
W
PDMAX
(TJ - TA) /RθJA
W
Junction to center of case
7
Notes:
1.
Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2.
Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number
of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the
non-single layer boards is Theta-JMA.
3.
Junction to case thermal resistance, Theta-JC (RθJC), was simulated to be equivalent to the measured values
using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.
4.
Thermal Characterization Parameter, Psi-JT (ΨJT), is the "resistance" from junction to reference point
thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction
temperature in steady state customer environments.
5.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
6.
See Section 5.1 from more details on thermal design considerations.
7.
TJ = Junction Temperature
TA = Ambient Temperature
56F827 Technical Data, Rev. 12
22
Freescale Semiconductor
DC Electrical Characteristics
3.2 DC Electrical Characteristics
Table 3-4 DC Electrical Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input high voltage (XTAL/EXTAL)
VIHC
2.25
—
3.6
V
Input low voltage (XTAL/EXTAL)
VILC
0
—
0.5
V
Input high voltage (Schmitt trigger inputs)1
VIHS
2.2
—
5.5
V
Input low voltage (Schmitt trigger inputs)2
VILS
-0.3
—
0.8
V
Input high voltage (all other digital inputs)
VIH
2.0
—
5.5
V
Input low voltage (all other digital inputs)
VIL
-0.3
—
0.8
V
Input current high (pull-up/pull-down resistors disabled, VIN=VDD)
IIH
-1
—
1
μA
Input current low (pull-up/pull-down resistors disabled, VIN=VSS)
IIL
-1
—
1
μA
Input current high (with pull-up resistor, VIN=VDD)
IIHPU
-0
—
1
μA
Input current low (with pull-up resistor, VIN=VSS)
IILPU
-210
—
-50
μA
Input current high (with pull-down resistor, VIN=VDD)
IIHPD
20
—
180
μA
Input current low (with pull-down resistor, VIN=VSS)
IILPD
-1
—
1
μA
Nominal pull-up or pull-down resistor value
RPU, RPD
30
KΩ
Output tri-state current low
IOZL
-10
—
10
μA
Output tri-state current high
IOZH
-10
—
10
μA
Input current high (analog inputs, VIN=VDDA)2
IIHA
-15
—
15
μA
Input current low (analog inputs, VIN=VSSA)2
IILA
-15
—
15
μA
Output High Voltage (at IOH)
VOH
VDD – 0.7
—
—
V
Output Low Voltage (at IOL)
VOL
—
—
0.4
V
Output source current
IOH
4
—
—
mA
Output sink current
IOL
4
—
—
mA
IOHP
10
—
—
mA
PWM pin output source current3
56F827 Technical Data, Rev. 12
Freescale Semiconductor
23
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
PWM pin output sink current4
IOLP
16
—
—
mA
Input capacitance
CIN
—
8
—
pF
Output capacitance
COUT
—
12
—
pF
VDD supply current
IDDT5
Run 6
—
60
90
mA
Wait7
—
35
50
mA
Stop
—
6
15
mA
Low Voltage Interrupt, VDDIO power supply8
VEIO
2.4
2.7
3.0
V
Low Voltage Interrupt, VDD power supply9
VEIC
2.0
2.2
2.4
V
Power-on Reset10
VPOR
—
1.7
2.0
V
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI, and RXD1.
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
6. Run (operating) IDD measured using 4MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;
measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (fosc = 4MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less
than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured
with PLL enabled.
8. This low-voltage interrupt monitors the VDDIO power supply. If VDDIO drops below VEIO, an interrupt is generated. Functionality of
the device is guaranteed under transient conditions when VDDIO >VEIO (between the minimum specified VDDIO and the point when
the VEIO interrupt is generated).
9. This low-voltage interrupt monitors the VDD power supply. If VDDIO drops below VEIC, an interrupt is generated. Functionality of
the device is guaranteed under transient conditions when VDD >VEIC (between the minimum specified VDD and the point when the
VEIC interrupt is generated).
10. Power–on reset occurs whenever the VDD power supply drops below VPOR. While power is ramping up, this signal remains active
as long as VDD is below VPOR, no matter how long the ramp-up rate is.
56F827 Technical Data, Rev. 12
24
Freescale Semiconductor
Supply Voltage Sequencing and Separation Cautions
100
IDD Digital
IDD Analog
IDD Total
80
IDD (mA)
60
40
20
0
10
20
30
40
50
60
70
80
Freq. (MHz)
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4)
3.3 Supply Voltage Sequencing and Separation Cautions
DC Power Supply Voltage
Figure 3-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.
3.3V
VDDIO, VDDA
2
2.5V
Supplies Stable
VDD
1
0
Time
Notes: 1. VDD rising before VDDIO, VDDA
2. VDDIO, VDDA rising much faster than VDD
Figure 3-2 Supply Voltage Sequencing and Separation Cautions
56F827 Technical Data, Rev. 12
Freescale Semiconductor
25
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD
supply (2.5V) from the voltage generated by the 3.3V VDDIO supply, see Figure 3-3. This keeps VDD from
rising faster than VDDIO.
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically, this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 3-3. The series diodes forward bias when the difference between VDDIO and VDD reaches
approximately 1.4, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
VDDIO > VDD > (VDDIO - 1.4V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.
Supply
VDDIO, VDDA
3.3V
Regulator
VDD
2.5V
Regulator
Figure 3-3 Example Circuit to Control Supply Sequencing
3.4 AC Electrical Characteristics
Timing waveforms in Section 3.4 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 3-4 the levels of VIH and VIL for an input signal are shown.
Pulse Width
Low
VIH
Input Signal
High
90%
50%
10%
Midpoint1
VIL
Fall Time
Rise Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3-4 Input Signal Measurement References
Figure 3-5 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
•
Data Invalid state, when a signal level is in transition between VOL and VOH
56F827 Technical Data, Rev. 12
26
Freescale Semiconductor
Flash Memory Characteristics
Data2 Valid
Data1 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 3-5 Signal States
3.5 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
Mode
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Standby
L
L
L
L
L
L
L
L
Read
H
H
H
H
L
L
L
L
Word Program
H
H
L
L
H
L
L
H
Page Erase
H
L
L
L
L
H
L
H
Mass Erase
H
L
L
L
L
H
H
H
1. X address enable, all rows are disabled when XE = 0
2. Y address enable, YMUX is disabled when YE = 0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE = 0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Table 3-6 IFREN Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Read main memory block
Word program
Program information block
Program main memory block
Page erase
Erase information block
Erase main memory block
Mass erase
Erase both block
Erase main memory block
56F827 Technical Data, Rev. 12
Freescale Semiconductor
27
Table 3-7 Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Typ
Max
Unit
Figure
Program time
Tprog*
20
–
–
us
Figure 3-6
Erase time
Terase*
20
–
–
ms
Figure 3-7
Mass erase time
Tme*
100
–
–
ms
Figure 3-8
Endurance1
ECYC
10,000
20,000
–
cycles
Data Retention1
DRET
10
30
–
years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
up time
Tnvs*
–
5
–
us
Figure 3-6, Figure 3-7,
Figure 3-8
NVSTR hold time
Tnvh*
–
5
–
us
Figure 3-6, Figure 3-7
NVSTR hold time (mass erase)
Tnvh1*
–
100
–
us
Figure 3-8
NVSTR to program set up time
Tpgs*
–
10
–
us
Figure 3-6,
Recovery time
Trcv*
–
1
–
us
Figure 3-6,
Figure 3-7,Figure 3-8
Cumulative program
HV period2
Thv
–
3
–
ms
Figure 3-6,
Program hold time3
Tpgh
–
–
–
Figure 3-6,
Address/data set up time3
Tads
–
–
–
Figure 3-6,
Address/data hold time3
Tadh
–
–
–
Figure 3-6,
1. One cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
56F827 Technical Data, Rev. 12
28
Freescale Semiconductor
Flash Memory Characteristics
IFREN
XADR
XE
Tadh
YADR
YE
DIN
Tads
PROG
Tnvs
Tprog
Tpgh
NVSTR
Tpgs
Tnvh
Thv
Trcv
Figure 3-6 Flash Program Cycle
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
Tnvs
NVSTR
Tnvh
Terase
Trcv
Figure 3-7 Flash Erase Cycle
56F827 Technical Data, Rev. 12
Freescale Semiconductor
29
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
Tnvs
NVSTR
Tnvh1
Tme
Trcv
Figure 3-8 Flash Mass Erase Cycle
3.6 External Clock Operation
The 56F827 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
3.6.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 3-8. A recommended crystal oscillator circuit
is shown in Figure 3-9. Follow the crystal supplier’s recommendations when selecting a crystal, because
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The crystal and associated components should be mounted as close as possible to the EXTAL
and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x
oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-9, no
external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
56F827 Technical Data, Rev. 12
30
Freescale Semiconductor
External Clock Operation
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
CL =
CL1 * CL2
CL1 + CL2
+ Cs =
12 * 12
12 + 12
+ 3 = 6 + 3 = 9pF
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
EXTAL XTAL Recommended External Crystal
Parameters:
Rz
Rz = 1 to 3MΩ
fc = 4MHz (optimized for 4MHz)
fc
Figure 3-9 Connecting to a Crystal Oscillator Circuit
3.6.2
Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in
Figure 3-10. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F82x oscillator circuitry is designed to have no external load capacitors
present. As shown in Figure 3-9, no external load capacitors should be used.
EXTAL XTAL Recommended Ceramic Resonator
Parameters:
Rz
Rz = 1 to 3 MΩ
fc = 4MHz (optimized for 4MHz)
fc
Figure 3-10 Connecting a Ceramic Resonator
Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).
56F827 Technical Data, Rev. 12
Freescale Semiconductor
31
3.6.3
External Clock Source
The recommended method of connecting an external clock is given in Figure 3-11. The external clock
source is connected to XTAL and the EXTAL pin is held VDDA/2.
56F827
XTAL
EXTAL
External
Clock
VDDA/2
Figure 3-11 Connecting an External Clock Signal
Table 3-8 External Clock Operation Timing Requirements
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)1
fosc
0
4
802
MHz
Clock Pulse Width3, 4
tPW
6.25
—
—
ns
1. See Figure 3-11 for details on using the recommended connection of an external clock driver.
2. When using Time-of-Day (TOD), maximum external frequency is 6MHz.
3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
4. Parameters listed are guaranteed by design.
VIH
External
Clock
90%
50%
10%
tPW
tPW
90%
50%
10%
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3-12 External Clock Timing
56F827 Technical Data, Rev. 12
32
Freescale Semiconductor
External Bus Asynchronous Timing
3.6.4
Phase Locked Loop Timing
Table 3-9 PLL Timing
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
External reference crystal frequency for the PLL1
PLL output frequency2
PLL stabilization time 3-40o to +85oC
Symbol
Min
Typ
Max
Unit
fosc
2
4
6
MHz
fout/2
40
—
110
MHz
tplls
—
1
10
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 4MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
3.7 External Bus Asynchronous Timing
Table 3-10 External Bus Asynchronous Timing1, 2
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
Address Valid to WR Asserted
tAWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR
7.5
(T*WS) + 7.5
—
—
ns
ns
WR Asserted to D0–D15 Out Valid
tWRD
—
T + 4.2
ns
Data Out Hold Time from WR Deasserted
tDOH
4.8
—
ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS
2.2
(T*WS) + 6.4
—
—
ns
ns
RD Deasserted to Address Not Valid
tRDA
0
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
—
18.7
(T*WS) + 18.7
ns
ns
56F827 Technical Data, Rev. 12
Freescale Semiconductor
33
Table 3-10 External Bus Asynchronous Timing1, 2 (Continued)
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
Input Data Hold to RD Deasserted
tDRD
0
—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
tRD
19
(T*WS) + 19
—
—
ns
ns
Address Valid to Output Data Valid
Wait states = 0
Wait states > 0
tAD
—
—
1
(T*WS) + 1
ns
ns
-4.4
—
ns
—
—
2.4
(T*WS) + 2.4
ns
ns
Address Valid to RD Asserted
tARDA
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD
WR Deasserted to RD Asserted
tWRRD
6.8
—
ns
RD Deasserted to RD Asserted
tRDRD
0
—
ns
WR Deasserted to WR Asserted
tWRWR
14.1
—
ns
RD Deasserted to WR Asserted
tRDWR
12.8
—
ns
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
56F827 Technical Data, Rev. 12
34
Freescale Semiconductor
External Bus Asynchronous Timing
A0–A15,
PS, DS
(See Note)
tARDD
tRDA
tARDA
RD
tAWR
tWRWR
tWR
tWRRD
tRDWR
WR
tAD
tWRD
tDOS
D0–D15
tRDRD
tRD
tRDD
tDRD
tDOH
Data Out
Data In
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 3-13 External Bus Asynchronous Timing
56F827 Technical Data, Rev. 12
Freescale Semiconductor
35
3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—
21
ns
Figure 3-14
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
—
—
ns
ns
RESET Deassertion to First External Address Output
tRDA
33T
34T
ns
Figure 3-14
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
Figure 3-15
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
15T
—
ns
Figure 3-16
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
16T
—
ns
Figure 3-16
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
13T
—
ns
Figure 3-17
IRQA Width Assertion to Recover from Stop State4
tIW
2T
—
ns
Figure 3-18
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Figure 3-14
Figure 3-18
—
—
275,000T
12T
ns
ns
Figure 3-19
—
—
275,000T
12T
ns
ns
Figure 3-19
tII
—
—
275,000T
12T
ns
ns
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
56F827 Technical Data, Rev. 12
36
Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
RESET
tRA
tRAZ
tRDA
A0–A15,
D0–D15
First Fetch
PS, DS,
RD, WR
First Fetch
Figure 3-14 Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 3-15 External Interrupt Timing (Negative-Edge-Sensitive)
A0–A15,
PS, DS,
RD, WR
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 3-16 External Level-Sensitive Interrupt Timing
56F827 Technical Data, Rev. 12
Freescale Semiconductor
37
IRQA,
IRQB
tIRI
A0–A15,
PS, DS,
RD, WR
First Interrupt Vector
Instruction Fetch
Figure 3-17 Interrupt from Wait State Timing
tIW
IRQA
tIF
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 3-18 Recovery from Stop State Using Asynchronous Interrupt Timing
tIRQ
IRQA
tII
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
Instruction Fetch
Figure 3-19 Recovery from Stop State Using IRQA Interrupt Service
56F827 Technical Data, Rev. 12
38
Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
3.9 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing1
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Cycle time
Master
Slave
tC
Enable lead time
Master
Slave
tELD
Enable lag time
Master
Slave
tELG
Clock (SCLK) high time
Master
Slave
tCH
Clock (SCLK) low time
Master
Slave
tCL
Data set-up time required for inputs
Master
Slave
tDS
Data hold time required for inputs
Master
Slave
tDH
Access time (time to data active from high-impedance state)
Slave
tA
Disable time (hold time to high-impedance state)
Slave
tD
Data Valid for outputs
Master
Slave (after enable edge)
tDV
Data invalid
Master
Slave
tDI
Rise time
Master
Slave
tR
Fall time
Master
Slave
tF
Min
Max
Unit
See Figure
50
25
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
—
25
—
—
ns
ns
—
100
—
—
ns
ns
24
12
—
—
24.1
12
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
20
0
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
0
2
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
4.8
15
ns
3.7
15.2
ns
—
—
4.5
20.4
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
0
0
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
—
—
11.5
10.0
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
—
—
9.7
9.0
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Figure 3-23
Figure 3-23
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Figure 3-23
Figure 3-23
1. Parameters listed are guaranteed by design.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
39
SS
SS is held High on master
(Input)
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
Bits 14–1
LSB in
tDI
MOSI
(Output)
tDV
Master MSB out
Bits 14–1
tDI(ref)
Master LSB out
tR
tF
Figure 3-20 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tR
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tDH
tR
MISO
(Input)
MSB in
tDI
tDV(ref)
MOSI
(Output)
Bits 14–1
Master MSB out
LSB in
tDV
Bits 14– 1
tF
Master LSB out
tR
Figure 3-21 SPI Master Timing (CPHA = 1)
56F827 Technical Data, Rev. 12
40
Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
SS
(Input)
tC
tF
tCL
SCLK (CPOL = 0)
(Input)
tELG
tR
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tA
MISO
(Output)
Slave MSB out
tF
tR
Bits 14–1
tDS
Slave LSB out
tDV
MSB in
tDI
tDI
tDH
MOSI
(Input)
tD
Bits 14–1
LSB in
Figure 3-22 SPI Slave Timing (CPHA = 0)
SS
(Input)
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELD
SCLK (CPOL = 1)
(Input)
tDV
tELG
tCL
tCH
tR
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
tDS
tDH
MOSI
(Input)
tD
tF
tA
MSB in
Bits 14–1
Slave LSB out
tDI
LSB in
Figure 3-23 SPI Slave Timing (CPHA = 1)
56F827 Technical Data, Rev. 12
Freescale Semiconductor
41
3.10 Analog-to-Digital Converter (ADC) Timing
Table 3-13 ADC Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
VADCIN
0
—
VREFHI1
V
Resolution
RES
12
—
12
Bits
Integral Non-Linearity2
INL
—
+/- 1
+/- 3
LSB3
Differential Non-Linearity
DNL
—
+/- 0.4
+/- 1
LSB3
ADC Input voltage
GUARANTEED
Monotonicity
ADC internal clock4
fADIC
0.5
—
2.5
MHz
Conversion range
RAD
VREFLO
—
VREFHI
V
Power-up time
tADPU
—
25
—
ms
Conversion time
tADC
—
6
—
tAIC cycles5
Sample time
tADS
—
1
—
tAIC cycles5
Input capacitance
CADI
—
5
—
pF5
Gain Error (transfer gain)4
EGAIN
0.95
1.00
1.10
—
VOFFSET
-60
+15
+40
mV
Total Harmonic Distortion4
THD
57
66
—
dB
Effective Number of Bits4
ENOB
9.3
10.5
—
bit
Spurious Free Dynamic Range4
SFDR
58
70
—
dB
Signal-to-Noise plus Distortion4
SINAD
56
64
—
dB
IADC
—
10
—
mA
IADCPD
—
1
—
μA
IVREF
—
1
—
mA
IVREFPD
—
1
—
μA
Offset Voltage4
ADC quiescent current
ADC quiescent current (power
down bit set high)
VREF quiescent current
VREF quiescent current (power
down bit set high)
1. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to
VDDA-0.3V.
56F827 Technical Data, Rev. 12
42
Freescale Semiconductor
Synchronous Serial Interface (SSI) Timing
2. Measured in 10-90% range.
3. LSB = Least Significant Bit.
4. Guaranteed by characterization.
5. tAIC = 1/fADIC
ADC analog input
1
1.
2.
3.
4.
3
2
4
Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only
connected to it at sampling time. (1pf)
Figure 3-24 Equivalent Analog Input Circuit
3.11 Synchronous Serial Interface (SSI) Timing
Table 3-14 SSI Master Mode1 Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
Parameter
Symbol
Min
Typ
Max
Units
fs
—
—
102
MHz
STCK period3
tSCKW
100
—
—
ns
STCK high time
tSCKH
504
—
—
ns
STCK low time
tSCKL
504
—
—
ns
—
—
4
—
ns
Delay from STCK high to STFS (bl) high - Master5
tTFSBHM
0.1
—
0.5
ns
Delay from STCK high to STFS (wl) high - Master5
tTFSWHM
0.1
—
0.5
ns
Delay from SRCK high to SRFS (bl) high - Master5
tRFSBHM
0.6
—
1.3
ns
Delay from SRCK high to SRFS (wl) high - Master5
tRFSWHM
0.6
—
1.3
ns
Delay from STCK high to STFS (bl) low - Master5
tTFSBLM
-1.0
—
-0.1
ns
STCK frequency
Output clock rise/fall time
56F827 Technical Data, Rev. 12
Freescale Semiconductor
43
Table 3-14 SSI Master Mode1 Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
Parameter
Symbol
Min
Typ
Max
Units
Delay from STCK high to STFS (wl) low - Master5
tTFSWLM
-1.0
—
-0.1
ns
Delay from SRCK high to SRFS (bl) low - Master5
tRFSBLM
-0.1
—
0
ns
Delay from SRCK high to SRFS (wl) low - Master5
tRFSWLM
-0.1
—
0
ns
STCK high to STXD enable from high impedance - Master
tTXEM
20
—
22
ns
STCK high to STXD valid - Master
tTXVM
24
—
26
ns
STCK high to STXD not valid - Master
tTXNVM
0.1
—
0.2
ns
STCK high to STXD high impedance - Master
tTXHIM
24
—
25.5
ns
SRXD Setup time before SRCK low - Master
tSM
4
—
—
ns
SRXD Hold time after SRCK low - Master
tHM
4
—
—
ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Master
tTSM
4
—
—
—
SRXD Hold time after STCK low - Master
tTHM
4
—
—
—
1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS
in the tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
56F827 Technical Data, Rev. 12
44
Freescale Semiconductor
Synchronous Serial Interface (SSI) Timing
tSCKH
tSCKW
tSCKL
STCK output
tTFSBHM
tTFSBLM
STFS (bl) output
tTFSWHM
tTFSWLM
STFS (wl) output
tTXVM
tTXEM
tTXNVM
tTXHIM
First Bit
STXD
Last Bit
SRCK output
tRFSBHM
tRFBLM
SRFS (bl) output
tRFSWHM
tRFSWLM
SRFS (wl) output
tSM
tHM
tTSM
tTHM
SRXD
Figure 3-25 Master Mode Timing Diagram
Table 3-15 SSI Slave Mode1 Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Parameter
Symbol
Min
Typ
Max
Units
STCK frequency
fs
—
—
102
MHz
STCK period3
tSCKW
100
—
—
ns
STCK high time
tSCKH
504
—
—
ns
STCK low time
tSCKL
504
—
—
ns
Output clock rise/fall time
—
—
4
—
ns
56F827 Technical Data, Rev. 12
Freescale Semiconductor
45
Table 3-15 SSI Slave Mode1 Switching Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Parameter
Symbol
Delay from STCK high to STFS (bl) high - Slave5
tTFSBHS
Min
Typ
Max
Units
0.1
—
46
ns
Delay from STCK high to STFS (wl) high - Slave5
tTFSWHS
0.1
—
46
ns
Delay from SRCK high to SRFS (bl) high - Slave5
tRFSBHS
0.1
—
46
ns
Delay from SRCK high to SRFS (wl) high - Slave5
tRFSWHS
0.1
—
46
ns
Delay from STCK high to STFS (bl) low - Slave5
tTFSBLS
-1
—
—
ns
Delay from STCK high to STFS (wl) low - Slave5
tTFSWLS
-1
—
—
ns
Delay from SRCK high to SRFS (bl) low - Slave5
tRFSBLS
-46
—
—
ns
Delay from SRCK high to SRFS (wl) low - Slave5
tRFSWLS
-46
—
—
ns
STCK high to STXD enable from high impedance - Slave
tTXES
—
—
—
ns
STCK high to STXD valid - Slave
tTXVS
1
—
25
ns
STFS high to STXD enable from high impedance (first bit) - Slave
tFTXES
5.5
—
25
ns
STFS high to STXD valid (first bit) - Slave
tFTXVS
6
—
27
ns
STCK high to STXD not valid - Slave
tTXNVS
11
—
13
ns
STCK high to STXD high impedance - Slave
tTXHIS
11
—
28.5
ns
SRXD Setup time before SRCK low - Slave
tSS
4
—
—
ns
SRXD Hold time after SRCK low - Slave
tHS
4
—
—
ns
Synchronous Operation (in addition to standard external clock parameters)
SRXD Setup time before STCK low - Slave
tTSS
4
—
—
—
SRXD Hold time after STCK low - Slave
tTHS
4
—
—
—
1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have
been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the
tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
56F827 Technical Data, Rev. 12
46
Freescale Semiconductor
Quad Timer Timing
tSCKW
tSCKH
tSCKL
STCK input
tTFSBLS
tTFSBHS
STFS (bl) input
tTFSWHS
tTFSWLS
STFS (wl) input
tFTXES
tFTXVS
tTXNVS
tTXVS
tTXES
tTXHIS
First Bit
STXD
SRCK input
Last Bit
tRFBLS
tRFSBHS
SRFS (bl) input
tRFSWHS
tRFSWLS
SRFS (wl) input
tSS
tTSS
tHS
tTHS
SRXD
Figure 3-26 Slave Mode Clock Timing
3.12 Quad Timer Timing
Table 3-16 Timer Timing1, 2
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
PIN
4T+6
—
ns
Timer input high/low period
PINHL
2T+3
—
ns
Timer output period
POUT
2T
—
ns
POUTHL
1T
—
ns
Timer input period
Timer output high/low period
1.
In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
47
Timer Inputs
PIN
PINHL
PINHL
Timer Outputs
POUT
POUTHL
POUTHL
Figure 3-27 Quad Timer Timing
3.13 Serial Communication Interface (SCI) Timing
Table 3-17 SCI Timing4
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
BR
—
(fMAX*2.5)/(80)
Mbps
RXD2 Pulse Width
RXDPW
0.965/BR
1.04/BR
ns
TXD3 Pulse Width
TXDPW
0.965/BR
1.04/BR
ns
Baud Rate1
1. fMAX is the frequency of operation of the system clock in MHz.
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 3-28 RXD Pulse Width
TXD
SCI receive
data pin
(Input)
TXDPW
Figure 3-29 TXD Pulse Width
56F827 Technical Data, Rev. 12
48
Freescale Semiconductor
JTAG Timing
3.14 JTAG Timing
Table 3-18 JTAG Timing1, 3
Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
fOP
DC
10
MHz
TCK cycle time
tCY
100
—
ns
TCK clock pulse width
tPW
50
—
ns
TMS, TDI data set-up time
tDS
0.4
—
ns
TMS, TDI data hold time
tDH
1.2
—
ns
TCK low to TDO data valid
tDV
—
26.6
ns
TCK low to TDO tri-state
tTS
—
23.5
ns
tTRST
50
—
ns
tDE
4T
—
ns
TCK frequency of
operation2
TRST assertion time
DE assertion time
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
tCY
tPW
tPW
VM
VM
VIH
TCK
(Input)
VM = VIL + (VIH – VIL)/2
VIL
Figure 3-30 Test Clock Input Timing Diagram
56F827 Technical Data, Rev. 12
Freescale Semiconductor
49
TCK
(Input)
tDS
TDI
TMS
(Input)
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 3-31 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 3-32 TRST Timing Diagram
DE
tDE
Figure 3-33 OnCE—Debug Event
56F827 Technical Data, Rev. 12
50
Freescale Semiconductor
Package and Pin-Out Information 56F827
Part 4 Packaging
4.1 Package and Pin-Out Information 56F827
SCLK
MOSI
MISO
SS
GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
VPP
PCS7
PCS6
PCS5
PCS4
PCS3
PCS2
VSSIO
VDDIO
VDD
VSS
ANA9
ANA8
ANA7
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
VDDA_ADC
VREFMID
VREFHI
VREFN
VREEFP
This section contains package and pin-out information for the 128-pin LQFP configuration of the 56F827.
PIN 64
PIN 102
ORIENTATION
MARK
PIN 39
PIN 1
VREFLO
VSSA_ADC
VDDA
VSSA
XTAL
EXTAL
VSSIO
CLKO
VDDIO
SRD
SRFS
SRCK
STD
STFS
STCK
IRQB
TDI
TDO
TMS
TRST
TCK
TCS
RESET
DE
IRQA
EXTBOOT
D4
D5
D6
VDDIO
VSSIO
D7
D8
D9
D10
D11
D12
D13
D14
D15
RD
WR
DS
PS
VDD
VSS
A0
A1
A2
A3
A4
A5
A6
A7
VDDIO
VSSIO
A8
A9
A10
A11
A12
A13
A14
A15
RXD2
TXD2
RXD1
TXD1
RXD0
TXD0
TA3
TA2
TA1
TA0
VDDIO
VSSIO
VSS
VDD
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOB1
GPIOB0
D0
D1
D2
D3
Figure 4-1 Top View, 56F827 128-pin LQFP Package
56F827 Technical Data, Rev. 12
Freescale Semiconductor
51
Table 4-1 56F827 Pin Identification by Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
D4
33
A10
65
VREFP
97
GPIOD1
2
D5
34
A11
66
VREFN
98
GPIOD0
3
D6
35
A12
67
VREFHI
99
SS
4
VDDIO
36
A13
68
VREFMID
100
MISO
5
VSSIO
37
A14
69
VDDA_ADC
101
MOSI
6
D7
38
A15
70
ANA0
102
SCLK
7
D8
39
EXTBOOT
71
ANA1
103
RXD2
8
D9
40
IRQA
72
ANA2
104
TXD2
9
D10
41
DE
73
ANA3
105
RXD1
10
D11
42
RESET
74
ANA4
106
TXD1
11
D12
43
TCS
75
ANA5
107
RXD0
12
D13
44
TCK
76
ANA6
108
TXD0
13
D14
45
TRST
77
ANA7
109
TA3
14
D15
46
TMS
78
ANA8
110
TA2
15
RD
47
TDO
79
ANA9
111
TA1
16
WR
48
TDI
80
VSS
112
TA0
17
DS
49
IRQB
81
VDD
113
VDDIO
18
PS
50
STCK
82
VDDIO
114
VSSIO
19
VDD
51
STFS
83
VSSIO
115
VSS
20
VSS
52
STD
84
PCS2
116
VDD
21
A0
53
SRCK
85
PCS3
117
GPIOB7
22
A1
54
SRFS
86
PCS4
118
GPIOB6
23
A2
55
SRD
87
PCS5
119
GPIOB5
24
A3
56
VDDIO
88
PCS6
120
GPIOB4
25
A4
57
CLKO
89
PCS7
121
GPIOB3
26
A5
58
VSSIO
90
VPP
122
GPIOB2
27
A6
59
EXTAL
91
GPIOD7
123
GPIOB1
56F827 Technical Data, Rev. 12
52
Freescale Semiconductor
Package and Pin-Out Information 56F827
Table 4-1 56F827 Pin Identification by Pin Number (Continued)
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
28
A7
60
XTAL
92
GPIOD6
124
GPIOB0
29
VDDIO
61
VSSA
93
GPIOD5
125
D0
30
VSSIO
62
VDDA
94
GPIOD4
126
D1
31
A8
63
VSSA_ADC
95
GPIOD3
127
D2
32
A9
64
VREFLO
96
GPIOD2
128
D3
56F827 Technical Data, Rev. 12
Freescale Semiconductor
53
102
65
103
64
128
39
38
01
MILLIMETERS
MIN
MAX
--1.60
0.05
0.15
1.35
1.45
0.17
0.27
0.17
0.23
0.09
0.20
0.09
0.16
22.00 BSC
20.00BSC
0.50 BSC
16.00 BSC
14.00 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
--0.08
--0.08
0.20
o
0
7o
o
--0
02
11o
DIM
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM
PLANE H.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER
SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM
PLANE H.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.35.
Case Outline - 1129-01
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
L2
S
R1
R2
0
13o
Figure 4-2 128-pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.
56F827 Technical Data, Rev. 12
54
Freescale Semiconductor
Thermal Design Considerations
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1: TJ = T A + ( P D × RθJA )
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2: RθJA = R θJC + R θCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system-level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system-level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
56F827 Technical Data, Rev. 12
Freescale Semiconductor
55
•
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation:
•
Provide a low-impedance path from the board power supply to each VDD, VDDIO, and VDDA pin on the
controller, and from the board ground to each VSS,VSSIO, and VSSA (GND) pin.
•
The minimum bypass requirement is to place 0.1μF capacitors positioned as close as possible to the package
supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the
VDD/VSS pairs, including VDDA/VSSA and VDDIO/VSSIO. Ceramic and tantalum capacitors tend to provide
better performance tolerances.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD, VDDIO, and
VDDA and VSS, VSSIO, and VSSA (GND) pins are less than 0.5 inch per capacitor lead.
•
56F827 Technical Data, Rev. 12
56
Freescale Semiconductor
Electrical Design Considerations
•
•
•
Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
•
•
When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
•
56F827 Technical Data, Rev. 12
Freescale Semiconductor
57
Part 6 Ordering Information
Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Table 6-1 56F827 Ordering Information
Part
Supply
Voltage
56F827
2.25–2.75V
56F827
2.25–2.75V
Pin
Count
Ambient
Frequency
(MHz)
Order Number
Low Profile Quad Flat Pack (LQFP)
128
80
DSP56F827FG80
Low Profile Quad Flat Pack (LQFP)
128
80
DSP56F827FG80E *
Package Type
*This package is RoHS compliant.
56F827 Technical Data, Rev. 12
58
Freescale Semiconductor
Electrical Design Considerations
56F827 Technical Data, Rev. 12
Freescale Semiconductor
59
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RoHS-compliant and/or Pb-free versions of Freescale products have the
functionality and electrical characteristics of their non-RoHS-compliant
and/or non-Pb-free counterparts. For further information, see
http://www.freescale.com or contact your Freescale sales representative.
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Information in this document is provided solely to enable system and
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56F827
Rev. 12
01/2007