DS07-12628-2E

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12628-2E
8-bit Microcontrollers
CMOS
New 8FX MB95310L/370L Series
MB95F314E/F314L/F316E/F316L/F318E/F318L
MB95F374E/F374L/F376E/F376L/F378E/F378L
■ DESCRIPTION
MB95310L/370L is a series of general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers of this series contain a variety of peripheral resources.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
• Clock
• Selectable main clock source
Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (1/8/10/12.5 MHz ±2%, maximum machine clock frequency: 12.5 MHz)
Main PLL clock (up to 16.25 MHz, maximum machine clock frequency: 16.25 MHz)
• Selectable subclock source
Sub-OSC clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
• Timer
• 8/16-bit composite timer
• 8/16-bit PPG
• 16-bit reload timer
• Event counter
• Time-base timer
• Watch prescaler
• UART-SIO
• Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer
• Full duplex double buffer
(Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.5
MB95310L/370L Series
(Continued)
• I2C
Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter
8-bit or 10-bit resolution can be selected
• LCD controller (LCDC)
• 40 SEG × 4 COM (MB95F314E/F314L/F316E/F316L/F318E/F318L)
• 32 SEG × 4 COM (MB95F374E/F374L/F376E/F376L/F378E/F378L)
• Internal divider resistor
• With blinking function
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port
• MB95F314E/F314L/F316E/F316L/F318E/F318L (maximum no. of I/O ports: 71)
General-purpose I/O ports (N-ch open drain)
:3
General-purpose I/O ports (CMOS I/O)
: 68
• MB95F374E/F374L/F376E/F376L/F378E/F378L (maximum no. of I/O ports: 55)
General-purpose I/O ports (N-ch open drain)
:3
General-purpose I/O ports (CMOS I/O)
: 52
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Low-voltage detection reset circuit
• Built-in low-voltage detector
• Three configurable low-voltage detection levels for generating reset
• Five configurable low-voltage detection levels for generating interrupts
• Clock supervisor counter
Built-in clock supervisor counter function
• Programmable port input voltage level
CMOS input level / hysteresis input level
• Dual operation Flash memory
The program/erase operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
Protects the content of the Flash memory
2
DS07-12628-2E
MB95310L/370L Series
■ PRODUCT LINE-UP
• MB95310L Series
Part number
MB95F314E
MB95F316E
MB95F318E
MB95F314L
MB95F316L
MB95F318L
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
20 Kbyte
36 Kbyte
60 Kbyte
20 Kbyte
36 Kbyte
60 Kbyte
capacity
RAM capacity
496 bytes
1008 bytes
2032 bytes
496 bytes
1008 bytes
2032 bytes
Low-voltage
Yes
No
detection reset
Reset input
Dedicated
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 71
General• CMOS I/O
: 68
purpose I/O
• N-ch open drain: 3
Time-base timer Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz)
Hardware/
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
• Bus error function and arbitration function
2C
I
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
2 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
UART/SIO
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
4
channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
(Continued)
DS07-12628-2E
3
MB95310L/370L Series
(Continued)
Part number
MB95F314E
MB95F316E
MB95F318E
MB95F314L
MB95F316L
MB95F318L
Parameter
2 channels
• Each timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
•
composite timer It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
• COM output: 4 (Max)
• SEG output: 40 (Max)
• LCD drive power supply (bias) pin: 4 (Max)
LCD controller • 40 SEG × 4 COM: 160 pixels can be displayed
(LCDC)
• Duty LCD mode
• Operate in LCD standby mode
• Blinking function
• Internal divider resistor for LCD drive
1 channel
• Two clock modes and two counter operating modes can be selected
16-bit reload
• Square waveform output
timer
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Counter operating mode: reload mode or one-shot mode can be selected
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter
Event counter function can be implemented. When the event counter function is used, the 16-bit reload timer
and the 8/16-bit composite timer ch. 1 are unavailable.
2 channels
8/16-bit PPG
• Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel”
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting
clock source of 1 second and setting counter value to 60)
8 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing. (asynchronous mode)
Eight different time intervals can be selected.
Watch prescaler
(62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
• Number of program/erase cycles: 100000
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
Package
FPT-80P-M37
4
DS07-12628-2E
MB95310L/370L Series
• MB95370L Series
Part number
MB95F374E
MB95F376E
MB95F378E
MB95F374L
MB95F376L
MB95F378L
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
20 Kbyte
36 Kbyte
60 Kbyte
20 Kbyte
36 Kbyte
60 Kbyte
capacity
RAM capacity
496 bytes
1008 bytes
2032 bytes
496 bytes
1008 bytes
2032 bytes
Low-voltage
Yes
No
detection reset
Reset input
Dedicated
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max): 55
General• CMOS I/O: 52
purpose I/O
• N-ch open drain: 3
Time-base timer Interval time: 0.256 ms - 8.3 s (external clock frequency = 4 MHz)
Hardware/
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
1 channel
• Master/Slave sending and receiving
• Bus error function and arbitration function
2C
I
• Detecting transmitting direction function
• Start condition repeated generation and detection functions
• Built-in wake-up function
2 channels
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
UART/SIO
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
4 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
2 channels
• Each timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
•
composite timer It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
(Continued)
DS07-12628-2E
5
MB95310L/370L Series
(Continued)
Part number
MB95F374E
MB95F376E
MB95F378E
MB95F374L
MB95F376L
MB95F378L
Parameter
• COM output: 4 (Max)
• SEG output: 32 (Max)
• LCD drive power supply (bias) pin: 3 (Max)
LCD controller • 32 SEG × 4 COM: 128 pixels can be displayed
(LCDC)
• Duty LCD mode
• Operate in LCD standby mode
• Blinking function
• Internal divider resistor for LCD drive
1 channel
• Two clock modes and two counter operating modes can be selected
16-bit reload
• Square waveform output
timer
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Counter operating mode: reload mode or one-shot mode can be selected
By configuring the 16-bit reload timer and the 8/16-bit composite timer ch. 1, event counter
Event counter function can be implemented. When the event counter function is used, the 16-bit reload timer
and the 8/16-bit composite timer ch. 1 are unavailable.
2 channels
8/16-bit PPG
• Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1 channel“
• Counter operating clock: Eight selectable clock sources
• Count clock: Four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s)
Watch counter • Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting
clock source of 1 second and setting counter value to 60)
8 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing. (asynchronous mode)
Eight different time intervals can be selected.
Watch prescaler
(62.5 ms, 125 ms, 250 ms, 500 ms, 1 s, 2 s, 4 s, 8 s)
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
• Number of program/erase cycles: 100000
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
FPT-64P-M38
Package
FPT-64P-M39
6
DS07-12628-2E
MB95310L/370L Series
■ OSCILLATION STABILIZATION WAIT TIME
The main CR clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum
value.
Oscillation stabilization wait time
Remarks
(210 − 2) / FCRH
Approx. 128 µs (when the main CR clock is 8 MHz)
The main PLL clock oscillation stabilization wait time is fixed to the maximum value. Below is the maximum
value.
Oscillation stabilization wait time
Remarks
(2 − 2) / FCH
Approx. 14.1 ms (when the main PLL clock is 4 MHz)
14
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F314E
MB95F316E
MB95F318E
MB95F314L
MB95F316L
MB95F318L
MB95F374L
MB95F376L
MB95F378L
Package
FPT-80P-M37
FPT-64P-M38
FPT-64P-M39
O
X
X
Part number
MB95F374E
MB95F376E
MB95F378E
Package
FPT-80P-M37
FPT-64P-M38
FPT-64P-M39
X
O
O
O: Available
X : Unavailable
DS07-12628-2E
7
MB95310L/370L Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. For
details of the connection method, refer to “CHAPTER 31 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in the hardware manual of the MB95310L/370L Series.
8
DS07-12628-2E
MB95310L/370L Series
PE1/SEG25
PE2/SEG26
PE4/SEG28
PE3/SEG27
PE6/SEG30
PE5/SEG29
PE7/SEG31
P42/SEG33/TO11
P43/SEG32
P40/SEG35/EC1
P41/SEG34/TO10
P07/INT07/SEG36
P05/INT05/SEG38
P06/INT06/SEG37
P03/INT03/AN03
P04/INT04/SEG39
P02/INT02/AN02
P00/INT00/AN00
P01/INT01/AN01
AVss
■ PIN ASSIGNMENT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVcc
1
60
PE0/SEG24
PPG10/P16
2
59
P67/SEG23
PPG11/P15
3
58
P66/SEG22
UCK0/P14
4
57
P65/SEG21
ADTG/P13
5
56
P64/SEG20
DBG/P12
6
55
P63/SEG19
UO0/P11
7
54
P62/SEG18
UI0/P10
8
53
P61/SEG17
TO0/P53
9
52
P60/SEG16
TI0/P52
10
51
PC7/SEG15
EC0/P51
11
50
PC6/SEG14
TO01/P50
12
49
PC5/SEG13
SDA0/P24
13
48
PC4/SEG12
SCL0/P23
14
47
PC3/SEG11
TO00/P22
15
46
PC2/SEG10
PPG01/P21
16
45
PC1/SEG09
PPG00/P20
17
44
PC0/SEG08
X0
18
43
PB7/SEG07
X1
19
42
PB6/SEG06
Vss
20
41
PB5/SEG05
(TOP VIEW)
MB95310L Series
(FPT-80P-M37)
SEG04/PB4
SEG03/PB3
SEG02/PB2
SEG01/PB1
COM3/PA3
SEG00/PB0
COM2/PA2
COM0/PA0
COM1/PA1
UI1/P95
UO1/P94
V0/P93
V1/P92
V2/P91
RST
V3/P90
X0A
X1A
UCK1/PG0
Vcc
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(Continued)
DS07-12628-2E
9
MB95310L/370L Series
PE1/SEG21
PE3/SEG23
PE2/SEG22
PE4/SEG24
PE6/SEG26/UI1
PE5/SEG25/TO0
P07/INT07/SEG28/UCK1
PE7/SEG27/UO1
P06/INT06/SEG29/TO11
P04/INT04/SEG31/EC1
P05/INT05/SEG30/TO10
P02/INT02/AN02
P03/INT03/AN03
P01/INT01/AN01
AVss
P00/INT00/AN00
(Continued)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc
1
48
PE0/SEG20
PPG10/P16
2
47
P67/SEG19
PPG11/P15
3
46
P66/SEG18
UCK0/EC0/TI0/P14
4
45
P65/SEG17
ADTG/TO01/P13
5
44
P64/SEG16
DBG/P12
6
43
P63/SEG15
UO0/P11
7
42
P62/SEG14
UI0/P10
8
41
P61/SEG13
SDA0/P24
9
SCL0/P23
10
(TOP VIEW)
MB95370L Series
(FPT-64P-M38)
(FPT-64P-M39)
40
P60/SEG12
39
PC3/SEG11
TO00/P22
11
38
PC2/SEG10
PPG01/P21
12
37
PC1/SEG09
PPG00/P20
13
36
PC0/SEG08
X0
14
35
PB7/SEG07
X1
15
34
PB6/SEG06
Vss
16
33
PB5/SEG05
SEG04/PB4
SEG03/PB3
SEG02/PB2
SEG01/PB1
COM3/PA3
SEG00/PB0
COM2/PA2
COM1/PA1
COM0/PA0
V1/P92
V2/P91
X0A
RST
X1A
Vcc
10
V3/P90
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS07-12628-2E
MB95310L/370L Series
■ PIN DESCRIPTION (MB95310L Series)
Pin no.
Pin name
I/O circuit type*
1
AVCC
—
2
3
4
5
6
7
8
9
P16
PPG10
P15
PPG11
P14
UCK0
P13
ADTG
P12
DBG
P11
UO0
P10
UI0
P53
TO0
H
H
H
H
C
H
G
H
P52
10
11
12
13
14
15
16
17
TI0
P51
EC0
P50
TO01
P24
SDA0
P23
SCL0
P22
TO00
P21
PPG01
P20
PPG00
Function
A/D converter power supply pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
UART/SIO ch. 0 clock I/O pin
General-purpose I/O port
A/D trigger input (ADTG) pin
General-purpose I/O port
DBG input pin
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
16-bit reload timer ch. 0 output pin
General-purpose I/O port
H
H
H
I
I
H
H
H
16-bit reload timer ch. 0 input pin
The pin can also be used as the event counter input pin when the
event counter function is used.
General-purpose I/O port
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
I2C data I/O pin
General-purpose I/O port
I2C clock I/O pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
18
X0
A
Main clock oscillation pin
19
X1
A
Main clock oscillation pin
(Continued)
DS07-12628-2E
11
MB95310L/370L Series
Pin no.
Pin name
I/O circuit type*
20
Vss
—
Power supply pin (GND)
21
VCC
—
Power supply pin
22
PG0
UCK1
H
Function
General-purpose I/O port
UART/SIO ch. 1 clock I/O pin
23
X1A
A
Subclock oscillation pin (32 kHz)
24
X0A
A
Subclock oscillation pin (32 kHz)
25
RST
B
Reset pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P90
V3
P91
V2
P92
V1
P93
V0
P94
UO1
P95
UI1
PA0
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PB0
SEG00
PB1
SEG01
PB2
SEG02
PB3
SEG03
PB4
SEG04
R
R
R
R
H
G
M
M
M
M
M
M
M
M
M
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
(Continued)
12
DS07-12628-2E
MB95310L/370L Series
Pin no.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Pin name
PB5
SEG05
PB6
SEG06
PB7
SEG07
PC0
SEG08
PC1
SEG09
PC2
SEG10
PC3
SEG11
PC4
SEG12
PC5
SEG13
PC6
SEG14
PC7
SEG15
P60
SEG16
P61
SEG17
P62
SEG18
P63
SEG19
P64
SEG20
P65
SEG21
P66
SEG22
I/O circuit type*
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Function
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
(Continued)
DS07-12628-2E
13
MB95310L/370L Series
Pin no.
59
60
61
62
63
64
65
66
67
68
Pin name
P67
SEG23
PE0
SEG24
PE1
SEG25
PE2
SEG26
PE3
SEG27
PE4
SEG28
PE5
SEG29
PE6
SEG30
PE7
SEG31
P43
SEG32
I/O circuit type*
M
M
M
M
M
M
M
N
M
M
P42
69
SEG33
M
M
72
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
LCDC SEG output pin
LCDC SEG output pin
General-purpose I/O port
M
LCDC SEG output pin
EC1
8/16-bit composite timer ch. 1 clock input pin
P07
General-purpose I/O port
INT07
Q
SEG36
INT06
SEG37
External interrupt input pin
LCDC SEG output pin
P06
73
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
P40
SEG35
General-purpose I/O port
General-purpose I/O port
TO10
71
LCDC SEG output pin
8/16-bit composite timer ch. 1 output pin
P41
SEG34
General-purpose I/O port
General-purpose I/O port
TO11
70
Function
General-purpose I/O port
Q
External interrupt input pin
LCDC SEG output pin
(Continued)
14
DS07-12628-2E
MB95310L/370L Series
(Continued)
Pin no.
Pin name
I/O circuit type*
P05
74
INT05
General-purpose I/O port
Q
SEG38
INT04
General-purpose I/O port
Q
SEG39
INT03
General-purpose I/O port
J
AN03
INT02
General-purpose I/O port
J
AN02
INT01
General-purpose I/O port
J
AN01
INT00
General-purpose I/O port
J
AN00
80
AVss
External interrupt input pin
A/D analog input pin
P00
79
External interrupt input pin
A/D analog input pin
P01
78
External interrupt input pin
A/D analog input pin
P02
77
External interrupt input pin
LCDC SEG output pin
P03
76
External interrupt input pin
LCDC SEG output pin
P04
75
Function
External interrupt input pin
A/D analog input pin
—
A/D converter power supply pin (GND)
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS07-12628-2E
15
MB95310L/370L Series
■ PIN DESCRIPTION (MB95370L Series)
s
Pin no.
Pin name
I/O circuit type*
1
AVCC
—
2
3
P16
PPG10
P15
PPG11
H
H
P14
5
EC0
7
8
9
10
11
12
13
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
General-purpose I/O port
8/16-bit PPG ch. 1 output pin
UART/SIO ch. 0 clock I/O pin
H
8/16-bit composite timer ch. 0 clock input pin
The pin can also be used as the event counter input pin when the
event counter function is used.
TI0
16-bit reload timer ch. 0 input pin
P13
General-purpose I/O port
ADTG
H
TO01
6
A/D converter power supply pin
General-purpose I/O port
UCK0
4
Function
P12
DBG
P11
UO0
P10
UI0
P24
SDA0
P23
SCL0
P22
TO00
P21
PPG01
P20
PPG00
A/D trigger input (ADTG) pin
8/16-bit composite timer ch. 0 output pin
C
H
G
I
I
H
H
H
General-purpose I/O port
DBG input pin
General-purpose I/O port
UART/SIO ch. 0 data output pin
General-purpose I/O port
UART/SIO ch. 0 data input pin
General-purpose I/O port
I2C data I/O pin
General-purpose I/O port
I2C clock I/O pin
General-purpose I/O port
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
8/16-bit PPG ch. 0 output pin
14
X0
A
Main clock oscillation pin
15
X1
A
Main clock oscillation pin
16
Vss
—
Power supply pin (GND)
17
VCC
—
Power supply pin
18
P90
V3
R
General-purpose I/O port
LCDC drive power supply pin
(Continued)
16
DS07-12628-2E
MB95310L/370L Series
Pin no.
Pin name
19
X1A
20
X0A
21
RST
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
P91
V2
P92
V1
PA0
COM0
PA1
COM1
PA2
COM2
PA3
COM3
PB0
SEG00
PB1
SEG01
PB2
SEG02
PB3
SEG03
PB4
SEG04
PB5
SEG05
PB6
SEG06
PB7
SEG07
PC0
SEG08
PC1
SEG09
PC2
SEG10
I/O circuit type*
A
B
R
R
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Function
Subclock oscillation pin (32 kHz)
Subclock oscillation pin (32 kHz)
Reset pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC drive power supply pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC COM output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
(Continued)
DS07-12628-2E
17
MB95310L/370L Series
Pin no.
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Pin name
PC3
SEG11
P60
SEG12
P61
SEG13
P62
SEG14
P63
SEG15
P64
SEG16
P65
SEG17
P66
SEG18
P67
SEG19
PE0
SEG20
PE1
SEG21
PE2
SEG22
PE3
SEG23
PE4
SEG24
I/O circuit type*
M
M
M
M
M
M
M
M
M
M
M
M
M
M
PE5
53
54
55
SEG25
Function
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
LCDC SEG output pin
General-purpose I/O port
M
LCDC SEG output pin
TO0
16-bit reload timer ch. 0 output pin
PE6
General-purpose I/O port
SEG26
N
LCDC SEG output pin
UI1
UART/SIO ch. 1 data input pin
PE7
General-purpose I/O port
SEG27
UO1
M
LCDC SEG output pin
UART/SIO ch. 1 data output pin
(Continued)
18
DS07-12628-2E
MB95310L/370L Series
(Continued)
Pin no.
Pin name
I/O circuit type*
P07
56
INT07
SEG28
General-purpose I/O port
Q
UCK1
INT06
SEG29
Q
SEG30
Q
60
SEG31
Q
P03
General-purpose I/O port
INT03
J
INT02
INT01
General-purpose I/O port
J
General-purpose I/O port
J
External interrupt input pin
A/D analog input pin
P00
General-purpose I/O port
J
AN00
AVss
External interrupt input pin
A/D analog input pin
AN01
INT00
External interrupt input pin
A/D analog input pin
P01
64
LCDC SEG output pin
8/16-bit composite timer ch. 1 clock input pin
AN02
63
External interrupt input pin
EC1
P02
62
LCDC SEG output pin
General-purpose I/O port
AN03
61
External interrupt input pin
8/16-bit composite timer ch. 1 output pin
P04
INT04
LCDC SEG output pin
General-purpose I/O port
TO10
59
External interrupt input pin
8/16-bit composite timer ch. 1 output pin
P05
INT05
LCDC SEG output pin
General-purpose I/O port
TO11
58
External interrupt input pin
UART/SIO ch. 1 clock I/O pin
P06
57
Function
External interrupt input pin
A/D analog input pin
—
A/D converter power supply pin (GND)
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS07-12628-2E
19
MB95310L/370L Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Clock input
X1 (X1A)
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
N-ch
X0 (X0A)
• Low-speed side
Feedback resistance:
approx. 24 MΩ
Dumping resistance:
approx. 144 kΩ
Standby control
B
Reset input
Reset input
C
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
G
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
CMOS input
Pull-up control available
Digital output
N-ch
Standby control
Hysteresis input
CMOS input
H
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
(Continued)
20
DS07-12628-2E
MB95310L/370L Series
Type
Circuit
I
Remarks
Standby control
CMOS input
• N-ch open drain output
• CMOS input
• Hysteresis input
Hysteresis input
Digital output
N-ch
J
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
Analog input
Pull-up control available
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
M
P-ch
Digital output
Digital output
• CMOS output
• LCD output
• Hysteresis input
N-ch
LCD output
LCD control
Standby control
Hysteresis input
N
P-ch
Digital output
Digital output
N-ch
•
•
•
•
CMOS output
LCD output
Hysteresis input
CMOS input
LCD output
LCD control
Standby control
Hysteresis input
CMOS input
(Continued)
DS07-12628-2E
21
MB95310L/370L Series
(Continued)
Type
Q
Circuit
Remarks
P-ch
Digital output
Digital output
• CMOS output
• LCD output
• Hysteresis input
N-ch
LCD output
LCD control
Standby control
External interrupt
control
Hysteresis input
R
P-ch
Digital output
Digital output
• CMOS output
• LCD power supply
• Hysteresis input
N-ch
LCD internal divider
resistor I/O
LCD control
Standby control
Hysteresis input
22
DS07-12628-2E
MB95310L/370L Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in “1. Absolute Maximum Ratings” of “■ ELECTRICAL CHARACTERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused input pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Notes on handling the external clock pins while using the CR clock
Connect the X0 pin and the X0A pin to the VSS pin and leave the X1 pin and the X1A pin unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance
between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance
between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
DS07-12628-2E
23
MB95310L/370L Series
• DBG/RST pins connection diagram
*
DBG
RST
*: Since the DBG input pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG.
24
DS07-12628-2E
MB95310L/370L Series
■ RECOMMENDED LAYOUT
• GND wire should be placed around X0, X1, X0A and X1A
The recommended layout method illustrated in following diagram aims to avoid noise coupled between the
oscillator pins and GPIO, which may cause the main oscillator or the suboscillator to malfunction.
X1A
X0A
RST
GND
P20
X0
X1
Vss
Vcc
PG0
MB95310L/370L Series
GND
GND
DS07-12628-2E
25
MB95310L/370L Series
■ BLOCK DIAGRAM (MB95310L Series)
F2MC-8FX CPU
RST
Flash with security function
(60/36/20 Kbyte)
Reset with LVD
X1
RAM (2032/1008/496 bytes)
X0
X1A
CR
Oscillator
Main PLL
oscillator
circuit
Interrupt controller
X0A
P22/TO00
8/16-bit composite
timer ch. 0
Clock control
P50/TO01
P51/EC0
Watch counter
P12/DBG
P00/AN00-P03/AN03
P13/ADTG
AVCC
On-chip debug
8/10-bit A/D converter
Wild register
External interrupt
P14/UCK0
P11/UO0
UART/SIO ch. 0
P10/UI0
PG0/UCK1
P94/UO1
Internal Bus
AVss
P00/INT00-P07/INT07
P90/V3-P93/V0
PA0/COM0-PA3/COM3
PB0/SEG00-PB7/SEG07
PC0/SEG08-PC7/SEG15
P60/SEG16-P67/SEG23
LCDC
(40 SEG × 4 COM)
PE0/SEG24-PE7/SEG31
UART/SIO ch. 1
P43/SEG32-P40/SEG35
P95/UI1
P07/SEG36-P04/SEG39
P20/PPG00
*
8/16bit PPG ch. 0
P21/PPG01
P52/TI0
16-bit reload timer
P53/TO0
P16/PPG10
8/16bit PPG ch. 1
P15/PPG11
P42/TO11
P23/SCL0
I2C
8/16-bit composite
timer ch. 1
P41/TO10
P40/EC1
P24/SDA0
Port
Port
*: 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as an event counter when the event counter operating mode is enabled.
26
DS07-12628-2E
MB95310L/370L Series
■ BLOCK DIAGRAM (MB95370L Series)
F2MC-8FX CPU
RST
Flash with security function
(60/36/20 Kbyte)
Reset with LVD
X1
RAM (2032/1008/496 bytes)
X0
X1A
CR
Oscillator
Main PLL
oscillator
circuit
Interrupt controller
X0A
P22/TO00
8/16-bit composite
timer ch. 0
Clock control
P13/TO01
P14/EC0
Watch counter
P12/DBG
P00/AN00-P03/AN03
P13/ADTG
AVCC
On-chip debug
8/10-bit A/D converter
Wild register
External interrupt
P14/UCK0
P11/UO0
UART/SIO ch. 0
P10/UI0
P07/UCK1
PE7/UO1
Internal Bus
AVss
P00/INT00-P07/INT07
P90/V3-P92/V1
PA0/COM0-PA3/COM3
PB0/SEG00-PB7/SEG07
PC0/SEG08-PC3/SEG11
P60/SEG12-P67/SEG19
LCDC
(32 SEG × 4 COM)
PE0/SEG20-PE7/SEG27
UART/SIO ch. 1
P07/SEG28-P04/SEG31
PE6/UI1
P20/PPG00
*
8/16bit PPG ch. 0
P21/PPG01
P14/TI0
16-bit reload timer
PE5/TO0
P16/PPG10
8/16bit PPG ch. 1
P15/PPG11
P05/TO10
P23/SCL0
I2C
8/16-bit composite
timer ch. 1
P06/TO11
P04/EC1
P24/SDA0
Port
Port
*: 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as an event counter when the event counter operating mode is enabled.
DS07-12628-2E
27
MB95310L/370L Series
■ CPU CORE
• Memory Space
The memory space of the MB95310L/370L Series is 64 Kbyte in size, and consists of an I/O area, a data
area, and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95310L/370L Series are shown
below.
• Memory Maps
MB95F314E/F314L
MB95F374E/F374L
MB95F316E/F316L
MB95F376E/F376L
0000H
0000H
Access prohibited
RAM 496 bytes
0080H
0090H
0100H
0200H
Access prohibited
0F80H
Access prohibited
RAM 2032 bytes
Registers
0200H
Access prohibited
0F80H
Flash 4 Kbyte
I/O area
0080H
0090H
0100H
0480H
0880H
0F80H
Extended I/O area
Extended I/O area
1000H
2000H
Access prohibited
RAM 1008 bytes
Registers
Registers
0200H
0280H
0000H
I/O area
I/O area
0080H
0090H
0100H
MB95F318E/F318L
MB95F378E/F378L
1000H
2000H
Flash 4 Kbyte
Access prohibited
Extended I/O area
1000H
Vacant
Vacant
7FFFH
Flash 60 Kbyte
Flash 32 Kbyte
BFFFH
Flash 16 Kbyte
FFFFH
28
FFFFH
FFFFH
DS07-12628-2E
MB95310L/370L Series
■ I/O MAP (MB95310L Series)
Address
Register
abbreviation
0000H
PDR0
0001H
Register name
R/W
Initial value
Port 0 data register
R/W
00000000B
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W XXXXXX11B
0008H
STBC
Standby control register
R/W
0009H
RSRR
Reset source register
R/W 000XXXXXB
(Disabled)
00000XXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH
PDR2
Port 2 data register
R/W
00000000B
000FH
DDR2
Port 2 direction register
R/W
00000000B
0010H,
0011H
—
—
—
0012H
PDR4
Port 4 data register
R/W
00000000B
0013H
DDR4
Port 4 direction register
R/W
00000000B
0014H
PDR5
Port 5 data register
R/W
00000000B
0015H
DDR5
Port 5 direction register
R/W
00000000B
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
001BH
—
—
—
001CH
PDR9
Port 9 data register
R/W
00000000B
001DH
DDR9
Port 9 direction register
R/W
00000000B
(Disabled)
(Disabled)
001EH
PDRA
Port A data register
R/W
00000000B
001FH
DDRA
Port A direction register
R/W
00000000B
0020H
PDRB
Port B data register
R/W
00000000B
0021H
DDRB
Port B direction register
R/W
00000000B
0022H
PDRC
Port C data register
R/W
00000000B
0023H
DDRC
Port C direction register
R/W
00000000B
0024H,
0025H
—
—
—
(Disabled)
(Continued)
DS07-12628-2E
29
MB95310L/370L Series
Address
Register
abbreviation
0026H
PDRE
0027H
DDRE
0028H,
0029H
—
002AH
PDRG
002BH
Register name
R/W
Initial value
Port E data register
R/W
00000000B
Port E direction register
R/W
00000000B
—
—
Port G data register
R/W
00000000B
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
PUL2
Port 2 pull-up register
R/W
00000000B
002FH,
0030H
—
—
—
0031H
PUL5
R/W
00000000B
0032H,
0033H
—
—
—
0034H
PUL9
Port 9 pull-up register
R/W
00000000B
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1 ch. 0
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1 ch. 0
R/W
00000000B
0038H
T11CR1
8/16-bit composite timer 11 status control register 1 ch. 1
R/W
00000000B
0039H
T10CR1
8/16-bit composite timer 10 status control register 1 ch. 1
R/W
00000000B
003AH
PC01
8/16-bit PPG01 control register ch. 0
R/W
00000000B
003BH
PC00
8/16-bit PPG00 control register ch. 0
R/W
00000000B
003CH
PC11
8/16-bit PPG11 control register ch. 1
R/W
00000000B
003DH
PC10
8/16-bit PPG10 control register ch. 1
R/W
00000000B
003EH
TMCSRH
16-bit reload timer control status register upper ch. 0
R/W
00000000B
003FH
TMCSRL
16-bit reload timer control status register lower ch. 0
R/W
00000000B
0040H
to
0047H
—
—
—
0048H
EIC00
External interrupt circuit control register ch. 0/ch. 1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH,
004DH
—
—
—
004EH
LVDR
LVD reset voltage selection ID register
R/W
00000000B
004FH
LVDC
LVD control register
R/W
X000000XB
0050H
to
0055H
—
—
—
(Disabled)
(Disabled)
Port 5 pull-up register
(Disabled)
(Disabled)
(Disabled)
(Disabled)
(Continued)
30
DS07-12628-2E
MB95310L/370L Series
Address
Register
abbreviation
0056H
SMC10
0057H
SMC20
0058H
R/W
Initial value
UART/SIO serial mode control register 1 ch. 0
R/W
00000000B
UART/SIO serial mode control register 2 ch. 0
R/W
00100000B
SSR0
UART/SIO serial status register ch. 0
R/W
00000001B
0059H
TDR0
UART/SIO output data register ch. 0
R/W
00000000B
005AH
RDR0
UART/SIO input data register ch. 0
R
00000000B
005BH
SMC11
UART/SIO serial mode control register 1 ch. 1
R/W
00000000B
005CH
SMC21
UART/SIO serial mode control register 2 ch. 1
R/W
00100000B
005DH
SSR1
UART/SIO serial status register ch. 1
R/W
00000001B
005EH
TDR1
UART/SIO output data register ch. 1
R/W
00000000B
005FH
RDR1
UART/SIO input data register ch. 1
R
00000000B
0060H
IBCR00
0061H
IBCR10
Register name
I2C bus control register 0
R/W
00000001B
2
R/W
00000000B
2
R
00000000B
I C bus control register 1
0062H
IBCR0
I C bus status register
0063H
IDDR0
I2C data register
R/W
00000000B
0064H
IAAR0
I2C address register
R/W
00000000B
R/W
00000000B
—
—
2
0065H
ICCR0
I C clock control register
0066H
to
006BH
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register upper
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register lower
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
R
00000000B
0075H
—
—
—
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
(Disabled)
Flash memory status register 3
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Continued)
DS07-12628-2E
31
MB95310L/370L Series
Address
Register
abbreviation
0079H
ILR0
007AH
Register name
R/W
Initial value
Interrupt level setting register 0
R/W
11111111B
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0 ch. 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0 ch. 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register ch. 0
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register ch. 0
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
ch. 0
R/W
00000000B
0F97H
T11CR0
8/16-bit composite timer 11 status control register 0 ch. 1
R/W
00000000B
0F98H
T10CR0
8/16-bit composite timer 10 status control register 0 ch. 1
R/W
00000000B
0F99H
T11DR
8/16-bit composite timer 11 data register ch. 1
R/W
00000000B
0F9AH
T10DR
8/16-bit composite timer 10 data register ch. 1
R/W
00000000B
0F9BH
TMCR1
8/16-bit composite timer 10/11 timer mode control register
ch. 1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG01 cycle setting buffer register ch. 0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG00 cycle setting buffer register ch. 0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG01 duty setting buffer register ch. 0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG00 duty setting buffer register ch. 0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG11 cycle setting buffer register ch. 1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG10 cycle setting buffer register ch. 1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG11 duty setting buffer register ch. 1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG10 duty setting buffer register ch. 1
R/W
11111111B
(Disabled)
(Disabled)
(Continued)
32
DS07-12628-2E
MB95310L/370L Series
Address
Register
abbreviation
0FA4H
PPGS
0FA5H
0FA6H
0FA7H
Register name
R/W
Initial value
8/16-bit PPG start register
R/W
00000000B
REVC
8/16-bit PPG output inversion register
R/W
00000000B
TMRH0
16-bit reload timer timer register upper
R/W
00000000B
TMRLRH0
16-bit reload timer reload register upper
R/W
00000000B
TMRL0
16-bit reload timer timer register lower
R/W
00000000B
TMRLRL0
16-bit reload timer reload register lower
R/W
00000000B
—
—
0FA8H
to
0FBDH
—
0FBEH
PSSR0
UART/SIO dedicated baud rate generator prescaler selecting
R/W
register ch. 0
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
R/W
00000000B
0FC0H
PSSR1
UART/SIO dedicated baud rate generator prescaler selecting
R/W
register ch. 1
00000000B
0FC1H
BRSR1
UART/SIO dedicated baud rate generator baud rate setting
register ch. 1
R/W
00000000B
0FC2H
—
—
—
0FC3H
AIDRL
A/D input disable register (lower)
R/W
00000000B
0FC4H
LCDCC
LCDC control register
R/W
00010000B
0FC5H
LCDCE1
LCDC enable register 1
R/W
00110000B
0FC6H
LCDCE2
LCDC enable register 2
R/W
00000000B
0FC7H
LCDCE3
LCDC enable register 3
R/W
00000000B
0FC8H
LCDCE4
LCDC enable register 4
R/W
00000000B
0FC9H
LCDCE5
LCDC enable register 5
R/W
00000000B
0FCAH
LCDCE6
LCDC enable register 6
R/W
00000000B
0FCBH
LCDCB1
LCDC blinking setting register 1
R/W
00000000B
0FCCH
LCDCB2
LCDC blinking setting register 2
R/W
00000000B
0FCDH
to
0FE0H
LCDRAM
LCDC display RAM
R/W
00000000B
0FE1H
—
—
—
0FE2H
EVCR
Event counter control register
R/W
00000000B
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 0XXXXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 00XXXXXXB
0FE6H
to
0FE8H
—
0FE9H
CMCR
Clock monitoring control register
0FEAH
CMDR
Clock monitoring data register
(Disabled)
(Disabled)
(Disabled)
(Disabled)
—
—
R/W
XX000000B
R
00000000B
(Continued)
DS07-12628-2E
33
MB95310L/370L Series
(Continued)
Address
Register
abbreviation
0FEBH
WDTH
0FECH
WDTL
0FEDH
—
0FEEH
ILSR
0FEFH
WICR
0FF0H
to
0FFFH
—
Register name
R/W
Initial value
Watchdog timer selection ID register (upper)
R
XXXXXXXXB
Watchdog timer selection ID register (lower)
R
XXXXXXXXB
—
—
Input level select register
R/W
00000000B
Interrupt pin control register
R/W
01000000B
—
—
(Disabled)
(Disabled)
• R/W access symbols
R/W : Readable / Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
34
DS07-12628-2E
MB95310L/370L Series
■ I/O MAP (MB95370L Series)
Address
Register
abbreviation
0000H
PDR0
0001H
Register name
R/W
Initial value
Port 0 data register
R/W
00000000B
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W XXXXXX11B
0008H
STBC
Standby control register
R/W
0009H
RSRR
Reset source register
R/W 000XXXXXB
(Disabled)
00000XXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH
PDR2
Port 2 data register
R/W
00000000B
000FH
DDR2
Port 2 direction register
R/W
00000000B
0010H
to
0015H
—
—
—
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
001BH
—
—
—
001CH
PDR9
Port 9 data register
R/W
00000000B
001DH
DDR9
Port 9 direction register
R/W
00000000B
001EH
PDRA
Port A data register
R/W
00000000B
001FH
DDRA
Port A direction register
R/W
00000000B
0020H
PDRB
Port B data register
R/W
00000000B
0021H
DDRB
Port B direction register
R/W
00000000B
0022H
PDRC
Port C data register
R/W
00000000B
0023H
DDRC
Port C direction register
R/W
00000000B
0024H,
0025H
—
—
—
0026H
PDRE
Port E data register
R/W
00000000B
0027H
DDRE
Port E direction register
R/W
00000000B
0028H
to
002BH
—
—
—
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
PUL2
Port 2 pull-up register
R/W
00000000B
(Disabled)
(Disabled)
(Disabled)
(Disabled)
(Continued)
DS07-12628-2E
35
MB95310L/370L Series
Address
Register
abbreviation
Register name
R/W
Initial value
002FH
to
0033H
—
(Disabled)
—
—
0034H
PUL9
R/W
00000000B
0035H
—
—
—
0036H
T01CR1
8/16-bit composite timer 01 status control register 1 ch. 0
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1 ch. 0
R/W
00000000B
0038H
T11CR1
8/16-bit composite timer 11 status control register 1 ch. 1
R/W
00000000B
0039H
T10CR1
8/16-bit composite timer 10 status control register 1 ch. 1
R/W
00000000B
003AH
PC01
8/16-bit PPG01 control register ch. 0
R/W
00000000B
003BH
PC00
8/16-bit PPG00 control register ch. 0
R/W
00000000B
003CH
PC11
8/16-bit PPG11 control register ch. 1
R/W
00000000B
003DH
PC10
8/16-bit PPG10 control register ch. 1
R/W
00000000B
003EH
TMCSRH
16-bit reload timer control status register upper ch. 0
R/W
00000000B
003FH
TMCSRL
16-bit reload timer control status register lower ch. 0
R/W
00000000B
0040H
to
0047H
—
—
—
0048H
EIC00
External interrupt circuit control register ch. 0/ch. 1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH,
004DH
—
—
—
004EH
LVDR
LVD reset voltage selection ID register
R/W
00000000B
004FH
LVDC
LVD control register
R/W
X000000XB
0050H
to
0055H
—
—
—
0056H
SMC10
UART/SIO serial mode control register 1 ch. 0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch. 0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch. 0
R/W
00000001B
0059H
TDR0
UART/SIO output data register ch. 0
R/W
00000000B
005AH
RDR0
UART/SIO input data register ch. 0
R
00000000B
005BH
SMC11
UART/SIO serial mode control register 1 ch. 1
R/W
00000000B
005CH
SMC21
UART/SIO serial mode control register 2 ch. 1
R/W
00100000B
005DH
SSR1
UART/SIO serial status register ch. 1
R/W
00000001B
005EH
TDR1
UART/SIO output data register ch. 1
R/W
00000000B
005FH
RDR1
UART/SIO input data register ch. 1
R
00000000B
Port 9 pull-up register
(Disabled)
(Disabled)
(Disabled)
(Disabled)
(Continued)
36
DS07-12628-2E
MB95310L/370L Series
Address
Register
abbreviation
0060H
IBCR00
0061H
0062H
0063H
R/W
Initial value
I2C bus control register 0
R/W
00000001B
IBCR10
I2C bus control register 1
R/W
00000000B
IBCR0
I2C bus status register
IDDR0
Register name
R
00000000B
2
R/W
00000000B
2
I C data register
0064H
IAAR0
I C address register
R/W
00000000B
0065H
ICCR0
I2C clock control register
R/W
00000000B
0066H
to
006BH
—
—
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register upper
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register lower
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
R
00000000B
0075H
—
—
—
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
(Disabled)
Flash memory status register 3
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Disabled)
(Continued)
DS07-12628-2E
37
MB95310L/370L Series
Address
Register
abbreviation
Register name
R/W
Initial value
0F89H
to
0F91H
—
(Disabled)
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0 ch. 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0 ch. 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register ch. 0
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register ch. 0
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
ch. 0
R/W
00000000B
0F97H
T11CR0
8/16-bit composite timer 11 status control register 0 ch. 1
R/W
00000000B
0F98H
T10CR0
8/16-bit composite timer 10 status control register 0 ch. 1
R/W
00000000B
0F99H
T11DR
8/16-bit composite timer 11 data register ch. 1
R/W
00000000B
0F9AH
T10DR
8/16-bit composite timer 10 data register ch. 1
R/W
00000000B
0F9BH
TMCR1
8/16-bit composite timer 10/11 timer mode control register
ch. 1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG01 cycle setting buffer register ch. 0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG00 cycle setting buffer register ch. 0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG01 duty setting buffer register ch. 0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG00 duty setting buffer register ch. 0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG11 cycle setting buffer register ch. 1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG10 cycle setting buffer register ch. 1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG11 duty setting buffer register ch. 1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG10 duty setting buffer register ch. 1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG start register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
TMRH0
16-bit reload timer timer register upper
R/W
00000000B
TMRLRH0
16-bit reload timer reload register upper
R/W
00000000B
TMRL0
16-bit reload timer timer register lower
R/W
00000000B
TMRLRL0
16-bit reload timer reload register lower
R/W
00000000B
—
—
0FA6H
0FA7H
0FA8H
to
0FBDH
—
0FBEH
PSSR0
UART/SIO dedicated baud rate generator prescaler selecting
R/W
register ch. 0
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
R/W
00000000B
0FC0H
PSSR1
UART/SIO dedicated baud rate generator prescaler selecting
R/W
register ch. 1
00000000B
0FC1H
BRSR1
UART/SIO dedicated baud rate generator baud rate setting
register ch. 1
R/W
00000000B
0FC2H
—
—
—
0FC3H
AIDRL
A/D input disable register (lower)
R/W
00000000B
0FC4H
LCDCC
LCDC control register
R/W
00010000B
(Disabled)
(Disabled)
(Continued)
38
DS07-12628-2E
MB95310L/370L Series
(Continued)
Address
Register
abbreviation
0FC5H
LCDCE1
0FC6H
Register name
R/W
Initial value
LCDC enable register 1
R/W
00110000B
LCDCE2
LCDC enable register 2
R/W
00000000B
0FC7H
LCDCE3
LCDC enable register 3
R/W
00000000B
0FC8H
LCDCE4
LCDC enable register 4
R/W
00000000B
0FC9H
LCDCE5
LCDC enable register 5
R/W
00000000B
0FCAH
—
—
—
0FCBH
LCDCB1
LCDC blinking setting register 1
R/W
00000000B
0FCCH
LCDCB2
LCDC blinking setting register 2
R/W
00000000B
0FCDH
to
0FDCH
LCDRAM
LCDC display RAM
R/W
00000000B
0FDDH
to
0FE1H
—
—
—
0FE2H
EVCR
Event counter control register
R/W
00000000B
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 0XXXXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 00XXXXXXB
0FE6H
to
0FE8H
—
0FE9H
CMCR
Clock monitoring control register
0FEAH
CMDR
0FEBH
(Disabled)
(Disabled)
(Disabled)
—
—
R/W
XX000000B
Clock monitoring data register
R
00000000B
WDTH
Watchdog timer selection ID register (upper)
R
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R
XXXXXXXXB
0FEDH
—
—
—
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
—
—
—
(Disabled)
(Disabled)
• R/W access symbols
R/W : Readable / Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS07-12628-2E
39
MB95310L/370L Series
■ INTERRUPT SOURCE TABLE
Vector table address
Interrupt
request
number
Upper
Lower
Bit name of
interrupt level
setting register
IRQ00
FFFAH
FFFBH
L00 [1:0]
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
—
IRQ07
FFECH
FFEDH
L07 [1:0]
—
IRQ08
FFEAH
FFEBH
L08 [1:0]
IRQ09
FFE8H
FFE9H
L09 [1:0]
8/16-bit PPG ch. 1 (upper)
IRQ10
FFE6H
FFE7H
L10 [1:0]
16-bit reload timer ch. 0
IRQ11
FFE4H
FFE5H
L11 [1:0]
8/16-bit PPG ch. 0 (upper)
IRQ12
FFE2H
FFE3H
L12 [1:0]
8/16-bit PPG ch. 0 (lower)
IRQ13
FFE0H
FFE1H
L13 [1:0]
8/16-bit composite timer ch. 1
(upper)
IRQ14
FFDEH
FFDFH
L14 [1:0]
IRQ15
FFDCH
FFDDH
L15 [1:0]
IRQ16
FFDAH
FFDBH
L16 [1:0]
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
IRQ20
FFD2H
FFD3H
L20 [1:0]
IRQ21
FFD0H
FFD1H
L21 [1:0]
8/16-bit composite timer ch. 1
(lower)
IRQ22
FFCEH
FFCFH
L22 [1:0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
UART/SIO ch. 0
Low-voltage detection reset circuit
8/16-bit PPG ch. 1 (lower)
UART/SIO ch. 1
—
I2C
—
Watch prescaler
Watch counter
—
40
Priority order of interrupt sources of
the same level
(occurring simultaneously)
High
Low
DS07-12628-2E
MB95310L/370L Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Power supply voltage for
LCD
Rating
Unit
Remarks
Min
Max
VCC, AVCC
VSS − 0.3
VSS + 4.0
V
*2
V0 to V3
VSS − 0.3
VSS + 4.0
V
Products with LCD internal division
resistance*3
VSS − 0.3
VSS + 6.0
V
P23,P24*4
VSS − 0.3
VSS + 4.0
V
Other than P23,P24*4
*4
Input voltage*1
VI
Output voltage*1
VO
VSS − 0.3
VSS + 4.0
V
ICLAMP
−2.0
+2.0
mA
Applicable to specific pins*5
Σ|ICLAMP|
—
20
mA
Applicable to specific pins*5
IOL
—
15
mA
Applicable to specific pins*5
Applicable to specific pins*5
Average output current =
operating current × operating ratio
(1 pin)
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
“L” level average current
IOLAV
—
4
mA
“L” level total maximum
output current
ΣIOL
—
100
mA
ΣIOLAV
—
50
mA
Total average output current =
operating current × operating ratio
(Total number of pins)
IOH
—
-15
mA
Applicable to specific pins*5
Applicable to specific pins*5
Average output current =
operating current × operating ratio
(1 pin)
“L” level total average
output current
“H” level maximum
output current
“H” level average
current
IOHAV
—
-4
mA
“H” level total maximum
output current
ΣIOH
—
-100
mA
ΣIOHAV
—
-50
mA
Power consumption
Pd
—
320
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
“H” level total average
output current
Storage temperature
Total average output current =
operating current × operating ratio
(Total number of pins)
*1: These parameters are based on the condition that VSS is 0.0 V.
*2: Apply equal potential to VCC and AVCC.
*3: V0 to V3 should not exceed VCC + 0.3 V.
*4: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum
current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of
the VI rating.
(Continued)
DS07-12628-2E
41
MB95310L/370L Series
(Continued)
*5: Applicable to the following pins: P00 to P07, P10, P11, P13 to P16, P20 to P22, P40 to P43, P50 to P53,
P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7, PE0 to PE7, PG0
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistance should be set so that when the HV (High Voltage) signal is applied the
input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged
periods.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, and
thus affects other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit
• Input/Output equivalent circuit
Protective diode
VCC
HV(High Voltage) input (0 V to 16 V)
P-ch
Limiting
resistor
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
42
DS07-12628-2E
MB95310L/370L Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Power supply
voltage
Operating
temperature
VCC,
AVCC
TA
Value
Unit
Remarks
Min
Max
1.8*1*2*3
3.6
In normal operation,
TA = -10°C to +85°C
2.0
3.6
In normal operation,
TA = -40°C to +85°C
1.5
3.6
Hold condition in stop mode
3.10*3
3.6
TA = +5°C to +35°C
1.5
3.6
Hold condition in stop mode
−40
+85
+5
+35
V
°C
Other than on-chip debug
mode
On-chip debug mode
Other than on-chip debug mode
On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is initially 2.03 V when the low-voltage detection reset is used.
*3: The threshold voltage can be set to be 2.03 V, 2.55 V, 3.10 V by software.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-12628-2E
43
MB95310L/370L Series
3. DC Characteristics
(VCC = 3.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Pin name
Condition
Value
Min
Typ*5
Max
Unit
VIHI1
P10, P95*1,
PE6*2
*3
0.7 VCC
—
VCC + 0.3
V
VIHI2
P23, P24
*3
0.7 VCC
—
VSS + 5.5
V
VIHS1
P00 to P07,
P10 to P16,
P20 to P22,
P40 to P43*1,
P50 to P53*1,
P60 to P67,
P90 to P92,
P93 to P95*1,
PA0 to PA3,
PB0 to PB7,
PC0 to PC3,
PC4 to PC7*1,
PE0 to PE7,
PG0*1
*3
0.8 VCC
—
VCC + 0.3
V
VIHS2
P23, P24
*3
0.8 VCC
—
VSS + 5.5
V
VIHM
RST
—
0.8 VCC
—
VCC + 0.3
V
VIL
P10, P23, P24,
P95*1, PE6*2
*3
VSS − 0.3
—
0.3 VCC
V
VILS
P00 to P07,
P10 to P16,
P20 to P24,
P40 to P43*1,
P50 to P53*1,
P60 to P67,
P90 to P92,
P93 to P95*1,
PA0 to PA3,
PB0 to PB7,
PC0 to PC3,
PC4 to PC7*1,
PE0 to PE7,
PG0*1
*3
VSS − 0.3
—
0.2 VCC
V
VILM
RST
—
VSS − 0.3
—
0.2 VCC
V
“H” level
output
voltage
VOH
Output pin other
than P12, P23,
P24
IOH = 4.0 mA
VCC − 0.5
—
—
V
“L” level
output
voltage
VOL
Output pin other
than RST
IOL = 4.0 mA
—
—
0.4
V
“H” level
input voltage
“L” level
input voltage
Remarks
When selecting
CMOS input level
Hysteresis input
When selecting
CMOS input level
Hysteresis input
(Continued)
44
DS07-12628-2E
MB95310L/370L Series
(VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Pin name
Condition
Input leakage
current (Hi-Z
output
leakage
current)
ILI
Ports other than
P12, P23, P24
0.0 V<VI<VCC
Open-drain
output
leakage
voltage
Pull-up
resistance
Input
capacitance
Value
Unit
Remarks
Min
Typ*5
Max
−5
—
+5
When pull-up
µA resistance is
disabled
µA
ILIOD
P12, P23, P24 0.0 V<VI<VSS + 5.5 V
—
—
5
RPULL
P00 to P03,
P10, P11,
P13 to P16,
P20 to P22,
P50 to P53*1,
P94, P95*1,
PG0*1
VI = 0.0 V
25
50
100
When pull-up
kΩ resistance is
enabled
Other than VCC
f = 1 MHz
and VSS
—
5
15
pF
CIN
ICC
Power supply
current*4
ICCS
ICCL
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
VCC
(External clock FCH = 32 MHz
operation)
FMP = 16 MHz
Main sleep mode
(divided by 2)
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25°C
—
16.5
27.7
Except during
Flash memory
mA
programming
and erasing
—
38.1
44.9
During Flash
memory
mA
programming
and erasing
—
9
15.9
mA
—
22.6
37.9
µA
(Continued)
DS07-12628-2E
45
MB95310L/370L Series
(VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Condition
Value
Unit
Min
Typ*5
Max
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25°C
—
11.2
16.5
µA
ICCT
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
—
6.7
9
µA
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
—
10.1
19.2
mA
FCH = 6.4 MHz
VCC
F
(External clock MP = 16 MHz
Main PLL mode
operation)
(multiplied by 2.5)
—
16.2
30.7
mA
ICCMPLL
Power supply
current*4
Pin name
ICCMCR
FCRH = 12.5 MHz
FMP = 12.5 MHz
Main CR clock mode
—
7.9
13.2
mA
ICCSCR
Sub-CR clock mode
(divided by 2)
TA = +25°C
—
77.8
138.5
µA
ICTS
FCH = 32 MHz
Time-base timer
mode
TA = +25°C
—
4.3
7.4
mA
ICCH
Substop mode
TA = +25°C
—
1
5
µA
Current
consumption for
A/D conversion at
16 MHz
—
0.8
1.9
mA
Current
consumption for
stopping A/D
conversion at
16 MHz
—
1
5
µA
IA
AVCC
IAH
Remarks
(Continued)
46
DS07-12628-2E
MB95310L/370L Series
(Continued)
Parameter
(VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Symbol
Pin name
ILVD
Power supply
current*4
ICRH
VCC
ICRL
LCD internal
division
resistance
COM0 to
COM3 output
impedance
—
RLCD
Condition
LCD leakage
current
Unit
Min
Typ*5
Max
Current
consumption for the
low-voltage
detection reset
circuit
—
6
9.8
µA
Current
consumption for the
main CR oscillator
—
0.5
0.6
mA
Current
consumption for the
sub-CR oscillator
oscillating at
100 kHz
—
20
72
µA
Between V3 and VSS
—
300
—
kΩ
—
—
5
kΩ
—
—
7
kΩ
−1
—
+1
µA
RVCOM COM0 to COM3
SEG00 to
SEG39
output
impedance
Value
Remarks
V1 to V3 = 3.6 V
RVSEG
SEG00 to
SEG39
ILCDL
V0 to V3,
COM0 to
COM3, SEG00
to SEG39
—
*1: It is for MB95310L Series.
*2: It is for MB95370L Series.
*3: The input level can be switched between “CMOS input level” and “hysteresis input level”. The input level
selection register (ILSR) is used to switch between the two input levels.
*4: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See “4. AC Characteristics: (1) Clock Timing” for FCH and FCL.
• See “4. AC Characteristics: (2) Source Clock/Machine Clock” for FMP and FMPL.
*5: VCC = 3.0 V, TA = +25°C
DS07-12628-2E
47
MB95310L/370L Series
4. AC Characteristics
(1) Clock Timing
(VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
FCH
Pin name Condition
—
FCRH
—
FCL
—
Input clock
pulse width
Input clock
rise time
and fall time
CR
oscillation
start time
48
tHCYL
X0, X1
tLCYL
X0A, X1A
tWH1
tWL1
X0
tWH2
tWL2
X0A
tCR
tCF
X0, X0A
—
Max
1.00
—
16.25
MHz
When the main oscillation
circuit is used
1.00
—
32.50
MHz
When the main external
clock is used
3.00
—
8.13
MHz Main PLL multiplied by 2
3.00
—
6.5
MHz Main PLL multiplied by 2.5
3.00
—
4.06
MHz Main PLL multiplied by 4
12.25
12.5
12.75
MHz
9.8
10
10.2
7.84
8
8.16
0.98
1
1.02
MHz Operating conditions:
• The main CR clock is used.
MHz • TA = −10°C to +85°C
MHz
12.1875
12.5
9.75
10
10.25
7.8
8
8.2
0.975
1
1.025
—
32.768
—
kHz
When the sub-oscillation
circuit is used
—
32.768
—
kHz
When the sub-external clock
is used
50
100
200
kHz
When the sub-CR clock is
used
61.5
—
1000
ns
When the main oscillation
circuit is used
30.8
—
1000
ns
When the external clock is
used
—
30.5
—
µs
When the subclock is used
61.5
—
—
ns
—
15.2
—
µs
When using external clock
and the duty ratio is about
30% to 70%
—
—
5
ns
When the external clock is
used
12.8125 MHz
MHz Operating conditions:
• The main CR clock is used.
MHz • TA = −40°C to −10°C
MHz
—
X1: open
Remarks
Typ
X0A, X1A
FCRL
Clock cycle
time
Unit
Min
X0, X1
—
Clock
frequency
Value
tCRHWK
—
—
—
—
150
µs
When the main CR clock is
used
tCRLWK
—
—
—
—
10
µs
When the sub-CR clock is
used
DS07-12628-2E
MB95310L/370L Series
• Input waveform generated when an external clock (main clock) is used
tHCYL
tWH1
tWL1
tCR
tCF
X0, X1
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When the external clock is used
(X1 is open)
X0
X1
When the external clock is used
X1
X0
X1
Open
FCH
FCH
FCH
• Input waveform generated when an external clock (subclock) is used
tLCYL
tWH2
tCR
X0A
tWL2
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When the external clock is used
X0A
X1A
Open
FCL
DS07-12628-2E
49
MB95310L/370L Series
(2) Source Clock/Machine Clock
(VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Source clock
cycle time*1
Symbol
tSCLK
Pin
name
—
FSP
Source clock
frequency
—
FSPL
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
FMPL
Min
Typ
Max
Unit
Remarks
61.5
—
2000
ns
When the main oscillation clock is used
Min: FCH = 8.125 MHz, multiplied by the
PLL multiplier of 2
Max: FCH = 1 MHz, divided by 2
80
—
1000
ns
When the main CR clock is used
Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
—
61
—
µs
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
0.50
—
16.25
MHz When the main oscillation clock is used
1
—
12.5
MHz When the main CR clock is used
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
80
—
16000
ns
When the main CR clock is used
Min: FSP = 12.5 MHz
Max: FSP = 1 MHz, divided by 16
61
—
976.5
µs
When the sub-oscillation clock is used
Min: FSPL = 16.393 kHz, no division
Max: FSPL = 16.393 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
MHz When the main oscillation clock is used
0.0625
—
12.5
MHz When the main CR clock is used
1.024
—
16.384
3.125
—
50
—
FMP
Machine clock
frequency
Value
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
kHz When the sub-oscillation clock is used
kHz
When the sub-CR clock is used
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select
bits (SYCC:DIV1 and DIV0). This source clock is divided to become a machine clock according to the division
ratio set by the machine clock divide ratio select bits (SYCC:DIV1 and DIV0). In addition, a source clock can
be selected from the following.
• Main clock divided by 2
• PLL multiplication of main clock (select from 2, 2.5, 4 multiplication)
• Main CR clock divided by 2
• Subclock divided by 2
• Sub-CR clock divided by 2
(Continued)
50
DS07-12628-2E
MB95310L/370L Series
(Continued)
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Schematic diagram of the clock generation block
Main PLL
× 2
× 2.5
× 4
FCH
(main oscillation)
Divided
by 2
FCRH
(Main CR clock)
FCL
(sub-oscillation)
FCRL
(Sub-CR clock)
Divided
by 2
Divided
by 2
Clock mode select bits
(SYCC2: RCS1, RCS0)
DS07-12628-2E
SCLK
(source clock)
Division
circuit
× 1
× 1/4
× 1/8
×1/16
MCLK
(machine clock)
Machine clock divide ratio select bits
(SYCC: DIV1, DIV0)
51
MB95310L/370L Series
• Operating voltage - Operating frequency (When TA = −10°C to +85°C)
Without the on-chip debug function
Operating voltage (V)
3.6
2.7
1.8
16 kHz
3 MHz
5 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
Without the on-chip debug function
Operating voltage (V)
3.6
2.7
2.0
16 kHz
3 MHz
7.5 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
52
DS07-12628-2E
MB95310L/370L Series
• Operating voltage - Operating frequency (When TA = +5°C to +35°C)
With the on-chip debug function
Operating voltage (V)
3.6
2.7*3
2.03*1
16 kHz
*2
3 MHz
7.875 MHz*4
16.25 MHz
Source clock frequency (FSP)
*1: This is the default LVD reset clear threshold: 1.93 V ± 0.10 V. It can also be set to 2.40 V ± 0.15 V or
2.95 V ± 0.15 V.
*2: If the LVD reset clear threshold is set to 2.95 V ± 0.15 V, the slope from 10 MHz to 16.25 MHz should be a
horizontal line.
*3: The operating voltage becomes 3.1 V if the LVD reset clear threshold is set to 2.95 V ± 0.15 V.
*4: The source clock frequency becomes 14.375 MHz if the LVD reset clear threshold is set to 2.40 V ± 0.15 V.
DS07-12628-2E
53
MB95310L/370L Series
(3) External Reset
(VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
RST “L” level
pulse width
Symbol
tRSTL
Value
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns
In normal operation
Oscillation time of the
oscillator*2 + 100
—
µs
In stop mode, subclock mode,
subsleep mode, watch mode, and
power-on
100
—
µs
In time-base timer mode
*1: See “(2) Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
clock has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
tRSTL
RST
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
100 μs
Oscillation
time of
oscillator
Internal reset
54
Oscillation stabilization wait time
Execute instruction
DS07-12628-2E
MB95310L/370L Series
(4) Power-on Reset
(VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
Remarks
Wait time until power-on
tOFF
1.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 20 mV/ms as
shown below.
VCC
1.5 V
Set the slope of rising to
a value below 20 mV/ms.
Hold condition in stop mode
VSS
DS07-12628-2E
55
MB95310L/370L Series
(5) Peripheral Input Timing
(VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Peripheral input “H” pulse width
Peripheral input “L” pulse width
Symbol
tILIH
tIHIL
Value
Pin name
INT00 to INT07, EC0, EC1,
ADTG
Unit
Min
Max
2 tMCLK*
—
ns
MCLK*
—
ns
2t
*: See “(2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, EC1, ADTG
56
0.8 VCC
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
DS07-12628-2E
MB95310L/370L Series
(6) UART/SIO, Serial I/O Timing
(VCC = 3.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Serial clock cycle time
tSCYC
UCK ↓→ UO time
tSLOVI
Valid UI → UCK ↑
tIVSHI
UCK ↑→ valid UI hold time
tSHIXI
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
UCK ↓→ UO time
tSLOVE
Valid UI → UCK ↑
tIVSHE
UCK ↑→ valid UI hold time
tSHIXE
Pin name
Value
Condition
UCK0, UCK1
UCK0, UCK1,
UO0, UO1
UCK0, UCK1,
UI0, UI1
UCK0, UCK1,
UI0, UI1
UCK0, UCK1
UCK0, UCK1
UCK0, UCK1,
UO0, UO1
UCK0, UCK1,
UI0, UI1
UCK0, UCK1,
UI0, UI1
Internal clock
operation output pin:
CL = 80 pF + 1 TTL
External clock
operation output pin:
CL = 80 pF + 1 TTL
Unit
Min
Max
4 tMCLK*
—
ns
−190
+190
ns
2 tMCLK*
—
ns
2 tMCLK*
—
ns
4 tMCLK*
4 tMCLK*
—
—
ns
ns
—
190
ns
2 tMCLK*
—
ns
2 tMCLK*
—
ns
*: See “(2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
UCK0,
UCK1
tSCYC
2.4 V
0.8 V
0.8 V
tSLOVI
UO0,
UO1
2.4 V
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
UI0,
UI1
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
UCK0,
UCK1
tSHSL
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOVE
UO0,
UO1
2.4 V
0.8 V
tIVSHE
UI0,
UI1
DS07-12628-2E
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
57
MB95310L/370L Series
(7) Low-voltage Detection
(VSS = 0.0 V, VCC = 1.8 V to 3.6 V, TA = −40°C to +85°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
Power release voltage 0
VPDL0+
1.83
1.93
2.03
V
At power supply rise
Power detection voltage 0
VPDL0-
1.80
1.90
2.00
V
At power supply fall
Power release voltage 1
VPDL1+
2.25
2.40
2.55
V
At power supply rise
Power detection voltage 1
VPDL1-
2.20
2.35
2.50
V
At power supply fall
Power release voltage 2
VPDL2+
2.80
2.95
3.10
V
At power supply rise
Power detection voltage 2
VPDL2-
2.70
2.85
3.00
V
At power supply fall
Interrupt release voltage 0
VIDL0+
2.03
2.18
2.33
V
At power supply rise
Interrupt detection voltage 0
VIDL0-
2.00
2.15
2.30
V
At power supply fall
Interrupt release voltage 1
VIDL1+
2.25
2.40
2.55
V
At power supply rise
Interrupt detection voltage 1
VIDL1-
2.20
2.35
2.50
V
At power supply fall
Interrupt release voltage 2
VIDL2+
2.46
2.61
2.76
V
At power supply rise
Interrupt detection voltage 2
VIDL2-
2.40
2.55
2.70
V
At power supply fall
Interrupt release voltage 3
VIDL3+
2.67
2.82
2.97
V
At power supply rise
Interrupt detection voltage 3
VIDL3-
2.60
2.75
2.90
V
At power supply fall
Interrupt release voltage 4
VIDL4+
2.90
3.10
3.30
V
At power supply rise
Interrupt detection voltage 4
VIDL4-
2.80
3.00
3.20
V
At power supply fall
Power supply start voltage
Voff
—
—
1.8
V
Power supply end voltage
Von
3.3
—
—
V
Power supply voltage
change time
(at power supply rise)
tr
3000
—
—
µs
Slope of power supply that the reset
release signal generates within the
rating (VPDL+/VIDL+)
Power supply voltage
change time
(at power supply fall)
tf
3000
—
—
µs
Slope of power supply that the reset
detection signal generates within
the rating (VPDL-/VIDL-)
(Continued)
58
DS07-12628-2E
MB95310L/370L Series
(Continued)
(VSS = 0.0 V, VCC = 1.8 V to 3.6 V, TA = −40°C to +85°C)
Parameter
Symbol
Power reset release delay
time
Value
Unit
Min
Typ
Max
tdp1
10
—
300
µs
Power reset detection
delay time
tdp2
—
—
150
µs
Interrupt reset release
delay time
tdi1
10
—
200
µs
Interrupt reset detection
delay time
tdi2
—
—
150
µs
Remarks
VCC
Von
Voff
time
VCC
tf
tr
VPDL+/VIDL+
VPDL-/VIDL-
Reset/Interrupt
time
tdp2/tdi2
DS07-12628-2E
tdp1/tdi1
59
MB95310L/370L Series
(8) I2C Timing
(VCC = 3.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Symbol
Pin name
Conditions
Standard-mode
Fast-mode
Unit
Min
Max
Min
Max
SCL clock
frequency
fSCL
SCL0
0
100
0
400
kHz
(Repeat)
Start
condition
hold time
SDA ↓ →
SCL ↓
tHD;STA
SCL0,
SDA0
4.0
—
0.6
—
µs
SCL clock
“L” width
tLOW
SCL0
4.7
—
1.3
—
µs
SCL clock
“H” width
tHIGH
SCL0
4.0
—
0.6
—
µs
(Repeat)
Start
condition
setup time
SCL ↑ →
SDA ↓
tSU;STA
SCL0,
SDA0
4.7
—
0.6
—
µs
0
3.45*2
0
0.9*3
µs
R = 1.7 kΩ,
C = 50 pF*1
Data hold
time
SCL ↓ →
SDA ↓ ↑
tHD;DAT
SCL0,
SDA0
Data setup
time
SDA ↓ ↑ →
SCL ↑
tSU;DAT
SCL0,
SDA0
0.25
—
0.1
—
µs
Stop
condition
setup time
SCL ↑ →
SDA ↑
tSU;STO
SCL0,
SDA0
4.0
—
0.6
—
µs
tBUF
SCL0,
SDA0
4.7
—
1.3
—
µs
Bus free
time
between
stop
condition
and start
condition
*1: R represents the pull-up resistor of the SCL0 and SDA0 lines, and C the load capacitor of the SCL0 and
SDA0 lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding
the SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition
of tSU;DAT ≥ 250 ns is fulfilled.
(Continued)
60
DS07-12628-2E
MB95310L/370L Series
(Continued)
Note: The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending
on the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA0 and SCL0 if the rating of the input data set-up time cannot be
satisfied.
tWAKEUP
SDA0
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL0
tHD;STA
DS07-12628-2E
tSU;DAT
fSCL
tSU;STA
tSU;STO
61
MB95310L/370L Series
(VCC = 3.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Pin name
Conditions
Value*2
Min
Max
Unit
Remarks
SCL clock
“L” width
tLOW
SCL0
(2 + nm / 2) tMCLK − 20
—
ns Master mode
SCL clock
“H” width
tHIGH
SCL0
(nm / 2)tMCLK − 20
(nm / 2)tMCLK + 20
ns Master mode
Start
condition
hold time
tHD;STA
SCL0,
SDA0
(−1 + nm / 2) tMCLK − 20 (−1 + nm)tMCLK + 20
Master mode
Maximum
value is
applied when
ns m, n = 1, 8.
Otherwise,
the minimum
value is
applied.
Stop
condition
setup time
tSU;STO
SCL0,
SDA0
(1 + nm / 2) tMCLK − 20 (1 + nm / 2)tMCLK + 20
ns Master mode
Start
condition
setup time
tSU;STA
SCL0,
SDA0
(1 + nm / 2)tMCLK − 20 (1 + nm / 2)tMCLK + 20
ns Master mode
(2 nm + 4)tMCLK − 20
—
ns
3 tMCLK − 20
—
ns Master mode
Bus free time
between
stop
condition
and start
condition
Data hold
time
Data setup
time
tBUF
SCL0,
SDA0
tHD;DAT
SCL0,
SDA0
tSU;DAT
SCL0,
SDA0
R = 1.7 kΩ,
C = 50 pF*1
Master mode
When
assuming that
“L” of SCL is
not extended,
the minimum
value is
(−2 + nm / 2)tMCLK − 20 (−1 + nm / 2)tMCLK + 20 ns applied to first
bit of
continuous
data.
Otherwise,
the maximum
value is
applied.
(Continued)
62
DS07-12628-2E
MB95310L/370L Series
(VCC = 3.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Pin name
Conditions
Value*2
Min
Max
Unit
Remarks
Setup time
between
clearing
interrupt
and SCL
rising
tSU;INT
SCL0
(nm / 2)tMCLK − 20
(1 + nm / 2)tMCLK + 20
ns
Minimum
value is
applied to
interrupt at
9th SCL↓.
Maximum
value is
applied to
interrupt at
8th SCL↓.
SCL clock
“L” width
tLOW
SCL0
4 tMCLK − 20
—
ns
At reception
SCL clock
“H” width
tHIGH
SCL0
4 tMCLK − 20
—
ns
At reception
tHD;STA
SCL0,
SDA0
ns
Not detected
when 1 tMCLK
is used at
reception
tSU;STO
SCL0,
SDA0
ns
Not detected
when 1 tMCLK
is used at
reception
Start
condition
detection
Stop
condition
detection
2 tMCLK − 20
2 tMCLK − 20
—
—
R = 1.7 kΩ,
C = 50 pF*1
tSU;STA
SCL0,
SDA0
2 tMCLK − 20
—
ns
Not detected
when 1 tMCLK
is used at
reception
Bus free
time
tBUF
SCL0,
SDA0
2 tMCLK − 20
—
ns
At reception
Data hold
time
tHD;DAT
SCL0,
SDA0
2 tMCLK − 20
—
ns
At slave
transmission
mode
Data setup
time
tSU;DAT
SCL0,
SDA0
tLOW − 3 tMCLK − 20
—
ns
At slave
transmission
mode
Data hold
time
tHD;DAT
SCL0,
SDA0
0
—
ns
At reception
Data setup
time
tSU;DAT
SCL0,
SDA0
tMCLK − 20
—
ns
At reception
SDA↓→
SCL↑
(at wakeup
function)
tWAKEUP
SCL0,
SDA0
Oscillation
stabilization wait
time + 2 tMCLK − 20
—
ns
Restart
condition
detection
condition
(Continued)
DS07-12628-2E
63
MB95310L/370L Series
(Continued)
*1: R represents the pull-up resistor of the SCL0 and SDA0 lines, and C the load capacitor of the SCL0 and
SDA0 lines.
*2: •
•
•
•
See “(2) Source Clock/Machine Clock” for tMCLK.
m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0).
n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0).
The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the
CS4 to CS0 bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22)
: 0.9 MHz < tMCLK ≤ 10 MHz
(m, n) = (8, 22)
: 0.9 MHz < tMCLK ≤ 16.25 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
(m, n) = (5, 8)
: 3.3 MHz < tMCLK ≤ 16.25 MHz
64
DS07-12628-2E
MB95310L/370L Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Value
Unit
Min
Typ
Max
Resolution
—
—
10
bit
Total error
−3
—
+3
LSB
−2.5
—
+2.5
LSB
−1.9
—
+1.9
LSB
Linearity error
—
Differential linear
error
Zero transition
voltage
VOT
Full-scale transition
voltage
VFST
Compare time
Sampling time
—
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
V
2.7 V ≤ VCC ≤ 3.6 V
AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB
V
1.8 V ≤ VCC < 2.7 V
AVCC − 3.5 LSB AVCC − 1.5 LSB AVCC + 0.5 LSB
V
2.7 V ≤ VCC ≤ 3.6 V
AVCC − 2.5 LSB AVCC − 0.5 LSB AVCC + 1.5 LSB
V
1.8 V ≤ VCC < 2.7 V
0.6
—
140
µs 2.7 V ≤ VCC ≤ 3.6 V
20
—
140
µs 1.8 V ≤ VCC < 2.7 V
0.4
—
∞
2.7 V ≤ VCC ≤ 3.6 V, with
µs external impedance
< 1.8 kΩ
30
—
∞
1.8 V ≤ VCC < 2.7 V, with
µs external impedance
< 14.8 kΩ
—
Analog input current
IAIN
−0.3
—
+0.3
µA
Analog input voltage
VAIN
AVSS
—
AVCC
V
DS07-12628-2E
Remarks
65
MB95310L/370L Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision
standard, considering the relationship between the external impedance and minimum sampling time, either
adjust the register value and operating frequency or decrease the external impedance so that the sampling
time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
2.7 V ≤ VCC ≤ 3.6V
1.7 kΩ (Max)
14.5 pF (Max)
1.8 V ≤ VCC < 2.7 V
8.4 kΩ (Max)
25.2 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
[External impedance = 0 kΩ to 100 kΩ]
20
90
External impedance [kΩ]
External impedance [kΩ]
100
(VCC ≥ 2.7 V)
80
70
60
50
40
30
(VCC ≥ 1.8 V)
20
10
18
16
14
12
(VCC ≥ 2.7 V)
10
8
6
4
2
0
0
0
5
10
15
20
25
30
Minimum sampling time [μs]
35
0
1
2
3
4
Minimum sampling time [μs]
• A/D conversion error
As |VCC−VSS| decreases, the A/D conversion error increases proportionately.
66
DS07-12628-2E
MB95310L/370L Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an
ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
2 LSB
3FDH
Digital output
Digital output
3FDH
004H
003H
Actual conversion
characteristic
3FEH
3FEH
VOT
{1 LSB × (N-1) + 0.5 LSB}
004H
VNT
003H
1 LSB
002H
002H
001H
Actual conversion
characteristic
Ideal characteristic
001H
0.5 LSB
VSS
Analog input
1 LSB =
VCC - VSS
(V)
1024
N
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
DS07-12628-2E
67
MB95310L/370L Series
(Continued)
Zero transition error
Full-scale transition error
004H
Ideal characteristic
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
002H
Digital output
Digital output
003H
Actual conversion
characteristic
Ideal
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
VOT (measurement value)
VSS
Analog input
VCC
VSS
3FEH
Ideal characteristic
Actual conversion
characteristic
(N+1)H
Actual conversion
characteristic
{1 LSB × N + VOT}
VFST
(measurement
value)
VNT
004H
002H
Digital output
Digital output
3FDH
V(N+1)T
NH
VNT
(N-1)H
Actual conversion
characteristic
003H
VCC
Differential linearity error
Linearity error
3FFH
Analog input
Ideal
characteristic
Actual conversion
characteristic
(N-2)H
001H
VOT (measurement value)
VSS
Analog input
VCC
VNT - {1 LSB × N + VOT}
Linearity error
=
of digital output N
1 LSB
N
VSS
Analog input
VCC
V(N+1)T - VNT
Differential linear error
=
- 1
of digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
68
DS07-12628-2E
MB95310L/370L Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.2*1
0.5*2
s
The time of programming 00H prior
to erasure is excluded.
Sector erase time
(16 Kbyte sector)
—
0.5*1
7.5*2
s
The time of programming 00H prior
to erasure is excluded.
Byte programming time
—
21
6100*2
µs
System-level overhead is excluded.
100000
—
—
cycle
Power supply voltage at
program/erase
2.7
3.0
3.6
V
Flash memory data retention
time
20*3
—
—
Program/erase cycle
year Average TA = +85°C
*1: TA = +25°C, VCC = 3.0 V, 100000 cycles
*2: TA = +85°C, VCC = 2.7 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from
the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being +85°C).
DS07-12628-2E
69
MB95310L/370L Series
■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics
ICC − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC − TA
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
25
25
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
20
FMP = 16 MHz
FMP = 10 MHz
20
15
ICC[mA]
ICC[mA]
15
10
10
5
5
0
−50
0
1
2
3
4
5
0
ICCS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
+150
20
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
FMP = 16 MHz
FMP = 10 MHz
15
ICCS[mA]
15
ICCS[mA]
+100
ICCS − TA
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
20
10
10
5
5
0
−50
0
1
2
3
4
5
0
+50
+100
+150
TA[°C]
VCC[V]
ICCL − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL − TA
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
40
100
30
75
ICCL[μA]
ICCL[μA]
+50
TA[°C]
VCC[V]
20
50
25
10
0
1
2
3
VCC[V]
4
5
0
−50
0
+50
+100
+150
TA[°C]
(Continued)
70
DS07-12628-2E
MB95310L/370L Series
ICCLS − TA
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
100
100
75
75
ICCLS[μA]
ICCLS[μA]
ICCLS − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
50
50
25
25
0
−50
0
1
2
3
4
5
0
+100
+150
ICCT − TA
VCC = 3.0 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
100
100
75
75
ICCT[μA]
ICCT[μA]
ICCT − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
50
50
25
25
0
−50
0
1
2
3
4
5
0
+50
+100
+150
TA[°C]
VCC[V]
ICTS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock operating
ICTS − TA
VCC = 3.0 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock operating
10
10
FMP = 16 MHz
FMP = 10 MHz
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
8
8
6
ICTS[mA]
ICTS[mA]
+50
TA[°C]
VCC[V]
6
4
4
2
2
0
1
2
3
VCC[V]
4
5
0
−50
0
+50
+100
+150
TA[°C]
(Continued)
DS07-12628-2E
71
MB95310L/370L Series
(Continued)
ICCH − TA
VCC = 3.0 V, FMPL = (stop)
Substop mode with the external clock stopping
+10
+10
+8
+8
+6
+6
ICCH[μA]
ICCH[μA]
ICCH − VCC
TA = +25°C, FMPL = (stop)
Substop mode with the external clock stopping
+4
+4
+2
+2
0
0
−2
−2
1
2
3
4
−50
5
0
VCC[V]
ICCMCR − VCC
TA = +25°C, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
FMP = 12.5 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 1 MHz
15
15
ICCMCR[mA]
ICCMCR[mA]
+150
20
FMP = 12.5 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 1 MHz
10
5
10
5
0
0
1
2
3
4
−50
5
0
VCC[V]
+50
+100
+150
TA[°C]
ICCSCR − VCC
TA = +25°C, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
ICCSCR − TA
VCC = 3.0 V, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
160
160
140
140
120
120
100
100
ICCSCR[μA]
ICCSCR[μA]
+100
ICCMCR − TA
VCC = 3.0 V, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
20
80
80
60
60
40
40
20
20
0
0
1
2
3
VCC[V]
72
+50
TA[°C]
4
5
−50
0
+50
+100
+150
TA[°C]
DS07-12628-2E
MB95310L/370L Series
• Input voltage characteristics
VIHI1 − VCC and VIL − VCC
TA = +25°C
VIHI2 − VCC and VIL − VCC
TA = +25°C
4
4
VIHI1
VIL
VIHI2
VIL
3
VIHI2/VIL[V]
VIHI1/VIL[V]
3
2
2
1
1
0
0
1
2
3
4
5
1
2
VCC[V]
3
4
VIHS1 − VCC and VILS − VCC
TA = +25°C
VIHS2 − VCC and VILS − VCC
TA = +25°C
4
4
VIHS1
VILS
VIHS2
VILS
3
VIHS2/VILS[V]
3
VIHS1/VILS[V]
5
VCC[V]
2
2
1
1
0
0
1
2
3
4
5
1
2
VCC[V]
3
4
5
VCC[V]
VIHM − VCC and VILM − VCC
TA = +25°C
4
VIHM
VILM
VIHM/VILM[V]
3
2
1
0
1
2
3
4
5
VCC[V]
DS07-12628-2E
73
MB95310L/370L Series
• Output voltage characteristics
VOL − IOL
TA = +25°C
1.0
1.0
0.8
0.8
0.6
0.6
VOL[V]
VCC − VOH[V]
(VCC − VOH) − IOH
TA = +25°C
0.4
0.4
0.2
0.2
0.0
0.0
0
−2
−6
−4
IOH[mA]
VCC = 1.8 V
VCC = 2.0 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
74
−8
−10
0
2
6
4
8
10
IOL[mA]
VCC = 1.8 V
VCC = 2.0 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
DS07-12628-2E
MB95310L/370L Series
• Pull-up characteristics
RPULL − VCC
TA = +25°C
250
RPULL[kΩ]
200
150
100
50
0
1
2
3
4
5
VCC[V]
DS07-12628-2E
75
MB95310L/370L Series
■ MASK OPTIONS
Part Number
No.
MB95F314E
MB95F316E
MB95F318E
MB95F374E
MB95F376E
MB95F378E
Selectable/Fixed
1
76
Low-voltage detection reset With low-voltage detection reset
MB95F314L
MB95F316L
MB95F318L
MB95F374L
MB95F376L
MB95F378L
Fixed
Without low-voltage detection reset
DS07-12628-2E
MB95310L/370L Series
■ ORDERING INFORMATION
Part Number
Package
MB95F314EPMC-G-SNE2
MB95F314LPMC-G-SNE2
MB95F316EPMC-G-SNE2
MB95F316LPMC-G-SNE2
MB95F318EPMC-G-SNE2
MB95F318LPMC-G-SNE2
80-pin plastic LQFP
(FPT-80P-M37)
MB95F374EPMC1-G-SNE2
MB95F374LPMC1-G-SNE2
MB95F376EPMC1-G-SNE2
MB95F376LPMC1-G-SNE2
MB95F378EPMC1-G-SNE2
MB95F378LPMC1-G-SNE2
64-pin plastic LQFP
(FPT-64P-M38)
MB95F374EPMC2-G-SNE2
MB95F374LPMC2-G-SNE2
MB95F376EPMC2-G-SNE2
MB95F376LPMC2-G-SNE2
MB95F378EPMC2-G-SNE2
MB95F378LPMC2-G-SNE2
64-pin plastic LQFP
(FPT-64P-M39)
DS07-12628-2E
77
MB95310L/370L Series
■ PACKAGE DIMENSION
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
0.145±0.055
(.006±.002)
*12.00±0.10(.472±.004)SQ
60
41
Details of "A" part
61
40
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
0.08(.003)
INDEX
80
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
21
"A"
1
20
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
M
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
78
DS07-12628-2E
MB95310L/370L Series
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.00 mm × 10.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
0.145±0.055
(.006±.002)
*10.00±0.10(.394±.004)SQ
48
33
49
Details of "A" part
32
+0.20
0.08(.003)
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
INDEX
64
17
1
0.22±0.05
(.009±.002)
0.10±0.10
(.004±.004)
(Stand off)
"A"
16
0.50(.020)
C
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.08(.003)
M
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-12628-2E
79
MB95310L/370L Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.006±.002)
33
Details of "A" part
49
32
+0.20
1.50 –0.10
+.008
.059 –.004
0.10(.004)
INDEX
0.50±0.20
(.020±.008)
64
17
1
C
0.32±0.05
(.013±.002)
0.10±0.10
(.004±.004)
0.25(.010)BSC
0.60±0.15
(.024±.006)
16
0.65(.026)
0~8˚
"A"
0.13(.005)
M
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
80
DS07-12628-2E
MB95310L/370L Series
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
1
—
Details
Changed the family name.
F2MC-8FX → New 8FX
1
■ FEATURES
Changed the main CR clock oscillation frequency.
1/8/10 MHz ±3%, maximum machine clock frequency:
10 MHz
→
1/8/10/12.5 MHz ±2%, maximum machine clock
frequency: 12.5 MHz
23
■ PIN CONNECTION
Added “• Notes on handling the external clock pins while
using the CR clock”.
46
■ ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Changed the condition for the power supply current
(ICCMCR).
FCRH = 10 MHz
FMP = 10 MHz
Main CR clock mode
→
FCRH = 12.5 MHz
FMP = 12.5 MHz
Main CR clock mode
Changed the condition for the power supply current
(ICCSCR).
FCL = 32 kHz
FMPL = 16 kHz
Sub-CR clock mode
(divided by 2)
TA = +25°C
→
Sub-CR clock mode
(divided by 2)
TA = +25°C
47
Changed the condition for the power supply current (ICRH).
Current consumption for the main CR oscillator at 10 MHz
→
Current consumption for the main CR oscillator
48
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1) Clock Timing
Changed the values of the clock frequency (FCRH).
58
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(7) Low-voltage Detection
Deleted the following parameters:
Power hysteresis width 0, Power hysteresis width 1,
Power hysteresis width 2, Interrupt hysteresis width 0,
Interrupt hysteresis width 1, Interrupt hysteresis width 2,
Interrupt hysteresis width 3, Interrupt hysteresis width 4
Deleted VPHYS/VIHYS from the diagram.
59
64
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(8) I2C Timing
70 to 75 ■ SAMPLE CHARACTERISTICS
DS07-12628-2E
Changed the settings related to the machine clock shown
in *2.
Added “■ SAMPLE CHARACTERISTICS”.
81
MB95310L/370L Series
MEMO
82
DS07-12628-2E
MB95310L/370L Series
MEMO
DS07-12628-2E
83
MB95310L/370L Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department