GSI GS820V32Q

GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
Features
• Single 3.3V +5%/-5% power supply
• Separate VDDQ to allow 2.375V to 3.465V output supply level
• High frequency operation: 117MHz
• Fast access time: 4.5ns Clock to Q
• Low power: 0.5mA ISB and IDD static
• FT mode pin for either flow-thru or pipeline operation
• LBO mode pin for linear or interleave (PentiumTM and X86)
burst mode
• Byte write (BWE) and global write (GW) operation
• 3 chip enable signals for easy depth expansion
• 2 cycles enable (pipeline mode) and 1 cycle disable to allow multiple
bank without data buss contention
• Compatible to both 3.3V and 2.5V interface level
• Standard Industrial Temperature Option: -40 to +85C
• JEDEC standard 100 lead package:
Q: QFP
T: TQFP
Pentium is a trademark of Intel Corp.
Functional Description
The GS820V32 is a 64Kx32 high performance synchronous SRAM
with 2 bit burst counter. It is designed to provide L2 Cache for PentiumTM and other high performance CPU. Addresses (A0-15), data
IOs (DQ1-32), chip enables (CE1, CE2, CE3), address control inputs
(ADSP, ADSC, ADV) and write control inputs (BW1, BW2, BW3,
BW4, BWE, GW) are synchronous and are controlled by a positive
edge triggered clock (CLK).
Pin configuration
A6
A7
CE1
CE2
BW4
BW3
BW2
BW1
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Top view
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
80
1
DQ16
79
2
DQ15
78
3
VDDQ
77
4
VSSQ
76
5
DQ14
75
6
DQ13
74
7
DQ12
73
8
DQ11
72
9
71
10
VSSQ
70
11
VDDQ
69
12
DQ10
68
13
DQ9
67
14
VSS
66
15
NC
65
VDD
16
64
ZZ
17
63
DQ8
18
DQ7
62
19
61
20
VDDQ
60
21
VSSQ
59
22
DQ6
58
23
DQ5
57
24
DQ4
56
25
DQ3
55
VSSQ
26
54
VDDQ
27
53
DQ2
28
52
DQ1
29
51
NC
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 pin QFP / TQFP
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
NC
NC
DQ17
DQ18
VDDQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VDDQ
DQ23
DQ24
FT
VDD
NC
VSS
DQ25
DQ26
VDDQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VDDQ
DQ31
DQ32
NC
Rev. 9/09/97
1/15
80-133MHz (P/L)
66MHz Flow-Thru
Output enable (OE) and power down control (ZZ) are asynchronous. 2 mode control pins (LBO & FT) define 4 operation modes
of linear/interleave burst order and output flow-thru/pipeline.
Burst can be initiated with either ADSP or ADSC inputs. Subsequent burst address are generated internally and are controlled by
ADV. The burst sequence is either interleave order (PentiumTM
and X86) or linear order and is defined by LBO.
Output registers are provided and are controlled by FT mode pin.
With FT mode pin, Output registers can be programmed in either
pipeline mode for very high frequency operation (117MHz) or
flow-thru mode for reduced latency.
Byte write operation can be obtained through byte write enable
(BWE) input combined with 4 individual byte write signals
BW1-4. In addition, global write (GW) signal is also available to
write all bytes at once.
Low power state (standby mode) can be obtained either through
the assertion of ZZ signal or simply stop the clock (CLK). In
standby mode, memory data are still retained. Low power design
of 0.5mA standby are provided on L version.
The GS820V32 operates from a 3.3V power supply and all
inputs and outputs are LVTTL compatible. Separate output
power (VDDQ) and ground (VSSQ) pins are employed to decouple output noise from internal circuit and VDDQ allow user
the flexibility to employ lower output supply level like 2.5V.
GS820V32’s interface level is also compatble to 2.5V supply
level.
The GS820V32 is implemented with GSI’s high performance
CMOS technology and is available in JEDEC standard 100 lead
QFP ( Q version ) and TQFP ( T version) package.
A0-15
Address Inputs
CLK
Clock Input
BWE
Byte Write Enable
BW1,BW2
BW3,BW4
Byte Write. BW1 for DQ1-8; BW2 for DQ9-16;
BW3 for DQ17-24; BW4 for DQ25-32
GW
Global Write Enable
CE1,CE2, CE3
Chip Enable
OE
Output Enable
ADV
Burst Address advance
ADSP, ADSC
Address Status
DQ1-32
Data I/O
ZZ
Power down control
FT
Flow-Thru mode
LBO
Linear Burst mode
VDD
3.3V Power Supply
VSS
Ground
VDDQ
Output Power
(3.465Vmax)
VSSQ
Output Ground
NC
No Connect
Supply,
2.375V
to
VDD
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Functional Block Diagram
16
A0-15
Register
D
Q
A0
A0
D0
A1
Q0
A1
Binary
D1
Counter
16
Q1
A
Load
LBO
64Kx32
Memory
Array
ADV
CLK
ADSC
ADSP
Q
D
Register
D
Q
GW
BWE
BW1
Register
D
Q
32
BW2
32
4
Register
D
Q
BW3
Register
Q
D
Register
Q
D
Register
D
Q
BW4
Register
D
Q
Register
D
Q
CE1
CE2
CE3
Register
D
Q
FT
OE
ZZ
32
Powerdown
DQ1-32
Control
Rev. 9/09/97
2/15
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Mode pin function
LBO
Function
FT
Function
L
Linear Burst
L
Flow-Thru
H or NC
Interleaved Burst
H or NC
Pipeline
Power down control
ZZ
Function
L or NC
Active
H
Standby
IDD=ISB
Note: There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and
the chip will operate in the default states as specified in the above tables.
Linear Burst sequence
Interleaved Burst sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
The burst wrap around to initial state upon completion
The burst wrap around to initial state upon completion
Byte Write Function
Function
SGW BWE BW1 BW2 BW3 BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all bytes
L
X
X
X
X
X
Write all bytes
H
L
L
L
L
L
Write byte 1
H
L
L
H
H
H
Write byte 2
H
L
H
L
H
H
Write byte 3
H
L
H
H
L
H
Write byte 4
H
L
H
H
H
L
Note: H=logic high, L=logic low, NC= no connect
Rev. 9/09/97
3/15
GSI TECHNOLOGY
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
GS820V32Q/T
64K x 32 Burst
80-133MHz (P/L)
66MHz Flow-Thru
Synchronous truth table
Cycle
Note:
Address used CE1
CE2
CE3 ADSP ADSC ADV BWx
Deselect
none
H
X
X
X
L
X
X
Deselect
none
L
L
X
X
L
X
X
Deselect
none
L
X
H
X
L
X
X
Deselect
none
L
L
X
L
X
X
X
Deselect
none
L
X
H
L
X
X
X
Read, begin burst
external
L
H
L
L
X
X
X
Read, begin burst
external
L
H
L
H
L
X
H
Read, continue burst
next
X
X
X
H
H
L
H
Read, continue burst
next
H
X
X
X
H
L
H
Read, suspend burst
current
X
X
X
H
H
H
H
Read, suspend burst
current
H
X
X
X
H
H
H
Write, begin burst
external
L
H
L
H
L
X
L
Write, continue burst
next
X
X
X
H
H
L
L
Write, continue burst
next
H
X
X
X
H
L
L
Write, suspend burst
current
X
X
X
H
H
H
L
Write, suspend burst
current
H
X
X
X
H
H
L
1. X=don’t care, H=logic high, L=logic low
2. BWx is the logic function of GW, BWE, BW1, BW2, BW3, BW4. See Byte Write Function table for detail.
3. All inputs in the table must meet setup and hold on rising edge of CLK.
DQ Bus Control and Asynchronous OE
Cycle
OE
DQ
Read
L
Q
Read
H
Hi-Z
Write
X
Hi-Z; D
Deselect
X
Hi-Z
Note: On the write cycle that follows read cycle, OE need to be held high prior to the start of write cycle to tri-state DQ buss and allow data
input to SRAM.
Rev. 9/09/97
4/15
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Absolute Maximum Ratings (Voltage reference to VSS=0V)
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
-0.5 to 4.6
V
Output Supply Voltage
VDDQ
-0.5 to VDD
V
CLK Input Voltage
VCLK
-0.5 to 6
V
Input Voltage
VIN
-0.5 to VDD+0.5
(≤ 4.6 V max. )
V
Output Voltage
VOUT
-0.5 to VDD+0.5
(≤ 4.6 V max. )
V
Power Dissipation
PD
1.5
W
Operating Temperature
Topr
0 to 70
oC
Storage Temperature
Tstg
-55 to 150
oC
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods
of time could affect device reliability.
Recommended Operating Conditions (Voltage reference to VSS=0V)
(VDD=3.135V to 3.465V, Ta=0 70C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
VDD
3.135
3.3
3.465
V
Output Supply Voltage
VDDQ
2.375
3.3
3.465
V
Input High Voltage
VIH
1.7
---
VDD+0.3
V
Input Low Voltage
VIL
-0.3
---
0.8
V
Note: Input overshoot voltage should be less than VDD+2V and not exceed 5ns.
Input undershoot voltage should be higher than -2V and not exceed 5ns.
Capacitance ( Ta=25C, f=1MHz)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN=0V
4
5
pF
Output Capacitance
COUT
VOUT=0V
6
7
pF
Note: These parameters are sampled and are not 100% tested.
Rev. 9/09/97
5/15
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
DC Characteristics (Voltage reference to VSS=0V)
(VDD=3.135V to 3.465V, Ta=0 to 70C)
(TA= -40 to +85C for Industrial Temperature Offering)
133MHz
Parameter
Symbol
Input Leakage Current
(except ZZ, FT, LBO pins)
IIL
-4
-5
-6
Test Conditions
Min
Max
Min
Max
Min
Max
Min
Max
VIN = 0 to VDD
-1uA
1uA
-1uA
1uA
-1uA
1uA
-1uA
1uA
ZZ Input Current
IINZZ
VDD ≥ VIN ≥ VIH
0V ≤ VIN ≤ VIH
-1uA
-1uA
1uA
300uA
-1uA
-1uA
1uA
300uA
-1uA
-1uA
1uA
300uA
-1uA
-1uA
1uA
300uA
Mode Input Current
(FT & LBO pins)
IINM
VDD ≥ VIN ≥ VIH
0V ≤ VIN ≤ VIH
-300uA
-1uA
1uA
1uA
-300uA
-1uA
1uA
1uA
-300uA
-1uA
1uA
1uA
-300uA
-1uA
1uA
1uA
Output Leakage Current
IOL
Output Disable,
VOUT = 0 to VDD
-1uA
1uA
-1uA
1uA
-1uA
1uA
-1uA
1uA
Output High Voltage
VOH
IOH = - 8mA
2.4V
Output Low Voltage
VOL
IOL = + 8mA
2.4
0.4V
Symbol
2.4V
0.4V
133MHz
Parameter
2.4V
0.4V
-4
0.4V
-5
-6
Test Conditions
Device Selected;
All other inputs ≥ VIH or ≤ VIL
Output open
0 to
70C
-40 to
+85C
240mA
245mA
0 to
70C
-40 to
+85C
0 to
70C
-40 to
+85C
0 to
70C
-40 to
+85C
185mA
150mA
155mA
Operating Supply Current
(VDD = man, E = VIH)
IDD
Standby Current
ISB
ZZ ≥ VDD - 0.2V
2mA
7mA
2mA
7mA
2mA
7mA
2mA
7mA
Deselect Supply Current
IDD
Device Selected;
All other inputs ≥ VIH or ≤ VIL
80mA
85mA
70mA
75mA
60mA
65mA
50mA
55mA
210mA 215mA 180mA
AC Test Conditions
Output load 1
(VDD=3.135V to 3.465V, Ta=0 to 70C)
Note:
DQ
Parameter
Conditions
Input high level
VIH=2.4V
Input low level
VIL=0.4V
Input rise time
tr=1V/ns
Input fall time
tf=1V/ns
Input reference level
1.4V
Output reference level
1.4V
Output load
Fig. 1& 2
50Ω 30pF1
VT=1.4V
Fig. 1
Output load 2
3.3V
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in
Fig. 1 unless otherwise noted
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
Rev. 9/09/97
295Ω
DQ
6/15
5pF1
Fig. 2
217Ω
GSI TECHNOLOGY
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
Rev. 9/09/97
GS820V32Q/T
64K x 32 Burst
7/15
80-133MHz (P/L)
66MHz Flow-Thru
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
AC Electrical Characteristics
(VDD=3.135V to 3.465V, Ta=0 to 70oC)
-4
Parameter
Clock to output valid
-5
-6
Min Max Min Max Min Max
Unit
tKQ
---
4.5
---
5
---
6
ns
tKQX
2
---
2
---
2
---
ns
tLZ2
2
---
2
---
2
---
ns
Clock cycle time
tKC
8.5
---
10
---
12.5
---
ns
Clock to output valid
tKQ
---
12
tKQX
3
---
tLZ2
3
---
ns
Clock cycle time
tKC
15
---
ns
Clock high time
tKH
2
---
3
---
4
---
ns
Clock low time
tKL
2
---
3
---
4
---
ns
Clock to output in Hi-Z
tHZ2
---
4
---
5
---
6
ns
OE to output valid
tOE
---
4
---
5
---
6
ns
OE to output in Low-Z
tOLZ2
0
---
0
---
0
---
ns
OE to output in Hi-Z
tOHZ2
---
4
---
5
---
6
ns
Setup time
tS
2.0
---
2.5
---
2.5
---
ns
Hold time
tH
0.5
---
0.5
---
0.5
---
ns
ZZ setup time
tZZS3
5
---
5
---
5
---
ns
ZZ hold time
tZZH3
1
---
1
---
1
---
ns
ZZ recovery
tZZR
20
---
20
---
20
---
ns
Pipeline Clock to output invalid
Clock to output in Low-Z
Flow-Thru Clock to output invalid
Clock to output in Low-Z
Note:
Symbol
ns
ns
NA1
1. Flow-Thru mode is available in -4 bin only
2. These parameters are sampled and are not 100% tested
3. ZZ is a asynchronous signal. However, in order to be recognized on any given clock cycle, the signal must meet specified setup
and hold time.
Rev. 9/09/97
8/15
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Read Cycle Timing (Pipeline)
Single Read
CLK
Burst Read
tS tH
tKH
ADSP
tKC
tKL
ADSP is blocked by CE1 inactive
tS tH
ADSC
ADSC initiated read
tS tH
Suspend Burst
ADV
tS tH
A0-A15
RD1
RD3
RD2
tS
tH
GW
tS
tH
BWE
BW1 BW4
tS tH
CE1 masks ADSP
CE1
tS tH
CE2 and CE3 only sampled with ADSP or ADSC
Deselected with CE2
CE2
tS tH
CE3
tOE
OE
DQ1DQ32
Hi-Z
tOHZ
tOLZ
Q1a
tKQX
tKQX
Q2a
Q2b
Q2c
Q2d
Q3a
tLZ
tHZ
tKQ
Rev. 9/09/97
9/15
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Write Cycle Timing
(This waveform can apply to both Pipeline and Flow-Thru modes)
Burst Write
Single Write
Deselected
Write
CLK
tS tH
tKH
tKL
ADSP is blocked by CE1 inactive
tKC
ADSP
tS tH
ADSC initiated write
ADSC
tS tH
ADV
tS tH
A0-A15
ADV must be inactive for ADSP Write
WR2
WR1
WR3
tS tH
GW
tS tH
BWE
tS tH
BW1 BW4
WR1
WR1
WR2
WR3
WR3
tS tH
CE1 masks ADSP
CE1
tS tH
Deselected with CE2
CE2
tS tH
CE2 and CE3 only sampled with ADSP or ADSC
CE3
OE
tS tH
DQ1DQ32
Rev. 9/09/97
Hi-Z
D1a
Write specified byte for 2a and all bytes for 2b, 2c& 2d
D2a
D2b
10/15
D2c
D2d
D3a
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Read/Write Cycle Timing (Pipeline)
Burst Read
Single Write
Single Read
CLK
tS tH
tKC
tKH tKL
ADSP is blocked by CE1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-A15
RD2
WR1
RD1
tS tH
GW
tS
tH
BWE
tS tH
BW1 BW4
WR1
tS tH
CE1 masks ADSP
CE1
tS tH
CE2 and CE3 only sampled with ADSP and ADSC
CE2
tS tH
Deselected with CE3
CE3
tOE
tOHZ
OE
tS tH
tKQ
DQ1DQ32
Rev. 9/09/97
Hi-Z
Q1a
D1a
11/15
Q2a
Q2b
Q2c
Q2d
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Read Cycle Timing (Flow-Thru)
Burst Read
Single Read
CLK
tS tH
tKH
ADSP
tKC
tKL
ADSP is blocked by CE1 inactive
tS tH
ADSC
ADSC initiated read
tS tH
Suspend Burst
Suspend Burst
ADV
tS tH
A0-A15
RD1
RD2
RD3
tS
tH
GW
tS
tH
BWE
BW1 BW4
tS tH
CE1 masks ADSP
CE1
tS tH
CE2 and CE3 only sampled with ADSP or ADSC
Deselected with CE2
CE2
tS tH
CE3
tOE
OE
DQ1DQ32
tOHZ
Hi-Z
tOLZ
Q1a
tKQX
Q2a
tKQX
Q2b
Q2d
Q3a
tHZ
tKQ
Rev. 9/09/97
Q2c
tLZ
12/15
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Read/Write Cycle Timing (Flow-Thru)
Burst Read
Single Write
Single Read
CLK
tS tH
tKC
tKH tKL
ADSP is blocked by CE1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-A15
RD2
WR1
RD1
tS tH
GW
tS
tH
BWE
tS tH
BW1 BW4
WR1
tS tH
CE1 masks ADSP
CE1
tS tH
CE2 and CE3 only sampled with ADSP and ADSC
CE2
tS tH
Deselected with CE3
CE3
tOE
tOHZ
OE
tKQ
DQ1DQ32
Hi-Z
tS tH
Q1a
D1a
Q2a
Q2b
Q2c
Q2d
Burst wrap around to it’s initial state
Rev. 9/09/97
13/15
Q2a
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
CLK
tS tH
ADSP
ADSC
ZZ
tKC
tKH tKL
~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~
ZZ Timing
tZZS Snooze tZZH
Rev. 9/09/97
14/15
tZZR
GSI TECHNOLOGY
GS820V32Q/T
64K x 32 Burst
GS820V32Q/T
4/5/6, 2.5V I/O, 2.0mA
80-133MHz (P/L)
66MHz Flow-Thru
Package Dimension
L
θ
c
Pin 1
L1
D
D1
e
b
A1
A2
E1
Y
Symbol
A1
A2
b
c
D
D1
E
E1
e
L
L1
Y
θ
Description
Stand Off
Body Thickness
Lead Width
Lead Thickness
Terminal Dimension
Package Body
Terminal Dimension
Package Body
Lead Pitch
Foot Length
Lead Length
Coplanarity
Lead Angle
E
Min.
0.25
2.55
0.20
0.10
22.95
19.9
17.0
13.9
0.60
0o
Note:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev. 9/09/97
15/15
QFP (Q)
Nom.
0.35
2.72
0.30
0.15
23.2
20.0
17.2
14.0
0.65
0.80
1.60
Max
0.45
2.90
0.40
0.20
23.45
20.1
17.4
14.1
Min.
0.05
1.35
0.20
0.09
21.9
19.9
15.9
13.9
1.00
0.45
0.10
7o
0o
TQFP (T)
Nom.
0.10
1.40
0.30
22.0
20.0
16.0
14.0
0.65
0.60
1.00
Max
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
0.75
0.10
7o