CXK77V3211Q -12/14 32768-word by 32-bit High Speed Synchronous Static RAM For the availability of this product, please contact the sales office. Description The CXK77V3211Q is a 32K × 32 high performance synchronous SRAM with a 2-bit burst counter and output register. All synchronous inputs pass through register controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2), burst control inputs (ADSC, ADSP, ADV), four individual byte write enables (BW1, BW2, BW3, BW4), one byte write enable (BWE), and global write enable (SGW). Asynchronous inputs include the output enable (OE) and power down control (ZZ). Two mode control pins (LBO, FT) define four different operation modes: Linear/Interleaved burst sequence and Flow-Thru/Pipelined operations. WRITE cycles can be from one to four bytes wide as controlled by BW1 through BW4 and BWE or SGW. The output register is included on-chip and controlled by clock, it can be activated by connecting FT to high for high speed pipeline operation. Burst operation can be initiated with either address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV). Burst order sequence can be controlled by connecting LBO to high for Interleaved burst order (i486/Pentium™) or by connecting LBO to low for Linear burst order. Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. WRITE pass through makes written data immediately available at the output register during READ cycle following a WRITE as controlled by OE. The CXK77V3211Q operates from a +3.3V power supply and all inputs and outputs are LVTTL compatible. The device is ideally suited for i486 and Pentium™ systems and those systems which benefit from a very wide data bus. 100 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • Fast address access times and High frequency operation Symbol Flow-through Pipeline Access Cycle Access Cycle -12 12ns 60MHz 7ns 75MHz -14 14ns 50MHz 8ns 66MHz • 5V tolerant inputs except I/O pins • A FT pin for pipelined or flow-thru architecture • A LBO mode pin as burst control pin (i486/Pentium™ and Linear burst sequence) • Single +3.3V +10% – 5% power supply • Common data inputs and data outputs • All inputs and outputs are LVTTL compatible • Four Individual BYTE WRITE enables, GLOBAL WRITE and BYTE WRITE ENABLE • Three Chip Enables for simple depth expansion • One cycle output disable for both pipelined and flow-thru operation • Internal input registers for address, data and control signals • Self-timed WRITE cycle • Write pass through capability • High 30pF output drive capability at rated access time • A ZZ pin for powerdown • 100-lead QFP package for high density, high speed operation i486/Pentium is a trademark of Intel Corp. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95721-PS –2– ZZ FT OE CE CE2 CE2 BW1 BW2 BW3 SGW BWE BW4 ADSP ADSC ADV CLK LBO A0 to A14 Block Diagram 15 Enable Register Byte 1 Write Register Byte 2 Write Register Byte 3 Write Register Byte 4 Write Register Address Register A0 A1 Load q0 Counter q1 0 1 Mux A0 0 1 Mux POWER DOWN A1 15 13 A0' A1' 8 8 8 8 32 8 Byte 1 Write Driver Byte 2 Write Driver 8 8 Byte 3 Write Driver 8 Byte 4 Write Driver 15 4 32 32 32 Input Registers 32K × 8 ×4 32 Sense 32 Output Output Memory Amps Registers Buffers Array DQ1 · · · DQ32 CXK77V3211Q CXK77V3211Q A9 A8 ADV ADSC ADSP OE BWE SGW CLK VSS CE2 VDD BW1 BW2 BW4 BW3 CE2 CE A7 A6 Pin Configuration 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC 1 80 NC DQ17 2 79 DQ16 DQ18 3 78 DQ15 VDDq 4 77 VDDq Vssq 5 76 Vssq DQ19 6 75 DQ14 DQ20 7 74 DQ13 DQ21 8 73 DQ12 DQ22 9 72 DQ11 Vssq 10 71 Vssq VDDq 11 70 VDDq DQ23 12 69 DQ10 DQ24 13 68 DQ9 FT 14 67 Vss VDD 15 66 NC NC 16 65 Vss 17 64 ZZ VDD DQ25 18 63 DQ8 DQ26 19 62 DQ7 VDDq 20 61 VDDq Vssq 21 60 Vssq DQ27 22 59 DQ6 DQ28 23 58 DQ5 DQ29 24 57 DQ4 DQ30 25 56 DQ3 Vssq 26 55 Vssq VDDq 27 54 VDDq DQ31 28 53 DQ2 DQ32 29 52 DQ1 NC 30 51 NC –3– NC NC A14 A13 A12 A11 A10 NC NC VDD Vss NC NC A0 A1 A3 A2 A4 A5 LBO 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXK77V3211Q Pin Description Symbol I/O Description I Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. BW1, BW2, BW3, BW4 I Synchronous Individual Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A BYTE WRITE enable is LOW for a WRITE cycle and HIGH for a READ cycle. BW1 controls DQ1 to DQ8. BW2 controls DQ9 to DQ16. BW3 controls DQ17 to DQ24. BW4 controls DQ25 to DQ32. Data I/O are tristated if any of these four inputs are LOW. CLK I Clock: This signal latches the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. CE I Synchronous Chip Enable: This active LOW input is used to enable the device and conditions internal use of ADSP. This input is sampled only when a new external address is loaded. CE2 I Synchronous Chip Enable: This active LOW input is used to enable the device. This input is sampled only when a new external address is loaded. This input can be used for memory depth expansion. CE2 I Synchronous Chip Enable: This active HIGH input is used to enable the device. This input is sampled only when a new external address is loaded. This input can be used for memory depth expansion. OE I Output Enable: This active LOW asynchronous input enables the data I/O output drivers. I Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait status to be generated (no address advance). This pin must be HIGH at the rising edge of the first clock after an ADSP cycle is initiated if a WRITE cycle is desired (to ensure use of correct address). I Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be latched. A READ is performed using the new address, independent of the byte write enables and ADSC but dependent upon CE2 and CE2. ADSP is ignored if CE is HIGH. Power down state is entered if CE2 is LOW or CE2 is HIGH. I Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst and causes a new external address to be latched. A READ or WRITE is performed using the new address if all chip enables are active. Powerdown state is entered if one or more chip enables are inactive. A0 to A14 ADV ADSP ADSC NC — No Connect: These signals are not internally connected. DQ1 to DQ32 I/O SRAM Data I/O: Byte 1 is DQ1 to DQ8; Byte 2 is DQ9 to DQ16; Byte 3 is DQ17 to DQ24; Byte 4 is DQ25 to DQ32. Input data must meet setup and hold times around the rising edge of CLK. BWE I Byte Write Enable: This active low input enables individual byte to write. SGW I Global Write: This active low input enables to write all bytes. FT I Flow Through: This active low input selects flow through output. LBO I Linear Burst: This active high input selects interleaved burst sequence. ZZ I ZZ: This active high input enables the device in powerdown mode. VDD Supply Power Supply: +3.3V +10% – 5% VSS Supply Ground: GND VDDq Supply Isolated Output Buffer Supply: +3.3V +10% – 5% VSSq Supply Isolated Output Buffer Ground: GND –4– CXK77V3211Q Interleaved Burst Sequence Table Address used Operation A14 to A2 A1 A0 First access, latch external address A14 to A2 A1 A0 Second access (first burst address) latched A14 to A2 latched A1 latched A0 Third access (second burst address) latched A14 to A2 latched A1 latched A0 Fourth access (third burst address) latched A14 to A2 latched A1 latched A0 Interleaved Burst Address Table First address Second address Third address Fourth address X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 Linear Burst Address Table First address Second address Third address Fourth address X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 Pass-Through Truth Table Previous cycle Present cycle Next cycle Operation BWs Operation CE BWs OE Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) All L Initial READ cycle Register A (n), Q = D (n – 1) L H L Read D (n) Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) All L No new cycle Q = D (n – 1) H H L No carryover from previous cycle Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) All L No new cycle Q = HIGH-Z H H H No carryover from previous cycle Initial WRITE cycle, one byte Address = A (n – 1), data = D (n – 1) One L No new cycle Q = D (n – 1) for one byte H H L No carryover from previous cycle Note) Previous cycle may be either BURST or NONBURST cycle. –5– Operation CXK77V3211Q Function LBO Linear burst L Interleaved burst H or NC Function FT Flow-thru output L or NC Pipelined output H Function ZZ Powerdown to ISB1 Active H L or NC Partial Truth Table Function SGW BWE BW1 BW2 BW3 BW4 READ H H X X X X READ H L H H H H WRITE byte 1 H L L H H H WRITE all bytes H L L L L L WRITE all bytes L X X X X X Absolute Maximum Rating Item (Ta = 25°C, GND = 0V) Symbol Rating Unit Supply voltage VDD –0.5 to +4.6 V Input voltage VIN –0.5 to 6 (Max.) V Power dissipation PD 1.6 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +150 °C Soldering temperature · time Tsolder 235 · 10 °C · sec DC Recommended Operating Conditions Item Symbol (Ta = 0 to +70°C, GND = 0V) Min. Typ. Max. Unit Note Supply voltage VDD 3.135 3.3 3.63 V 1 Input high voltage VIH 2.0 — 5.5 V 1, 2 Input low voltage VIL –0.3 — 0.8 V 1, 2 Note) 1. All voltage referenced to VSS (GND). 2. Overshoot: VIH ≤ VDD + 2.0V for t ≤ tKC/2. Undershoot: VIL ≥ –2.0V for t ≤ tKC/2. –6– CXK77V3211Q (VDD = 3.3V +10% – 5% , GND = 0V, Ta = 0 to +70°C) DC and Operating Characteristics Item Symbol Test condition Min. Max. Unit Input leakage current ILI VIN = GND to VDD –1 1 µA Output leakage current ILO Output disabled, VOUT = GND to VDD –1 1 µA IDD-0MHz IDD-66MHz IDD-80MHz Device selected; all inputs ≤ VIL or ≥ VIH; cycle time ≥ tKC min, VDD = MAX; outputs open — 20 210 250 mA Static CMOS supply current IDD1-0MHz All inputs ≤ 0.2V or ≥ VDD – 0.2V — 20 mA Standby current ISB1 ZZ ≥ VDD –0.2V, All inputs ≤ 0.2V or ≥ VDD – 0.2V — 20 mA Deselect supply current ISB2-0MHz ISB2-66MHz ISB2-80MHz Device deselect — 20 120 140 mA Output High voltage VOH IOH = –5.0mA 2.4 — V Output Low voltage VOL IOL = 5.0mA — 0.4 V Operating supply current DC and Operating Characteristics for Special Modes-pins Mode-pins FT ZZ LBO VIN ILI ≥ VIH + 0.5V < VIH + 0.5V < 1µA > 10KΩ to VSS ≥ VIL < VIL < 1µA > 10KΩ to VDD These Mode-pin input buffers (FT, ZZ, LBO) have special self-bias circuit to protect against coupling noise when these pins are not connected during normal operations. –7– CXK77V3211Q (VDD = 3.3V +10% – 5% , Ta = 0 to +70°C) AC Electrical Characteristics -12 Item Symbol tKQ tKQX tLZ2 tKC tKQ tKQX tLZ2 tKC tKH tKL tHZ2 tOE tOLZ2 tOHZ2 tS tH tZZS3 tZZH3 tZZR Clock to output valid Flow-thru Clock to output invalid Clock to output in Low-Z Clock cycle time Clock to output valid Pipeline Clock to output invalid Clock to output in Low-Z Clock cycle time Clock HIGH time Clock LOW time Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup time Hold time ZZ setup ZZ hold ZZ recovery -14 Min. Max. Min. Max. Unit — 12 — 14 ns 3 — 3 — ns 3 — 3 — ns 16.6 — 20 — ns — 7 — 8 ns 2 — 2 — ns 2 — 2 — ns 13 — 15 — ns 3.5 — 4 — ns 3.5 — 4 — ns — 5 — 6 ns — 5 — 6 ns 0 — 0 — ns — 5 — 6 ns 2.5 — 2.5 — ns 0.5 — 0.5 — ns 5 — 5 — ns 1 — 1 — ns 20 — 20 — ns 1. All parameters are specified over the range 0 to 70°C. 2. These parameters are sampled and are not 100% tested. 3. Signal is asynchronous, however, to be recognized on any given clock the signal must meet specified setup and hold times. –8– CXK77V3211Q I/O capacitance (Ta = 25°C, f = 1MHz) Item Symbol Test condition Typ. Max. Unit Input capacitance CIN VIN = 0V 4 5 pF I/O capacitance COUT VI/O = 0V 6 7 pF This parameter is sampled and is not 100% tested. AC Test Conditions (VDD = 3.3V +10% – 5% , Ta = 0 to +70°C) Item Conditions Input pulse high level VIH = 2.8V Input pulse low level VIL = 0V Input rise time Input fall time tr = 1V/ns tf = 1V/ns Input reference level 1.4V Output reference level 1.4V Output load conditions Fig. 1 and Fig. 2 I/O Zo = 50Ω 50Ω VT = 1.4V Output load (1) Fig. 1. +3.3V ∗ Include scope and jig capacitance. ∗ Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. ∗ Output load (2) for tLZ and tHZ, tOLZ and tOHZ. 295Ω I/O ∗5pF 217Ω Output load (2) Fig. 2. –9– ∗30pF CXK77V3211Q Truth Tables Operation Address used CE CE2 CE2 ADSP ADSC ADV BWx OE CLK DQ Deselected cycle, power-down None H X X X L X X X L-H High-Z Deselected cycle, power-down None L X L L X X X X L-H High-Z Deselected cycle, power-down None L H X L X X X X L-H High-Z Deselected cycle, power-down None L X L H L X X X L-H High-Z Deselected cycle, power-down None L H X H L X X X L-H High-Z READ cycle, begin burst External L L H L X X X L L-H READ cycle, begin burst External L L H L X X X H L-H High-Z WRITE cycle, begin burst External L L H H L X L X L-H D READ cycle, begin burst External L L H H L X H L L-H Q READ cycle, begin burst External L L H H L X H H L-H High-Z READ cycle, continue burst Next X X X H H L H L L-H READ cycle, continue burst Next X X X H H L H H L-H High-Z READ cycle, continue burst Next H X X X H L H L L-H READ cycle, continue burst Next H X X X H L H H L-H High-Z WRITE cycle, continue burst Next X X X H H L L X L-H D WRITE cycle, continue burst Next H X X X H L L X L-H D READ cycle, suspend burst Current X X X H H H H L L-H Q READ cycle, suspend burst Current X X X H H H H H L-H High-Z READ cycle, suspend burst Current H X X X H H H L L-H READ cycle, suspend burst Current H X X X H H H H L-H High-Z WRITE cycle, suspend burst Current X X X H H H L X L-H D WRITE cycle, suspend burst Current H X X X H H L X L-H D Q Q Q Q Note) 1. X means "don't care". H means logic HIGH. L means logic LOW. BWx = L means any one or more byte write enable signals (BW1, BW2, BW3, BW4) are LOW. BWx = H means all byte write enable signals are HIGH. 2. BW1 enables writes to Byte 1 (DQ1 to DQ8). BW2 enables writes to Byte 2 (DQ9 to DQ16). BW3 enables writes to Byte 3 (DQ17 to DQ24). BW4 enables writes to Byte 4 (DQ25 to DQ32). 3. All inputs except OE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. Wait states are inserted by suspending burst. 5. For a write operation following a read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in HIGH-Z during power-up. 7. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. – 10 – CXK77V3211Q Read Timing (Pipeline) tKC CLK AA AA AA A AA A AA AA A AA AA A AA AA AA A AA A AA AA A AA AA A AA AAA A AA A AA AA A AA AA A AA AAA AA AAAAAAAAA AA AA AAA AA AAAAAAAAA AA AA AAAAA A AA AA AA AA A AA AA A AA A AAAAA A AA AA AA AA A AA AA A AA A AA AAA AAAAAAAAAA A AA A AAAAA AA A AA AA A AA AA AA AAAAAAA AAAAAAAAAA AA tKH tKL tS tH ADSP tS tH ADSC tS ADDR. tH A1 A4 A3 A2 Burst continued with new base address tS tH BW1 to BW4 tS tH Deselect cycle CE (∗2) tS tH ADV ADV suspends burst OE tOE High-Z tOHZ tOLZ tLZ Q Q (A1) tKQ (∗3) tHZ tKQX Q (A2) Q (A2 + 1) Q (A2 + 2) Q (A2 + 3) Q (A2) Q (A2 + 1) tKQ Single READ (∗1) Burst wrap around to its initial state. Burst READ A DON'T CARE UNDEFINED ∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE is LOW. ∗3 On deselect cycle, Q is tri-stated immediately on the same cycle CE is LOW. – 11 – CXK77V3211Q Write Timing (Pipeline) tKC CLK tKH tKL AA A AA AA AA A AA AA AA AA AAA AA AAA AAA A AA AA AA AA AA AA A AA AAA AAA A AA AA AA AA AA A AA A AAA AA AAAAAAAA AAAAA AAA AA AAAAAAAA AAAAA AA AAA AAA AA AA AA AA AA AA AA AA AA AAA AAA AA AA AA AA AA AA AA AA AAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AA AA A AA A AA AA A AA AAAAAAAAAAAAAAA tS tH ADSP ADSC extends burst tS tH tS tH ADSC tS ADDR. tH A1 A3 A2 BYTE WRITE signal are ignored for first cycle when ADSP intiates burst tS tH BW1 to BW4 tS tH CE (∗2) tS tH ADV (∗4) OE ADV suspends burst (∗3) tS tH High-Z D D (A1) tOHZ D (A2) D (A2 + 1) D (A2 + 1) D (A2 + 2) D (A2 + 3) D (A3 + 1) D (A3) D (A3 + 2) (∗1) Q Burst READ Single WRITE Burst WRITE Extended Burst WRITE AA AA DON'T CARE UNDEFINED ∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. ∗3 OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. ∗4 ADV must be HIGH to permit a WRITE to the loaded address. – 12 – CXK77V3211Q Read/Write Timing (Pipeline) tKC AA AA AA AAAAAA AAA AAA AAA AAAAAAAAAAA AAA AAA AAA AAAAAAAAAAA AAAA AAAAA AAA AAA AAAAAAAAAAAAAA A AAAAAAA AAA AAAA AAAAAAAAAA AAAA CLK tKH tKL tS tH ADSP ADSC tS ADDR. tH A1 A2 A3 tS tH BW1 to BW4 tS tH CE (∗2) ADV OE High-Z D tS tKQ tH tOLZ D (A2) tLZ tKQ tOHZ (∗1) High-Z Q Q (A1) Single READ Q (A2) Single WRITE Pass Through READ Q (A3) Q (A3 + 1) Burst READ Q (A3 + 2) AA AA DON'T CARE UNDEFINED ∗1 Q (A3) refers to output from address A3. Q (A3 + 1) refers to output from the next internal burst address following A3. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. – 13 – CXK77V3211Q Read Timing (Flow-Thru) tKC AA AA AA AA AA AA AA A AA A AA A AA AA AA AA AA AA AA A AA A AA A AA AAA AA AA AA AA A AA A AA A AA AAA AA AA AA AA A AA A AA A AAA AA AAAAAAAAA AAAA AAA AA AAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAA AA AA AAAAAAAAAA A AAAAA AAA AA AA A AA A AA AAA AAAAAAAAAAAAAAAAAAAAA CLK tKH tKL tS tH ADSP tS tH ADSC tS ADDR. tH A1 A3 A2 tS tH BW1 to BW4 tS tH CE (∗2) tS tH ADV ADV suspends burst OE tOE High-Z tOHZ tOLZ tKQ tKOX tHZ tLZ Q Q (A1) Q (A2) Q (A2 + 1) Q (A2 + 2) Q (A2 + 3) Q (A2) Q (A2 + 1) Q (A3) tKQ (∗1) Single READ Burst READ AA AA Burst wrap around to its initial state. DON'T CARE UNDEFINED ∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE is LOW. – 14 – CXK77V3211Q Write Timing (Flow-Thru) tKC CLK tKH tKL AA A AA AA AA A AA AA AA AA AAA AA AAA AAA A AA AA AA AA AA AA A AA AAA AAA A AA AA AA AA AA A AA A AAA AA AAAAAAAA AAAAA AAA AA AAAAAAAA AAAAA AAAAAAAA AAAAAAAAAAAAAAAA AA AAA AAA AA AA AA AA AA AA AA AA AAA AAA AAAAAAAAA AAAAA A AAAAA AAA A AA AA AAA AA AA AAAAAAAA A AA AA A AAA AA AA AAAAAAAAAAAAA AAAAAAAAAAAAA AA AA A AA A AA AA A AA AAAAAAAAAAAAAAA tS tH ADSP ADSC extends burst tS tH tS tH ADSC tS tH A1 ADDR. A3 A2 BYTE WRITE signal are ignored for first cycle when ADSP intiates burst tS tH BW1 to BW4 tS tH CE (∗2) tS tH ADV (∗4) OE (∗3) tS tH High-Z D ADV suspends burst D (A1) tOHZ D (A2) D (A2 + 1) D (A2 + 1) D (A2 + 2) D (A2 + 3) D (A3 + 1) D (A3) D (A3 + 2) (∗1) Q Burst READ Single WRITE Burst WRITE Extended Burst WRITE AA AA DON'T CARE UNDEFINED ∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. ∗3 OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period to the byte write enable inputs being sampled. ∗4 ADV must be HIGH to permit a WRITE to the loaded address. – 15 – CXK77V3211Q Read/Write Timing (Flow-Thru) tKC CLK tKH tKL AAAAA AAA AA AA AAAAAAAAAAA AAA AA AA AAAAAAAAAAA AAAAAAAAAA AAA AAA AAAAAAAAAAAAAA A AAAAAAA AAA AAA AAAAAAAAAA AAA tS tH ADSP ADSC tS ADDR. tH A1 A2 A3 tS tH BW1 to BW4 tS tH CE (∗2) ADV OE tS tH tOLZ High-Z D tOHZ D (A2) tKQ (∗1) High-Z Q Q (A1) Single READ Q (A3) Single WRITE Q (A3 + 1) Q (A3 + 2) Burst READ Q (A3 + 3) AA DON'T CARE UNDEFINED ∗1 Q (A3) refers to output from address A3. Q (A3 + 1) refers to output from the next internal burst address following A3. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. – 16 – CXK77V3211Q ZZ Timing tKC CLK AAAAAA AAA AAAA AAAAA AAAA AAAAA tKH tKL tS tH ADSP ADSC tZZS tZZH ZZ Snooze – 17 – tZZR AAA AAA AAA CXK77V3211Q Package Outline Unit: mm 100PIN QFP (PLASTIC) 1420 23.2 ± 0.2 ∗20.0 ± 0.1 51 80 50 81 (15.4) 17.2 ± 0.2 ∗14.0 ± 0.1 B A 31 100 30 0.65 + 0.35 2.75 – 0.15 0.12 M 0.25 + 0.15 0.1 – 0.05 0.1 DETAIL A 1.6 ± 0.2 15.6 ± 0.2 (0.3) (0.8) + 0.13 0.9 – 0.15 (15.4) 0° to 10° + 0.08 0.32 – 0.07 (0.15) + 0.04 0.17 – 0.03 1 DETAIL B NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE SONY CODE QFP-100P-L02 EIAJ CODE ∗QFP100-P-1420-B JEDEC CODE – 18 – PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER PACKAGE WEIGHT 1.7g