TI TPS5510P

TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168 – JULY 1998
D
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
Over Voltage Protection and Lock Out for
5 V, 3.3 V, and 12 V
Under Voltage Protection and Lock Out for
5 V and 3.3 V
Fault Protection Output with Open Drain
Output Stage
Open Drain Power Good Output Signal for
Power Good Input, 5 V and 3.3 V
300 ms Power Good Delay
75 ms Delay for 5-V and 3.3-V Short-Circuit
Turn On Protection
38 ms PSON Control Debounce
73 µs Width Noise Deglitches
Wide Power Supply Voltage Range
from 4 V to 15 V
PGI
GND
FPO
PSON
1
8
2
7
3
6
4
5
PGO
VCC
VS5
VS33
description
The TPS5510 is designed to minimize external components of personal computer switching power supply
systems. It provides protection circuits, power good indicator, fault protection output (FPO), and a PSON control.
OVP (Over Voltage Protection) monitors 5 V, 3.3 V, and 12 V (12 V OV detects via VCC terminal). UVP (Under
Voltage Protection) monitors 5 V and 3.3 V. When an OV or UV condition is detected, the PGO (power good
output) is asserted low and FPO is latched high. PSON from low to high resets the protection latch. UVP function
will be enabled 75 ms after PSON is set low and debounced.
Power good feature monitors PGI, 5 V and 3.3 V and issues a power good signal when they are ready.
The TPS5510 is characterised for operation from TJ = –40°C to 125°C junction temperature.
PGI
5 VSB
PGO
TPS5510
1
2
3
4
PSON
12 V
PGI
PGO
GND
VCC
FPO
VS5
PSON
VS33
8
0.5 V
Drop
7
6
5
VSB
5V
3.3 V
Figure 1. TPS5510 Typical Application
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168 – JULY 1998
functional block diagram
VCC
POR
12 OV
–
Vref
+
Reset
RST
VCCI = 3.6 V
RI = 200 kΩ
R
R
VS5
Vref
1.192 V
RTT
FPO
R
73 µs
Debounce
5 OV
Vref
Bandgap
Reference
Vreg
S
Q
–
73 µs
Debounce
+
RI = 100 kΩ
Reset
Derminent
Latch
R
VCC
150 µA
VS33
Reset
Reset
OSC
3.3 OV
Vref
VCCI
RTT
–
38 ms
Debounce
RST
+
PSON
RI = 100 kΩ
Vref
–
75 ms
Delay
Counter
3.3 UV
+
R
EN
Pull-High
Resistor
R
Vref
–
73 µs
Debounce
5 UV
+
PGO
EN
RST
Vref
PGI
2
–
+
POST OFFICE BOX 655303
VCC
• DALLAS, TEXAS 75265
300 ms
Delay
Counter
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168 – JULY 1998
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
VS33
5
I
3.3 V over/under voltage protection input pin
VS5
6
I
5 V over/under voltage protection input pin
GND
2
FPO
3
PGI
PGO
Ground
O
Inverted fault protection output, open drain output stage
1
I
Power good input signal pin
8
O
Power good output signal pin, open drain output stage
PSON
4
I
ON/OFF control input pin
VCC
7
I
Supply voltage/12 V over voltage protection input pin
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA = 125°C
POWER RATING
P
1092 mW
8.74 mW/°C
218 mW
D
730 mW
5.84 mW/°C
146 mW
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC, (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Output voltage, VO (FPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Output voltage, VO (PGO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Supply current, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see Dissipation Rating Table
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to the device GND terminal.
recommended operating conditions
TEST CONDITIONS
Supply voltage, VCC
Input voltage, VI
voltage VO
Output voltage,
4
PSON, VS5, VS33, PGI
TYP
MAX
UNIT
15
V
7
V
FPO
15
V
PGO
7
V
Operating junction temperature, TJ
Output sink current
current, IO(
O(sink)
i k)
MIN
–40
FPO
PGO
Supply voltage rising time, tr
See Note 2
1
125
°C
30
mA
10
mA
ms
NOTE 2: VCC rising and falling slew rate must be less then 14 V/ms.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168 – JULY 1998
electrical characteristics, VCC = 5 V, TJ = full range. (unless otherwise specified)
over voltage protection
PARAMETER
TEST CONDITIONS
Over-voltage threshold
MIN
TYP
MAX
VS33
3.9
4.1
4.3
VS5
5.7
6.1
6.5
13.3
13.8
14.3
VCC
ILKG
VOL
Leakage current (FPO)
V(FPO) = 5 V
5
Low level output voltage (FPO)
Isink = 10 mA
Isink = 30 mA
0.3
0.7
UNIT
V
µA
V
PGI and PGO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.141
1.192
1.242
V
VS33
2.71
2.83
2.95
VS5
4.1
4.3
4.47
3.3 V, 5 V
49
75
114
ms
5
µA
0.4
V
Input threshold voltage (PGI)
Under voltage threshold
Under-voltage
Short circuit protection delay time
ILKG
VOL
Leakage current (PGO)
PGO = 5 V
Low level output voltage (PGO)
Sink current = 10 mA
V
PSON control
PARAMETER
TEST CONDITIONS
Input pull-up current
MIN
PSON = 0 V
High-level input voltage
TYP
MAX
UNIT
µA
150
2.4
V
Low-level input voltage
1.2
V
total device
PARAMETER
ICC
TEST CONDITIONS
Supply current
MIN
TYP
PSON = 5 V
MAX
1
UNIT
mA
switching characteristics, VCC = 5 V, TJ = full range
PARAMETER
td
tb
4
MIN
TYP
MAX
UNIT
Delay time (PGI to PGO)
TEST CONDITIONS
200
300
450
ms
De-bounce time (PSON)
24
38
57
ms
Noise deglitch time
47
73
110
µs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168 – JULY 1998
timing chart
VCC
Reset
R
PSON
S
Q
FPO
PGI
3.3 V
5V
12 V
PGO
td
td
td
PG OFF delay
tb
Protect Occur
tb
AC
OFF
PSON
OFF
POST OFFICE BOX 655303
PSON
ON
• DALLAS, TEXAS 75265
5
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated