www.ti.com
SLVS422A – JULY 2003
FEATURES
D OVER-VOLTAGE PROTECTION AND LOCKOUT: 12V,
5V, and 3.3V Supplies
D OVER-CURRENT PROTECTION AND LOCKOUT:
D
12V, 5V, and 3.3V Supplies
UNDER-VOLTAGE PROTECTION AND
LOCKOUT: 12V Supplies
D UNDER-VOLTAGE DETECT: 5V and 3.3V Supplies
D FAULT-PROTECTION OUTPUT WITH
OPEN–DRAIN OUTPUT STAGE
D
D
D
D
D
D
OPEN-DRAIN, POWER-GOOD OUTPUT SIGNAL:
Monitors Power–Good Signal Input 3.3V and 5V
Supplies
300ms POWER-GOOD DELAY
75ms DELAY: 5V, 3.3V Power-Supply Short-Circuit
Turn-On Protection
2.3ms PSON CONTROL TO FPO TURN–OFF DELAY
38ms PSON CONTROL DEBOUNCE
WIDE SUPPLY VOLTAGE RANGE: 4.5V to 15V
DESCRIPTION
The TPS3514 is a PC switching power-supply system monitor
with minimum external components. It provides under-voltage
lockout (UVLO), over-voltage (OV), under-voltage (UV),
over-current (OC), protection circuits, power-good indicator, and
on/off control.
UVLO thresholds are 4.45V (on) and 3.65V (off). Over-current
protection (OCP) and over-voltage protection (OVP) monitor 3.3V,
5V, and 12V supplies. When an OC or OV condition is detected,
the power–good output (PGO) is asserted LOW and the fault
protection output (FPO) is latched HIGH. PSON from
LOW-to-HIGH resets the latch. The OCP function will be enabled
75ms after PSON goes LOW with PGI HIGH and a debounce of
typically 38ms. A built-in 2.3ms delay with 38ms debounce from
PSON to FPO output is enabled at turn–off.
An external resistor is connected between the RI pin and the GND
pin. This will program a precise I(REF) for OCP function. The
programmable I(REF) range is from 12.5µA to 62.5µA. Three OCP
comparators and the I(REF) section are supplied by VS12. The
current draw from the VS12 pin is less than 1mA.
The power–good feature monitors PGI, the 3.3V and 5V supplies,
and issues a power–good signal when the output is ready.
The TPS3514 is characterized for operation from –40°C to 85°C.
The TPS3514 is available in DIP-14 and SO-14 packages.
IO
0.01Ω
12V
12V
0.01Ω
5V
5V
0.01Ω
3.3V
5V VSB
PG
From Transformer
R1Ω
R2Ω
System Side
3.3V
5V VSB
470kΩ
1kΩ
TPS3514
PGI
PGO
GND
VDD
FPO
VS5
PSON
VS33
IS12
VS12
Power Supply
Output Side
560Ω
820Ω
56kΩ
RI
IS33
NC
IS5
1.5kΩ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
!" #!$% &"' &! #" #" (" " ") !" && *+'
&! # ", &" " "%+ %!&" ", %% #""'
Copyright 2002–2003, Texas Instruments Incorporated
www.ti.com
SLVS422A – JULY 2003
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE–LEAD
PACKAGE
DESIGNATOR(1)
SO 14
SO-14
D
DIP-14
N
TPS3514
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TPS3514D
Rails, 50
–40°C
40 C to +85
+85°C
C
TPS3514
TPS3514DR
Tape and Reel, 2500
TPS3514N
Rails, 25
TRANSPORT
MEDIA, QUANTITY
NOTE: (1) For the most current specifications and package information, refer to our web site at www. ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
Voltage on PSON, IS5, IS33, PGI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Voltage on VS33, VS5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
Voltage on FPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
PGO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 16V
Continuous Total Power Dissipation . . . . . . . . See Dissipation Rating Table
Operating Free-Air Temperature Range, TA . . . . . . . . . . . . . . –40°C to 85°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTES: (1) Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure
to absolute-maximum–rated conditions for extended periods may affect device
reliability. (2) All voltage values are with respect to GND.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe proper handling and installation procedures can
cause damage.
ESD damage can range from subtle performance
degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because very small parametric changes could cause
the device not to meet its published specifications.
RECOMMENDED OPERATING CONDITIONS
At specified temperature range.
PARAMETER
Supply Voltage
VDD
Inputs
MIN
MAX
UNITS
4.5
15
V
VI
PSON, VS5, VS33, IS5, IS33
7
V
VS12, IS12
15
V
VDD + 0.3V
(max = 7V)
V
FPO
15
V
PGO
7
V
FPO
20
mA
PGO
10
mA
PGI
Outputs
Sink Current
TA < 25°C
POWER
RATING
DERATING
FACTOR
ABOVE
TA = 25°C
TA = 70°C
POWER
RATING
TA = 85°C
POWER
RATING
D
956mW
7.65mW/°C
612mW
497mW
N
1512mW
12.1mW/°C
968mW
786mW
OVER–CURRENT PROTECTION
IO(SINK)
tR(1)
I(REF)
Operating Free-Air Temperature Range
TA
1
MAX
OUTPUT CURRENT
OVER–CURRENT
PROTECTION TRIP POINT(1)
ms
12V
6A
9.2A
12.5
62.5
µA
5V
16A
24.6A
–40
85
°C
3.3V
9A
13.5A
NOTE: (1) VDD rising and falling slew rate must be less than 14V/ms.
2
PACKAGE
VO
Supply Voltage Rising Time
OCP Reference Source
DISSIPATION RATING TABLE
NOTE: (1) Over-current protection trip point can be programmable.
www.ti.com
SLVS422A – JULY 2003
ELECTRICAL CHARACTERISTICS
Limits apply over operating free-temperature range, TA = –40°C to +85°C, unless otherwise noted.
TPS3514
PARAMETER
CONDITIONS
UNITS
MIN
TYP
MAX
VS33
3.7
3.9
4.1
V
VS5
5.7
6.1
6.5
V
VS12
13.2
13.8
14.4
V
7.6
8
8.4
OVER–VOLTAGE AND OVER-CURRENT PROTECTION
Over–Voltage Threshold
Ratio of Current Sense Sink Current to Current
Sense Setting Pin (RI) Source Current, I(REF) C
Leakage Current (FPO)
Low-Level Output Voltage (FPO)
V(FPO) = 5V
I(SINK) = 20mA, VDD = 5V
V(RI)
VDD = 5V
VDD = 5V
Noise Deglitch Time (OVP)
Current Source Reference Voltage
Resistor at RI = 30kΩ, 0.1% Resistor
llkg
VOL
5
µA
0.7
V
35
73
110
µs
1.1
1.15
1.2
V
4.45
V
UNDER–VOLTAGE LOCKOUT
Start Threshold Voltage
Minimum Operating Voltage After Start–Up
3.65
V
PGI AND PGO
Input Threshold
VIT(PGI)
0.99 x typ
1.15
1.01 x typ
V
VS33
2
2.2
2.4
V
VS5
3.3
3.5
3.7
V
VS12
8.5
9
9.5
V
5
mV
PGO = 5V
5
µA
I(SINK) = 10mA, VDD = 4.5V
0.4
V
Under-Voltage Threshold
Input Offset Voltage for OCP Comparators
Leakage Current (PGO)
Low-Level Output Voltage (PGO)
Short-Circuit Protection Delay
Delay Time
–5
llkg
VOL
3.3V, 5V
49
75
114
ms
VDD = 5V
VDD = 5V
200
300
450
ms
3.2
4.8
7.2
ms
VDD = 5V
VDD = 5V
88
150
225
ms
88
150
225
ms
td(1)
PGI to PGO
PGI to FPO
Noise Deglitch Time
PGI to PGO
12V UVP to FPO
PSON CONTROL
Input Pull-Up Current
PSON = 0V
Low-Level Input Voltage
II
VIH
VIL
Debounce Time (PSON)
t(b)
VDD = 5V
VDD = 5V
High-Level Input Voltage
Delay Time (PSON to FPO)
t(d)(2)
µA
–120
2.4
V
1.2
V
24
38
50
ms
tb + 1.1
tb + 2.3
tb + 4
ms
1
mA
TOTAL DEVICE
Supply Current
IDD
PSON = 5V
3
www.ti.com
SLVS422A – JULY 2003
PIN CONFIGURATION
PIN ASSIGNMENTS
PIN
Top View
SO, DIP
NAME
FUNCTION
3
FPO
Inverted Fault Ptotection output. Open-drain output
stage.
2
GND
Ground
5
IS12
12V Over-Current Protection Input
8
IS5
5V Over-Current Protection Input
9
IS33
3.3V Over-Current Protection Input
7
NC
No Internal Connection
1
PGI
Power-Good Input
14
PGO
Power-Good Output. Open-drain output stage.
4
PSON
On/Off Control Input
6
RI
13
Supply Voltage
10
VDD
VS12
11
VS33
3.3V Over-Voltage/Under-Voltage Protection Input
12
VS5
5V Over-Voltage/Under-Voltage Protection Input
OCP Reference Source
12V Over-Voltage/Under-Voltage Protection Input
FUNCTION TABLE
PGI
PSON
UV CONDITION
3.3V/5V
OV CONDITIONS
UV CONDITION 12V
OC CONDITIONS
FPO(1)
PGO(2)
< 0.9V
L
No
< 0.9V
L
No
No
No
L
L
No
Yes
L
< 0.9V
L
L
No
Yes
No
H
< 0.9V
L
L
No
Yes
Yes
H
L
< 0.9V
L
Yes
No
No
L
L
< 0.9V
L
Yes
No
Yes
L
L
< 0.9V
L
Yes
Yes
No
H
L
< 0.9V
L
Yes
Yes
Yes
H
L
> 1.2V
L
No
No
No
L
H
> 1.2V
L
No
No
Yes
H
L
> 1.2V
L
No
Yes
No
H
L
> 1.2V
L
No
Yes
Yes
H
L
> 1.2V
L
Yes
No
No
H
L
> 1.2V
L
Yes
No
Yes
H
L
> 1.2V
L
Yes
Yes
No
H
L
> 1.2V
L
Yes
Yes
Yes
H
L
x
H
x
x
x
H
L
x = Don’t Care.
NOTES: (1) For FPO, L = Fault is not latched. H = Fault is latched. (2) For PGO, L = Fault. H = No Fault.
4
www.ti.com
SLVS422A – JULY 2003
TIMING DIAGRAMS
VDD
(SB5V)
PSON
PFO
PGI
3.3V/5V
300ms
2.3ms 300ms
12V
38ms
38ms
PGO
PSON Off
PSON
On
PGO
Off
300ms
OVP
Occurs
DIAGRAM 1: AC Turn-On and Over-Voltage Protect.
VDD
PSON
FPO
PGI
3.3V/5V
12V
300ms
300ms
PGO
38ms
38ms
300ms
3.3V or 5V Drop
OCP Occurs
300ms
12V UVP
Occurs
DIAGRAM 2: Over-Current and Under-Voltage Detect/Protect.
5
www.ti.com
SLVS422A – JULY 2003
SCHEMATIC
VDD
VS12
12V OV
+
_
UVLO
POR
VS5
R
5V OV
FPO
+
_
S
73µ s
Debounce
VS33
2.3ms
Delay
VDD
38ms
Debounce
3.3V OV
+
_
PSON
3.3V UV
+
_
75ms
Delay
5V UV
VDD
+
_
PGO
PGI1
PGI
150µs
Debounce
+
_
300ms
Delay
12V UV
+
_
Band-Gap
Reference
1.153V
150µ s
Debounce
_
IS12
+
Iref x 8
_
IS5
+
Iref x 8
_
IS33
+
Iref x 8
6
I(REF) OCP Reference Source
RI
www.ti.com
SLVS422A – JULY 2003
TYPICAL CHARACTERISTICS
TA = 25° unless otherwise noted.
7
www.ti.com
SLVS422A – JULY 2003
TYPICAL CHARACTERISTICS (Cont.)
TA = 25° unless otherwise noted.
Conversely, when either the 5VDC or the 3.3VDC output
voltages fall below the under-voltage threshold, or when
main power has been removed for a sufficiently long time
so that power-supply operation is no longer assured,
PGO should be deasserted to a LOW state.
The power-good, DC enable (PSON), and the 5V/3.3V
supply rails are shown in Figure 1.
Although there is no requirement to meet specific timing
parameters, the following signal timings are
recommended:
DETAILED DESCRIPTION
POWER-GOOD AND POWER-GOOD DELAY
A PC power supply is commonly designed to provide
a power-good signal, which is defined by the
computer manufacturers. Power-Good Output (PGO)
is a power-good indicator and should be asserted
HIGH by the PC power supply to indicate that the
5VDC and 3.3VDC outputs are above the
under-voltage threshold limit. At this time, the supply
should be able to provide enough power to assure
continuous operation within the specification.
PSON
2ms ≤ t2 ≤ 20ms, 100ms < t3 < 2000ms, t4 > 1ms, t5 ≤
10ms
On
Off
75%
5V/3.3V
Output
10%
PGO
t5
t3
t2
FIGURE 1: Timing of PSON and PGO.
8
t4
www.ti.com
SLVS422A – JULY 2003
Furthermore, motherboards should be designed to
comply with the above recommended timing. If timings
other than these are implemented or required, this
information should be clearly specified.
The TPS3514 family of power-supply supervisors
provides a PGO for the 3.3V and 5V supply voltage rails
and a separate Power-Good Input (PGI). An internal
timer is used to generate a 300ms power-good delay.
If the voltage signals at PGI, VS33, and VS5 rise above
the under-voltage threshold, the open-drain PGO will go
HIGH after a delay of 300ms. When the PGI voltage or
any of the 3.3V/5V rail drops below the under-voltage
threshold, PGO will be disabled immediately.
POWER-SUPPLY REMOTE ON/OFF (PSON) AND
FAULT PROTECT OUTPUT (FPO)
Since the latest personal computer generation focuses
on easy turn-on and power–saving functions, the PC
power supply will require two characteristics. One is a
DC power-supply remote on/off function; the other is
standby voltage to achieve very low power consumption
of the PC system. Thus, requiring the main power
supply to be shut down.
The power-supply remote on/off (PSON) is an
active-LOW signal that turns on all of the main power
rails including the 3.3V, 5V, –5V, and –12V power rails.
When this signal is held HIGH by the PC motherboard
or left open-circuited, the signal of the Fault Protect
Output (FPO) also goes HIGH. In this condition, the
main power rails should not deliver current and should
be held at 0V.
When the FPO signal is held HIGH due to an occurring
fault condition, the fault status will be latched and the
outputs of the main power rails should not deliver
current and should be held at 0V. Toggling PSON from
LOW to HIGH will reset the fault protection latch. During
this fault condition, only the standby power is not
affected.
When PSON goes from HIGH to LOW or LOW to HIGH,
the 38ms debounce block will prevent a glitch on the
input from disabling/enabling the FPO output. During
the HIGH to LOW transition, the under-voltage function
is disabled to prevent turn-on failure.
Power should be delivered to the rails only if the PSON
signal is held at ground potential, thus, FPO is active
LOW. The FPO pin can be connected to 5VDC (or up to
15VDC) through a pull-up resistor.
UNDER-VOLTAGE PROTECTION (UVP)
The TPS3514 provides Under-Voltage Protection
(UVP) for the 12V rail and Under-Voltage Detect (UVD)
for the 3.3V and 5V rails. When an under-voltage
condition appears at the VS12 input pin for more than
150µs, the FPO output goes HIGH and PGO goes LOW.
Also, this fault condition will be latched until PSON is
toggled from LOW to HIGH or VDD is removed.
OVER-CURRENT PROTECTION (OCP)
In bridge, or forward type, off-line switching power
supplies, usually designed for medium to large power,
the overload protection design needs to be very precise.
Most of these types of power supplies sense the output
current for an overload condition. The trigger-point
needs to be set higher than the maximum load in order
to prevent false turn-on.
The TPS3514 provides Over-Current Protection (OCP)
for the 3.3V, 5V, and 12V rails. When an over-current
condition appears at the OCP comparator input pins for
more than 73µs, the FPO output goes HIGH and PGO
goes LOW. Also, this fault condition will be latched until
PSON is toggled from LOW to HIGH or VDD is removed.
The resistor connected between the RI pin and the GND
pin will create a precise I(REF) for the OCP function. The
formula for choosing the RI resistor is V(RI)/I(REF). The
I(REF) range is from 12.5µA to 62.5µA. Three OCP
comparators and the I(REF) section are supplied through
the V12 pin. Current drawn from the VS12 pin is less
than 1mA.
9
www.ti.com
SLVS422A – JULY 2003
Following is an example on calculating OCP for the 12V
rail:
RI = V(RI)/I(REF) = 1.15V/20µA = 56KΩ
I(REF) • C • R(IS12) = R(SENSE) • I(OCP_TRIP)
I(OCP_TRIP) = 20µA • 8 • 560Ω/0.01Ω = 9.2A
C = Current Ratio (typically = 8)
OVER-VOLTAGE PROTECTION (OVP)
The Over-Voltage Protection (OVP) of the TPS3514
monitors 3.3V, 5V, and 12V. When an over-voltage
condition appears at one of the 3.3V, 5V, or 12V input pins
for more than 73µs, the FPO output goes HIGH and PGO
goes LOW. Also, this fault condition will be latched until
PSON is toggled from LOW-to-HIGH or VDD is removed.
10
During fault conditions, most power supplies have the
potential to deliver higher output voltages than those
normally specified or required. In unprotected
equipment, it is possible for output voltages to be high
enough to cause internal or external damage of the
system. To protect the system under these abnormal
conditions, it is common practice to provide
over-voltage protection within the power supply.
www.ti.com
SLVS422A – JULY 2003
PACKAGE DRAWINGS
11
www.ti.com
SLVS422A – JULY 2003
PACKAGE DRAWINGS (Cont.)
12
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS3514D
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS3514DR
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TPS3514N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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