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FEATURES
D Up to 95% Conversion Efficiency
D Typical Quiescent Current: 18 µA
D Load Current: 1.2 A
D Operating Input Voltage Range: 2.5 V to 6.0 V
D Switching Frequency: 1.25 MHz
D Adjustable and Fixed Output Voltage
D Power Save Mode Operation at Light load
D
D
D
D
D
D
D
Currents
100% Duty Cycle for Lowest Dropout
Internal Softstart
Dynamic Output Voltage Positioning
Thermal Shutdown
Short-Circuit Protection
10 Pin MSOP PowerPad Package
10 Pin QFN 3 X 3 mm Package
APPLICATIONS
D PDA, Pocket PC and Smart Phones
D
D
D
D
D
USB Powered Modems
CPUs and DSPs
PC Cards and Notebooks
xDSL Applications
Standard 5-V to 3.3-V Conversion
DESCRIPTION
The TPS6204x family of devices are high efficiency
synchronous step-down dc-dc converters optimized for
battery powered portable applications. The devices are
ideal for portable applications powered by a single Li-Ion
battery cell or by 3-cell NiMH/NiCd batteries. With an
output voltage range from 6.0 V down to 0.7 V, the devices
support low voltage DSPs and processors in PDAs,
pocket PCs, as well as notebooks and subnotebook
computers. The TPS6204x operates at a fixed switching
frequency of 1.25 MHz and enters the power save mode
operation at light load currents to maintain high efficiency
over the entire load current range. For low noise
applications, the devices can be forced into fixed
frequency PWM mode by pulling the MODE pin high. The
TPS6204x supports up to 1.2-A load current.
EFFICIENCY
vs
LOAD CURRENT
100
Typical Application Circuit 1.2-A Output Current
VO = 1.8 V
95
VI = 2.7 V
90
C1
22 µF
TPS6204x
2
VIN
3
VIN
1
EN
6
MODE
4
GND
SW
8
L1
6.2 µH
7
SW
5
FB
10
PGND
9
PGND
VO
0.7 V to VI /1.2 A
C2
22 µF
VI = 3.6 V
85
Efficiency − %
VI
2.5 V to 6 V
80
VI = 5 V
75
70
65
MODE = Low
60
55
50
VI = 3.6 V
MODE = High
45
40
0
0.01
0.1
1
10
100
1k
10 k
IL − Load Current − mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
!"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(, %$0+*()
*$"#$%& ($ )-,*!#!*'(!$") -,% (1, (,%&) $# ,2') ")(%+&,"() )('"0'%0 3'%%'"(4
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Copyright 2003, Texas Instruments Incorporated
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE
TA
PACKAGE MARKING
VOLTAGE OPTIONS
MSOP(1)
QFN(2)
MSOP
QFN
Adjustable
TPS62040DGQ
TPS62040DRC
BBI
BBO
1.5 V
TPS62042DGQ
TPS62042DRC
BBL
BBS
1.6 V
TPS62043DGQ
TPS62043DRC
BBM
BBT
1.8 V
TPS62044DGQ
TPS62044DRC
BBN
BBU
−40°C
−40
C to 85
85°C
C
3.3 V
TPS62046DGQ
TPS62046DRC
BBQ
(1) The DGQ package is available in tape and reel. Add R suffix (DGQR) to order quantities of 2500 parts per reel.
(2) The DRC package is available in tape and reel. Add R suffix (DRCR) to order quantities of 3000 parts per reel.
BBW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
Supply voltage VIN (2)
−0.3 V to 7 V
Voltages on EN, MODE, FB, SW(2)
−0.3 V to VCC +0.3 V
See Dissipation Rating Table
Continuous power dissipation
Operating junction temperature range
−40°C to 150°C
Storage temperature range
−65°C to 150°C
Lead temperature (soldering, 10 sec)
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
RQJA(1)
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
MSOP
60°C/W
1.67 W
917 mW
667 mW
QFN
48.7°C/W
2.05 W
1.13 W
821 mW
PACKAGE
(1) The thermal resistance, RΘJA is based on a soldered PowerPAD using thermal vias.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
VI
VO
Supply voltage
2.5
6.0
V
Output voltage range for adjustable output voltage version
0.7
V
IO
L
Output current
Inductor(1)
VI
1.2
CI
CO
Input capacitor(1)
Output capacitor(1)
TA
Operating ambient temperature
TJ
Operating junction temperature
(1) Refer to application section for further information
2
A
6.2
µH
22
µF
µF
22
−40
85
°C
−40
125
°C
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
ELECTRICAL CHARACTERISTICS
VI = 3.6 V, VO = 1.8 V, IO = 600 mA, EN = VIN, TA = −40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)(1)
SUPPLY CURRENT
PARAMETER
VI
I(Q)
Input voltage range
ISD
VUVLO
Shutdown supply current
TEST CONDITIONS
MIN
TYP
2.5
Operating quiescent current
IO = 0 mA, device is not switching
EN = GND
Under−voltage lockout threshold
MAX
V
35
µA
1
µA
18
0.1
1.5
UNIT
6.0
2.3
V
ENABLE AND MODE
VEN
VEN
EN high level input voltage
1.4
V
EN low level input voltage
IEN
EN input bias current
V(MODE) MODE high level input voltage
EN = GND or VIN
0.01
0.4
V
1.0
µA
1.4
V(MODE) MODE low level input voltage
I(MODE) MODE input bias current
MODE = GND or VIN
V
0.01
0.4
V
1.0
µA
POWER SWITCH
P-channel MOSFET on−resistance
rDS(ON)
P-channel MOSFET on−resistance
Ilkg(P)
P-channel leakage current
VI = VGS = 3.6 V
VI = VGS = 2.5 V
VDS = 6.0 V
VI = VGS = 3.6 V
N-channel MOSFET on−resistance
rDS(ON)
IIkg(N)
IL
N-channel MOSFET on−resistance
N-channel leakage current
VI = VGS = 2.5 V
VDS = 6.0 V
P-channel current limit
2.5 V < VI< 6.0 V
1.5
Thermal shutdown
115
210
mΩ
145
270
mΩ
1
µA
85
200
mΩ
115
280
mΩ
1
µA
1.85
2.2
A
°C
150
OSCILLATOR
fS
VFB = 0.5 V
VFB = 0 V
Oscillator frequency
1
1.25
1.5
625
MHz
kHz
OUTPUT
VO
Vref
Adjustable output voltage range
VFB
Feedback voltage
VO
Fixed output voltage
0.7
VI = 2.5 V to 6.0 V; IO= 0 mA
VI = 2.5 V to 6.0 V; 0 mA ≤ IO ≤ 1.2 A
0%
−3%
3%
3%
TPS62042
1.5V
VI = 2.5 V to 6.0 V; IO = 0 mA
VI = 2.5 V to 6.0 V; 0 mA ≤ IO ≤ 1.2 A
0%
−3%
3%
3%
TPS62043
1.6V
VI = 2.5 V to 6.0 V; IO = 0 mA
VI = 2.5 V to 6.0 V; 0 mA ≤ IO ≤ 1.2 A
0%
−3%
3%
3%
TPS62044
1.8V
VI = 2.5 V to 6.0 V; IO = 0 mA
VI = 2.5 V to 6.0 V; 0 mA ≤ IO ≤ 1.2 A
0%
−3%
3%
3%
TPS62046
3.3V
VI = 3.6 V to 6.0 V; IO = 0 mA
VI = 3.6 V to 6.0 V; 0 mA ≤ IO ≤ 1.2 A
0%
−3%
3%
3%
Load regulation(1)
IO = 10 mA to 1200 mA
VI>VO, 0 V ≤ Vsw ≤ VI
VI = open; EN = GND; VSW = 6.0 V
VFB = 0 V
f
Short circuit switching frequency
(1) The line and load regulations are digitally controlled to assure an output voltage accuracy of ±3%.
V
V
TPS62040
Adjustable
VI = VO + 0.5 V (min. 2.5 V) to 6.0 V,
IO = 10 mA
Reverse leakage current into pin SW
VIN
0.5
Line regulation(1)
Leakage current into SW pin
IIkg(SW)
TPS62040
Reference voltage
0
%/V
0
%/mA
0.1
1
0.1
1
625
µA
µA
kHz
3
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PIN ASSIGNMENTS
DGQ PACKAGE
(TOP VIEW)
EN
VIN
VIN
GND
FB
1
10
2
9
3
8
4
7
5
6
DRC PACKAGE
(TOP VIEW)
PGND
PGND
SW
SW
MODE
EN
VIN
VIN
GND
FB
1
10
2
9
3
8
4
7
5
6
PGND
PGND
SW
SW
MODE
NOTE: The PowerPAD must be connected to GND.
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
EN
1
I
Enable. Pulling EN to ground forces the device into shutdown mode. Pulling EN to VI enables the device. EN should
not be left floating and must be terminated.
VIN
2,3
I
Supply voltage input
GND
4
FB
5
I
Feedback pin. Connect FB directly to the output if the fixed output voltage version is used. For the adjustable version
an external resistor divider is connected to this pin. The internal voltage divider is disabled for the adjustable version.
MODE
6
I
Pulling the MODE pin high allows the device to be forced into fixed frequency operation. Pulling the MODE pin to low
enables the power save mode where the device operates in fixed frequency PWM mode at high load currents and
in PFM mode (pulse frequency modulation) at light load currents.
SW
7,8
I/O
PGND
9,10
4
Analog ground
This is the switch pin of the converter and is connected to the drain of the internal power MOSFETs
Power ground
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
FUNCTIONAL BLOCK DIAGRAM
VIN
Current limit Comparator
Undervoltage
Lockout
Bias supply
+
−
Soft
Start
EN
+
Ref
SkipComparator
−
V
Vcomp
Comparator
+
Saw Tooth
Generator
Ref
MODE
1.25 MHz
Oscillator
I
P−Channel
Power MOSFET
VIN
S
R
Control Logic
−
SW
Driver
Shoot−thru
Logic
SW
Comp High
N−Channel
Power MOSFET
Comp Low
Comp Low 2
Comp High
LoadComparator
−
Gm
R1
Compensation
+
R2
+
Comp Low
Comp Low 2
Vref = 0.5 V
MODE
GND
−
+
−
FB
PGND
PGND
For the Adjustable Version the FB Pin Is
Directly Connected to the Gm Amplifier
5
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
η
Efficiency
vs Load current
1, 2, 3
η
Efficiency
vs Input voltage
4
IQ
fs
Quiescent current
vs Input voltage
5, 6
Switching frequency
vs Input voltage
7
rDS(on)
rDS(on)
P-Channel rDS(on)
vs Input voltage
8
N-Channel rectifier rDS(on)
vs Input voltage
9
Load transient response
10
PWM operation
11
Power save mode
12
Start-up
13
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
100
100
VO = 3.3 V
95
VI = 3.6 V
MODE = Low
90
Efficiency − %
75
VI = 3.6 V
MODE = High
70
65
60
VI = 5 V
MODE = High
55
85
VI = 3.6 V
80
VI = 5 V
75
70
MODE = Low
65
55
50
45
45
0.01
0.1
1
10
100
Figure 1
1k
10 k
VI = 3.6 V
MODE = High
60
50
IL − Load Current − mA
6
Efficiency − %
VI = 5 V
MODE = Low
80
0
VI = 2.7 V
90
85
40
VO = 1.8 V
95
40
0
0.01
0.1
1
10
100
IL − Load Current − mA
Figure 2
1k
10 k
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100
100
VO = 1.5 V
95
90
VO = 1.8 V
MODE = Low
95
VI = 2.7 V
85
IL = 500 mA
VI = 3.6 V
Efficiency − %
Efficiency − %
80
VI = 5 V
75
70
65
60
90
85
IL = 1000 mA
IL = 1 mA
80
55
50
75
45
40
0
0.01
0.1
1
10
100
IL − Load Current − mA
1k
70
2.5
10 k
3
3.5
4
4.5
5
VI − Input Voltage − V
Figure 3
QUIESCENT CURRENT
vs
INPUT VOLTAGE
23
7.5
MODE = Low
MODE = High
TA = 85°C
19
7
Quisecent Current − mA
21
Quisecent Current − µ A
6
Figure 4
QUIESCENT CURRENT
vs
INPUT VOLTAGE
TA = 25°C
17
TA = −40°C
15
13
11
6.5
5.5
5
4.5
4
7
3.5
2.8
3.2
3.6
4
4.4 4.8 5.2
VI − Input Voltage − V
Figure 5
5.6
6
TA = 25°C
6
9
5
2.4
5.5
3
2.5
3
3.5
4
4.5
5
5.5
6
VI − Input Voltage − V
Figure 6
7
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
P-CHANNEL rDS(on)
vs
INPUT VOLTAGE
0.180
1.23
TA = 85°C
0.170
1.22
P−Channel r DS(on) − Ω
f − Switching Frequency − MHz
1.23
TA = 25°C
1.22
1.21
1.21
TA = −40°C
1.20
1.20
TA = 85°C
0.150
TA = 25°C
0.140
0.130
0.120
0.110
1.19
0.100
1.19
TA = −40°C
0.090
1.18
1.18
2.5
0.160
2.9
3.3
3.7 4.1 4.5
4.9
VI − Input Voltage − V
5.3
5.7
6
0.080
2.5
2.9
3.3
Figure 7
3.7 4.1 4.5
4.9
VI − Input Voltage − V
Figure 8
N-CHANNEL RECTIFIER rDS(on)
vs
INPUT VOLTAGE
0.150
N-Channel Rectifier r DS(on) − Ω
0.140
0.130
TA = 85°C
0.120
TA = 25°C
0.110
0.100
0.090
0.080
0.070
TA = −40°C
0.060
0.050
2.5
2.9
3.3
3.7 4.1 4.5
4.9
VI − Input Voltage − V
Figure 9
8
5.3
5.7
6
5.3
5.7
6
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PWM OPERATION
IL
500 mA/div
IO
150mA to 1.15 A
VO
20 mV/div
VO
100 mV/div
VI = 3.6 V
VO = 1.8 V
PWM/PFM Operation
V SW
5 V/div
LOAD TRANSIENT RESPONSE
500 ns/div
50 µs/div
Figure 10
Figure 11
POWER SAVE MODE
Enable
2 V/div
VO
1 V/div
I IN
2.5 µs/div
Figure 12
200 mA/div
V SW
5 V/div
IL
500 mA/div
VO
20 mV/div
START-UP
VI = 3.6 V
VO = 1.8 V
IO = 1.1 A
200 µs/div
Figure 13
9
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
DETAILED DESCRIPTION
OPERATION
The TPS6204x is a synchronous step-down converter operating with typically 1.25 MHz fixed frequency. At moderate
to heavy load currents, the device operates in pulse width modulation (PWM), and at light load currents, the device
enters power save mode operation using pulse frequency modulation (PFM). When operating in PWM mode, the
typical switching frequency is 1.25 MHz with a minimum switching frequency of 1 MHz. This makes the device
suitable for xDSL applications minimizing RF (radio frequency) interference.
During PWM operation the converter uses a unique fast response voltage mode controller scheme with input voltage
feed−forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors.
At the beginning of each clock cycle initiated by the clock signal (S) the P-channel MOSFET switch turns on and the
inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit
comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the dead time
preventing current shoot through, the N-channel MOSFET rectifier is turned on and the inductor current ramps down.
The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel
switch.
The Gm amplifier as well as the input voltage determines the rise time of the saw tooth generator, and therefore, any
change in input voltage or output voltage directly controls the duty cycle of the converter, giving a very good line and
load transient regulation.
POWER SAVE MODE OPERATION
As the load current decreases, the converter enters power save mode operation. During power save mode the
converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current
maintaining high efficiency.
The converter monitors the average inductor current and the device enters power save mode when the average
inductor current is below the threshold. The transition point between PWM and power save mode is given by the
transition current with the following equation:
I
transition
+
V
I
18.66 W
(1)
During power save mode the output voltage is monitored with the comparator by the threshold’s comp low and comp
high. As the output voltage falls below the comp low threshold set to typically 0.8% above the nominal output voltage,
the P-channel switch turns on. The P-channel switch remains on until the transition current (1) is reached. Then the
N-channel switch turns on completing the first cycle. The converter continues to switch with its normal duty cycle
determined by the input and output voltage but with half the nominal switching frequency of 625-kHz typ. Thus the
output voltage rises and as soon as the output voltage reaches the comp high threshold of 1.6%, the converter stops
switching. Depending on the load current, the converter switches for a longer or shorter period of time in order to
deliver the energy to the output. If the load current increases and the output voltage can not be maintained with the
transition current , equation (1), the converter enters PWM again. See Figure 11 and Figure 12 under the typical
graphs section and Figure 14 for power save mode operation. Among other techniques this advanced power save
mode method allows high efficiency over the entire load current range and a small output ripple of typically 1% of
the nominal output voltage.
Setting the power save mode thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load
current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient
changes. This allows the converter to operate with small output capacitors like 22 µF and still having a low absolute
voltage drop during heavy load transient. Refer to Figure 14 as well for detailed operation of the power save mode.
10
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
PFM Mode at Light Load
1.6%
Comp High
0.8%
Comp Low
VO
Comp Low 2
PWM Mode at Medium to Full Load
Figure 14. Power Save Mode Thresholds and Dynamic Voltage Positioning
The converter enters the fixed frequency PWM mode as soon as the output voltage falls below the comp low 2
threshold.
DYNAMIC VOLTAGE POSITIONING
As described in the power save mode operation sections before and as detailed in Figure 14 the output voltage is
typically 0.8% (i.e., 1% on average) above the nominal output voltage at light load currents, as the device is in power
save mode. This gives additional headroom for the voltage drop during a load transient from light load to full load.
In the other direction during a load transient from full load to light load the voltage overshoot is also minimized by
turning on the N-Channel rectifier switch to pull the output voltage actively down.
MODE (AUTOMATIC PWM/PFM OPERATION AND FORCED PWM OPERATION)
Connecting the MODE pin to GND enables the automatic PWM and power save mode operation. The converter
operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
Pulling the MODE pin high forces the converter to operate constantly in the PWM mode even at light load currents.
The advantage is the converter operates with a fixed switching frequency that allows simple filtering of the switching
frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode
during light loads (see Figure 1 to Figure 3). For additional flexibility it is possible to switch from power save mode
to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the
TPS6204x to the specific system requirements.
100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS6204x offers a low input to output voltage difference while still maintaining regulation with the use of the 100%
duty cycle mode. In this mode, the P−Channel switch is constantly turned on. This is particularly useful in battery
powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range.
i.e. The minimum input voltage to maintain regulation depends on the load current and output voltage and can be
calculated as:
V min + V max ) I max
I
O
O
ǒrDS(on) max ) RLǓ
(2)
with:
IO(max)= maximum output current plus inductor ripple current
rDS(on)max= maximum P-channel switch tDS(on).
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
SOFTSTART
The TPS6204x series has an internal softstart circuit that limits the inrush current during start up. This prevents
possible voltage drops of the input voltage in case a battery or a high impedance power source is connected to the
input of the TPS6204x.
The softstart is implemented with a digital circuit increasing the switch current in steps of typically ILIM/8, ILIM/4, ILIM/2
and then the typical switch current limit 1.85 A as specified in the electrical parameter table. The start-up time mainly
depends on the output capacitor and load current, see Figure 13.
SHORT-CIRCUIT PROTECTION
As soon as the output voltage falls below 50% of the nominal output voltage, the converter switching frequency as
well as the current limit is reduced to 50% of the nominal value. Since the short-circuit protection is enabled during
start-up, the device does not deliver more than half of its nominal current limit until the output voltage exceeds 50%
of the nominal output voltage. This needs to be considered in case a load acting as a current sink is connected to
the output of the converter.
THERMAL SHUTDOWN
As soon as the junction temperature of typically 150_C is exceeded the device goes into thermal shutdown. In this
mode, the P-Channel switch and N-Channel rectifier are turned off. The device continues its operation when the
junction temperature falls below typically 150°C again.
ENABLE
Pulling the EN low forces the part into shutdown mode, with a shutdown current of typically 0.1 µA. In this mode, the
P-Channel switch and N-Channel rectifier are turned off and the whole device is in shut down. If an output voltage
is present during shut down, which could be an external voltage source or super cap, the reverse leakage current
is specified under electrical parameter table. For proper operation the enable (EN) pin must be terminated and should
not be left floating.
Pulling EN high starts up the TPS6204x with the softstart as described under the section Softstart.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents device misoperation at low input voltages. It prevents the converter from
turning on the switch or rectifier MOSFET with undefined conditions.
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APPLICATION INFORMATION
ADJUSTABLE OUTPUT VOLTAGE VERSION
When the adjustable output voltage version TPS62040 is used, the output voltage is set by the external resistor
divider. See Figure 15.
The output voltage is calculated as:
V
O
ǒ1 ) R1
Ǔ
R2
+ 0.5 V
(3)
with R1 + R2 ≤ 1 MΩ and internal reference voltage Vref typical = 0.5 V
R1 + R2 should not be greater than 1 MΩ because of stability reasons. To keep the operating quiescent current to
a minimum, the feedback resistor divider should have high impedance with R1+R2≤1 MΩ. Due to this and the low
reference voltage of Vref = 0.5 V, the noise on the feedback pin (FB) needs to be minimized. Using a capacitive divider
C1 and C2 across the feedback resistors minimizes the noise at the feedback, without degrading the line or load
transient performance.
C1 and C2 should be selected as:
C1 +
2
1
10 kHz
p
R1
(4)
with:
R1 = upper resistor of voltage divider
C1 = upper capacitor of voltage divider
For C1 a value should be chosen that comes closest to the calculated result.
C2 + R1
R2
C1
(5)
with:
R2 = lower resistor of voltage divider
C2 = lower capacitor of voltage divider
For C2, the selected capacitor value should always be selected larger than the calculated result. For example, in
Figure 15 for C2 100 pF are selected for a calculated result of C2 = 88.42 pF.
If quiescent current is not a key design parameter C1 and C2 can be omitted, and a low impedance feedback divider
has to be used with R1 + R2 < 100 kΩ. This reduces the noise available on the feedback pin (FB) as well but increases
the overall quiescent current during operation. The higher the programmed output voltage the lower the feedback
impedance has to be for best operation when not using C1 and C2.
VI
2.5 V to 6 V
C3
10 µF
TPS62040
2
SW
VIN
3
SW
VIN
1
FB
EN
6
MODE PGND
4
GND
PGND
8
7
5
10
9
VO
1.8 V / 1.2 A
L1
10 µH
R1
470 kΩ
R2
180 kΩ
C1
33 pF
C4
10 µF
C2
100 pF
Figure 15. Adjustable Output Voltage Version
13
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
Inductor Selection
The TPS6204x typically uses a 6.2-µH output inductor. Larger or smaller inductor values can be used to optimize
the performance of the device for specific operation conditions. The selected inductor has to be rated for its dc
resistance and saturation current. The dc resistance of the inductance directly influences the efficiency of the
converter. Therefore an inductor with the lowest dc resistance should be selected for highest efficiency.
Formula (7) calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with formula (7). This is needed
because during heavy load transient the inductor current rises above the value calculated under (7).
DI + V
L
O
V
1– O
V
I
L ƒ
(6)
DI
I max + I max ) L
L
O
2
(7)
with
ƒ = Switching frequency (1.25 MHz typical)
L = Inductor value
∆IL= Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
The highest inductor current occurs at maximum VI.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus
a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the
maximum switch current of 2.2 A for the TPS6204x. Keep in mind that the core material from inductor to inductor
differs and has an impact on the efficiency, especially at high switching frequencies. Refer to Table 1 and the typical
applications and inductors selection.
Table 1. Inductor Selection
INDUCTOR VALUE
14
DIMENSIONS
COMPONENT SUPPLIER
4.7 µH
5,0 mm × 5,0 mm × 3,0 mm
Sumida CDRH4D28C-4.7
4.7 µH
5,2 mm × 5,2 mm × 2,5 mm
Coiltronics SD25-4R7
5.3 µH
5,7 mm × 5,7 mm × 3,0 mm
Sumida CDRH5D28-5R3
6.2 µH
5,7 mm × 5,7 mm × 3,0 mm
Sumida CDRH5D28-6R2
6.0 µH
7,0 mm × 7,0 mm × 3,0 mm
Sumida CDRH6D28-6R0
www.ti.com
SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
Output Capacitor Selection
The advanced fast response voltage mode control scheme of the TPS6204x allows the use of small ceramic
capacitors with a typical value of 22 µF without having large output voltage under and overshoots during heavy load
transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended.
If required, tantalum capacitors may also be used. Refer to Table 2 for component selection.
If ceramic output capacitor are used, the capacitor RMS ripple current rating always meets the application
requirements. Just for completeness the RMS ripple current is calculated as:
I
RMSCout
+V
O
V
1– O
V
I
L ƒ
1
2
Ǹ3
(8)
At nominal load current the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor:
DV
O
+V
O
V
1– O
V
I
L ƒ
ǒ
8
1
C
O
ƒ
Ǔ
) ESR
(9)
Where the highest output voltage ripple occurs at the highest input voltage, VI.
At light load currents, the device operates in power save mode and the output voltage ripple is independent of the
output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical output
voltage ripple is 1% of the nominal output voltage.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required
for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes.
The input capacitor should have a minimum value of 22 µF. The input capacitor can be increased without any limit
for better input voltage filtering.
Table 2. Input and Output Capacitor Selection
CAPACITOR
VALUE
CASE SIZE
22 µF
1206
Taiyo Yuden JMK316BJ226ML
Ceramic
22 µF
1210
Taiyo Yuden JMK325BJ226MM
Ceramic
COMPONENT SUPPLIER
COMMENTS
15
www.ti.com
SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
Layout Considerations
For all switching power supplies, the layout is an important step in the design especially at high peak currents and
switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well as EMI
problems. Therefore, use wide and short traces for the main current paths as indicated in bold in Figure 16. These
traces should be routed first. The input capacitor should be placed as close as possible to the IC pins as well as the
inductor and output capacitor. The feedback resistor network should be routed away from the inductor and switch
node to minimize noise and magnetic interference. To further minimize noise from coupling into the feedback network
and feedback pin, the ground plane or ground traces should be used for shielding. A common ground plane or a star
ground as shown below should be used. This becomes very important especially at high switching frequencies of
1.25 MHz.
The Switch Node Must Be
Kept as Small as Possible
TPS6204x
VI
C3
22 µF
2
3
1
6
4
VIN
VIN
EN
MODE
GND
8
L1
10 µH
SW
7
SW
FB 5
10
PGND
9
PGND
VO
C2
22 µF
Figure 16. Layout Diagram
THERMAL INFORMATION
One of the most influential components on the thermal performance of a package is board design. In order to take
full advantage of the heat dissipating abilities of the PowerPADt packages, a board should be used that acts similar
to a heat sink and allows for the use of the exposed (and solderable), deep downset pad. For further information
please refer to Texas Instruments application note (SLMA002) PowerPAD Thermally Enhanced Package.
The PowerPADt of the 10-pin MSOP package has an area of 1,52 mm × 1,79 mm (± 0,05 mm) and must be soldered
to the PCB to lower the thermal resistance. Thermal vias to the next layer further reduce the thermal resistance.
16
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
TYPICAL APPLICATIONS
VI
Li-lon
TPS62046
2
VIN
3
VIN
1
EN
6
MODE
4
GND
C1
22 µF
SW
8
L1
6.2 µH
7
SW
5
FB
10
PGND
9
PGND
VO
3.3 V / 1.2 A
C2
22 µF
Components:
C1: Taiyo Yuden JMK316BJ226ML
C2: Taiyo Yuden JMK316BJ226ML
L1: Sumida CDRH5D28−6R2
Figure 17. Li-Ion to 3.3 V/1.2 A Conversion
VI
2.5 V to 6 V
C3
22 µF
Components:
C1: Taiyo Yuden JMK316BJ226ML
C2: Taiyo Yuden JMK316BJ226ML
L1: Sumida CDRH4D28C−4R7
TPS62040
2
3
1
6
4
VIN
VIN
EN
MODE
GND
8
SW
SW 7
FB 5
PGND 10
9
PGND
VO
1.8 V / 1.2 A
L1
4.7 µH
R1
470 kΩ
C1
33 µF
R2
180 kΩ
C2
100 µF
C4
22 µF
Figure 18. Li-Ion to 1.8 V/1.2 A Conversion Using the Adjustable Output Voltage Version
17
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SLVS463A − JUNE 2003 − REVISED OCTOBER 2003
THERMAL PAD MECHANICAL DATA
DGQ (S−PDSO−G10)
18
PowerPADt PLASTIC SMALL-OUTLINE
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