MIC44F18/19/20 6A High Speed MOSFET Drivers General Description Features The MIC44F18, MIC44F19 and MIC44F20 are highspeed single MOSFET drivers capable of sinking and sourcing 6A for driving capacitive loads. With delay times of less than 15ns and rise times into a 1000pF load of 10ns, these MOSFET drivers are ideal for driving large gate charge MOSFETs in power supply applications. The MIC44F18 is a non-inverting driver, the MIC44F19 is an inverting driver suited for driving PChannel MOSFETs and the MIC44F20 is an inverting driver for N-Channel MOSFETs. Fabricated using Micrel’s proprietary BiCMOS/DMOS process for low power consumption and high efficiency, the MIC44F18/19/20 translates TTL or CMOS input logic levels to output voltage levels that swing within 25mV of the positive supply or ground. Comparable bipolar devices are capable of swinging only to within 1V of the supply. The input supply voltage range of the MIC44F18/19/20 is 4.5V to 13.2V, making the devices suitable for driving MOSFETs in a wide range of power applications. Other features include an enable function, latch-up protection, and a programmable UVLO function. The MIC44F18/19/20 has a junction temperature range of –40°C to +125°C with exposed pad ePAD MSOP-8 and 2mm x 2mm MLF®-8 package options. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. • • • • • • • • • • 4.5V to 13.2V input operating range 6A peak output current High accuracy ±5% enable input threshold High speed switching capability 10ns rise time in 1000pF load <15ns propagation delay time Flexible UVLO function 4.2V internally set UVLO Programmable with external resistors Latch-up protection to >500mA reverse current on the output pin Enable function Thermally enhanced ePAD MSOP-8 package option Miniature 2mm x 2mm MLF®-8 package option Pb-free packaging Applications • Synchronous switch-mode power supplies • Secondary side synchronous rectification Typical Applications MOSFET Driver w/6.2V Programmed UVLO Internally Set MOSFET Driver with 4V MLF and MicroLeadFrame are registered trademarks of Amkor Technologies, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com January 2007 M9999-011207 Micrel, Inc. MIC44F18/19/20 Ordering Information Part Number Marking Configuration Junction Temp. Range Package Lead Finish D12 Non-Inverting –40°C to 125°C 2x2 MLF-8 Pb-Free Non-Inverting –40°C to 125°C ePAD MSOP-8 Pb-Free Inverting Output high when disabled –40°C to 125°C 2x2 MLF-8 Pb-Free Inverting Output high when disabled –40°C to 125°C ePAD MSOP-8 Pb-Free Inverting Output low when disabled –40°C to 125°C 2x2 MLF-8 Pb-Free Inverting Output low when disabled –40°C to 125°C ePAD MSOP-8 Pb-Free MIC44F18YML MIC44F18YMME MIC44F19YML D13 MIC44F19YMME MIC44F20YML D14 MIC44F20YMME Note: Over bar symbol may not be to scale. Pin Configuration OUT 1 8 OUT OUT 1 8 OUT VDD 2 7 GND VDD 2 7 GND 6 GND NC 3 6 GND 5 EN/UVLO NC 3 IN 4 EP IN 4 5 EN/UVLO 8-Pin ePAD MSOP (MME) EP 8-Pin MLF (ML) Pin Description Pin Number 1,8 Pin Name OUT Pin Function Driver Output 2 VDD Supply Input 3 NC No Connect 4 IN Input (Input): Logic high produces a high output voltage for the MIC44F18 and a low output voltage for the MIC44F19/20. Logic low produces a low output voltage for the MIC44F18 and a high output voltage for the MIC44F19/20. 5 EN/UVLO EN / Under-Voltage Lockout (Input): Pulling this pin below low disables the driver. When disabled, the output is in the off state (low for the MIC44F18/20 and high for the MIC44F19). Floating this pin enables the driver and the UVLO circuitry when VDD reaches the UVLO threshold. A resistor divider can set a different UVLO threshold voltage as shown on page 1 (See “Application Information” section for more details). 6,7 GND Ground EP GND Ground. Exposed Backside Pad. Logic Table EN/UVLO IN MIC44F18 OUTPUT MIC44F19 OUTPUT MIC44F20 OUTPUT 0 0 LOW HI LOW 0 1 LOW HI LOW 1 0 LOW HI HI 1 1 HI LOW LOW January 2007 2 M9999-011207 Micrel, Inc. MIC44F18/19/20 Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (Vdd). ………………………………….. 14V UVLO/Enable Voltage (VUVLO/EN)…………………....... 14V Input Voltage (VIN) …………… .. (VS + 0.1V) to (GND-5V) Output Voltage (VOUT) ……………………………........ 14V Junction Temperature (TJ)…………………... ..........150°C Ambient Storage Temperature (Tdd) …. . -65°C to +150°C Lead Temperature (10 sec).....................................300°C ESD Rating, Note 3 Pins 1,2,3,5,6,7,8................................................. 2KV Pin 4................................................................... 500V Supply Voltage (Vdd) ............................... 4.5V to 13.2V Package Thermal Impedance ePAD MSOP-8 (θJA)……………………… ...78°C/W 2x2 MLF-8L (θJA)…………………… ............93°C/W Operating Junction Temperature (TJ).................. 125°C Electrical Characteristics(4) 4.5V< Vdd< 13.2V; CL =1000pf; TA = 25°C, bold values indicate –40°C< Tj < +125°C, unless noted. Symbol Parameter Condition Min Power Supply Vdd Supply Voltage Range EN/UVLO VEN Max Units 13.2 V High Output Quiescent Current VIN = 5V (MIC44F18), VIN = 0V (MIC44F19/20) 2.5 mA Low Output Quiescent Current VIN = 0V (MIC44F18), VIN = 5V (MIC44F19/20) 2.5 mA Shutdown Current VEN = 0V 200 µA IS ISD Typ 4.5 Enable Threshold 1.3 Enable Hysteresis 1.4 1.5 120 VEN = open VDD rising V mV VUVLO Under-Voltage Lockout Threshold (Internally Set) VUVLO Under-Voltage Lockout Threshold (Externally Set) VDD rising Input VIN Input Voltage Range Steady State Voltage (note 5) VIH Logic 1 Input Voltage Ta=25C (+/-5%) Over temperature range (+/-10%) 1.615 1.53 1.7 1.7 1.785 1.87 V VIL Logic 0 Input Voltage Ta=25C (+/-5%) Over temperature range (+/-10%) 1.45 1.377 1.53 1.53 1.607 1.683 V IIN Input Current 4.5V< VIN< 10V 5 µA 3.6 UVLO Hysteresis January 2007 4.2 4.4 370 VEN 3 mV Vdd (MAX) 0 V V Vdd M9999-011207 Micrel, Inc. MIC44F18/19/20 Electrical Characteristics (cont.) Symbol Parameter Condition Output VOH High Output Voltage See Figure 1 VOL RO IPEAK IR Min Typ Max VS 0.025 Units V Low Output Voltage See Figure 1 0.025 V Output Resistance, Output High IOUT = 100mA, Vdd = 12V IOUT = 100mA, Vdd = 5V 2 3 Ω Output Resistance, Output Low IOUT = 100mA, Vdd = 12V IOUT = 100mA, Vdd = 5V 2 3 Ω Peak Output Sink Current Vdd=12V 6 A Peak Output Source Current VS=12V 6 A Latch-Up Protection Withstand Reverse Current >500 mA Switching Time tR Rise Time VS=12V, CL=1000pF See Figure 1 and 2 10 20 nS tF Fall Time VS=12V, CL=1000pF See Figure 1 and 2 10 20 nS tD1 Delay Time VS=12V, CL=1000pF See Figure 1 and 2 15 35 nS tD2 Delay Time VS=12V, CL=1000pF See Figure 1 and 2 13 35 nS tPW Minimum Input Pulse Width VS=12V See Figure 1 and 2 50 nS fMAX Maximum Input Frequency VS=12V See Figure 1 and 2 Note 6 MHz Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. 4. Specification for packaged product only. 5. The device is protected from damage when -5V< Vin< 0V. However, 0V is the recommended minimum continuous VIL voltage. See the applications section for additional information. 6. See applications section for information on the maximum operating frequency. January 2007 4 M9999-011207 Micrel, Inc. MIC44F18/19/20 Typical Characteristics January 2007 5 M9999-011207 Micrel, Inc. MIC44F18/19/20 Typical Characteristics cont. January 2007 6 M9999-011207 Micrel, Inc. MIC44F18/19/20 Timing Diagram Functional Diagram Figure 1. MIC44F18/19/20 Functional Block Diagram January 2007 7 M9999-011207 Micrel, Inc. MIC44F18/19/20 Because the external resistors are parallel with the internal resistors, it is important to keep the value of the external resistors at least 10 times lower than the typical values of the internal resistors. This prevents the internal resistors from affecting the accuracy of the enable calculation as well as preventing the large tolerance of the internal resistors from affecting the tolerance of the enable voltage setting. Functional Description The MIC44F18/19/20 family of drivers are high speed, high current drivers that are designed to drive P-channel and N-channel MOSFETs. The drivers come in both inverting and non-inverting versions. The block diagram of the MIC44Fxx driver is shown in Figure 1. The MIC44F18 is a non-inverting driver. When disabled, the VOUT pin is pulled low. The MIC44F19 is an inverting driver that is optimized to drive P-channel MOSFETs. When disabled, the VOUT pin is pulled high, which turns off the P-channel MOSFET. The MIC44F20 is an inverting driver, whose VOUT pin is pulled low when disabled. This allows it to drive an N-channel MOSFETs and turn it off when the driver is disabled. The logic table below summarizes the driver operation. EN/UVLO IN MIC44F18 OUTPUT MIC44F19 OUTPUT MIC44F20 OUTPUT 0 0 1 1 0 1 0 1 LOW LOW LOW HI HI HI HI LOW LOW LOW HI LOW Startup and UVLO The UVLO circuit disables the output until the VDD supply voltage exceeds the UVLO threshold. Hysteresis in the UVLO circuit prevents noise and finite circuit impedance from causing chatter during turn-on and turnoff. Figure 2. UVLO Circuit Input Stage The MIC44Fxx family of drivers have a high impedance, TTL compatible input stage. The tight tolerance of the input threshold makes it compatible with CMOS devices powered from any supply voltage between 3V and VDD. Hysteresis on the input pin improves noise immunity and prevents input signals with slow rise times from falsely triggering the output. The amplitude of the input voltage has no effect on the supply current draw of the driver. As shown in figure 2, with the EN/UVLO pin open, an internal resistor divider senses the VDD voltage and the UVLO threshold is set at the minimum operating voltage of the driver. The driver can be set to turn on at a higher voltage by adding an external resistor to the UVLO pin. The input voltage signal may go up to -5V below ground without damaging the driver or causing a latch up condition. Negative input voltages 0.7V below ground or greater will cause an increase in propagation delay. With an external divider, the VDD turn on (rising VDD) threshold is calculated as: ⎡ R1 ⎤ VDD enable = VTH × ⎢1 + ⎥ ⎣ R2 ⎦ ⎡ R1 ⎤ VDD hysteresis = VHyst × ⎢1 + ⎥ ⎣ R2 ⎦ where : VTH = Enable Threshold Voltage VDD Hysteresis = Hysteresis Voltage at the VDD pin VHyst = Enable Hysteresis Voltage January 2007 8 M9999-011207 Micrel, Inc. MIC44F18/19/20 Output Driver Section A block diagram of the low-side driver is shown in Figure 3. Low driver impedances allow the external MOSFET to be turned on and off quickly. The rail-to-rail drive capability of the output ensures a low RDSON from the external MOSFET. Redundant Vout pins lower the driver circuit impedance, which helps increase the drive current and minimize LC circuit ringing between the MOSFET gate and driver output. The slew rate of the output is non-adjustable and depends only on the VDD voltage and how much capacitance is present at the VOUT pin. The slew rate at the MOSFET gate can be adjusted by adding a resistor between the MOSFET gate and the driver output. Figure 3. Output Driver Section January 2007 9 M9999-011207 Micrel, Inc. MIC44F18/19/20 Application Information Power Dissipation Considerations Power dissipation in the driver can be separated into two areas: • Output driver stage dissipation • Quiescent current dissipation used to supply the internal logic and control functions. E = 21 × Ciss × VGS 2 but Q = C× V so E = 1/2 × Qg × VGS where Ciss is the total gate capacitanc e of the MOSFET Output Driver Stage Power Dissipation Power dissipation in the output driver stage is mainly caused by charging and discharging the gate to source and gate to drain capacitance of the external MOSFET. Figure 4 shows a simplified equivalent circuit of the MIC44F18 driving an external MOSFET. Figure 5. GATE Charge Figure 4. Output Driver Stage Power Dissipation Dissipation During the External MOSFET Turn-On Energy from capacitor CVDD is used to charge up the input capacitance of the MOSFET (CGD and CGS). The energy delivered to the MOSFET is dissipated in the three resistive components, RON, RG and RG_FET. RON is the on resistance of the upper driver MOSFET in the MIC44F18. RG is the series resistor (if any) between the driver IC and the MOSFET. RG_FET is the gate resistance of the MOSFET. RG_FET is usually listed in the power MOSFET’s specifications. The ESR of capacitor CB and the resistance of the connecting etch can be ignored since they are much less than RON and RG_FET. The effective capacitance of CGD and CGS is difficult to calculate since they vary non-linearly with ID, VGS, and VDS. Fortunately, most power MOSFET specifications include a typical graph of total gate charge vs. VGS. Figure 5 shows a typical gate charge curve for an arbitrary power MOSFET. This illustrates that for a gate voltage of 10V, the MOSFET requires about 23.5nC of charge. The energy dissipated by the resistive components of the gate drive circuit during turn-on is calculated as: January 2007 10 The same energy is dissipated by ROFF, RG and RG_FET when the driver IC turns the MOSFET off. Assuming Ron is approximately equal to ROFF, the total energy and power dissipated by the resistive drive elements is: EDRIVER = QG × VGS and PDRIVER =QG ×VGS × fS Where EDRIVER is the energy dissipated per switching power PDRIVER is the power dissipated by switching the MOSFET on and off QG is the total GATE charge at VGS VGS is the GATE to SOURCE voltage on the MOSFET fS is the switching frequency of the GATE drive circuit The power dissipated inside the MIC4100/4101 is equal to the ratio of RON & ROFF to the external resistive losses in RG and RG_FET. Letting RON = ROFF, the power dissipated in the MIC44F18 due to driving the external MOSFET is: M9999-011207 Micrel, Inc. Pdiss drive = PDRIVER MIC44F18/19/20 RON RON + RG + RG _ FET Supply Current Power Dissipation Power is dissipated in the MIC44F18 even if is there is nothing being driven. The supply current is drawn by the bias for the internal circuitry, the level shifting circuitry and shoot-through current in the output drivers. The supply current is proportional to operating frequency and the VDD voltage. The typical characteristic graphs show how supply current varies with switching frequency and supply voltage. The power dissipated by the MIC44F18 due to supply current is Pdiss SUPPLY = VDD × I DD Figure 6A. Driver Power Dissipation Total Power Dissipation and Thermal Considerations Total power dissipation in the Driver equals the power dissipation caused by driving the external MOSFETs plus the supply current. PdissTOTAL = Pdiss SUPPLY + Pdiss DRIVE The die temperature may be calculated once the total power dissipation is known. TJ = T A + PdissTOTAL × θ JA Where TA is the Maximum ambient temperature TJ is the junction temperature (°C) PdissTOTAL is the power dissipation of the Driver θJC is the thermal resistance from junction-toambient air (°C/W) The following graphs help determine the maximum gate charge that can be driven with respect to switching frequency, supply voltage and ambient temperature. Figure 6A shows the power dissipation in the driver for different values of gate charge with VDD=5V. Figure 6B shows the power dissipation at VDD=12V. Figure 6C show the maximum power dissipation for a given ambient temperature for the MLF and ePad packages. Figure 6B. Driver Power Dissipation The maximum operating frequency of the driver may be limited by the maximum power dissipation of the driver package. Figure 6C. Max. Driver Power Dissipation January 2007 11 M9999-011207 Micrel, Inc. MIC44F18/19/20 Propagation Delay and Delay Matching and Other Timing Considerations Fast propagation delay between the input and output drive waveform is desirable. It improves overcurrent protection by decreasing the response time between the control signal and the MOSFET gate drive. Minimizing propagation delay also minimizes phase shift errors in power supplies with wide bandwidth control loops. Care must be taken to insure the input signal pulse width is greater than the minimum specified pulse width. An input signal that is less than the minimum pulse width may result in no output pulse or an output pulse whose width is significantly less than the input. Decoupling and Bootstrap Capacitor Selection Decoupling capacitors are required for proper operation by supplying the charge necessary to drive the external MOSFETs as well as minimizing the voltage ripple on the supply pins. Ceramic capacitors are recommended because of their low impedance and small size. Z5U type ceramic capacitor dielectrics are not recommended due to the large change in capacitance over temperature and voltage. A minimum value of 0.1µf is required for each of the capacitors, regardless of the MOSFETs being driven. Larger MOSFETs may require larger capacitance values for proper operation. The voltage rating of the capacitors depends upon the supply voltage, ambient temperature and the voltage derating used for reliability. Placement of the decoupling capacitors is critical. The bypass capacitor for VDD should be placed as close as possible between the VDD and VSS pins. The etch connections must be short, wide and direct. The use of a ground plane to minimize connection impedance is recommended. Refer to the section on layout and component placement for more information. Grounding, Component Placement and Circuit Layout Nanosecond switching speeds and ampere peak currents in and around the MOSFET driver requires proper placement and trace routing of all components. Improper placement may cause degraded noise immunity, false switching and excessive ringing. Figure 7 shows the critical current paths when the driver outputs go high and turn on the external MOSFETs. It also helps demonstrate the need for a low impedance ground plane. Charge needed to turn-on the MOSFET gates comes from the decoupling capacitors CVDD. Current in the gate driver flows from CVDD through the internal driver, into the MOSFET gate and out the source. The return connection back to the decoupling capacitor is made through the ground plane. Any inductance or resistance in January 2007 12 the ground return path causes a voltage spike or ringing to appear on the source of the MOSFET. This voltage works against the gate drive voltage and can either slow down or turn off the MOSFET during the period when it should be turned on. IN Figure 7. Critical Current Paths for High Driver Outputs Figure 8 shows the critical current paths when the driver outputs go low and turn off the external MOSFETs. Short, low impedance connections are important during turn-off for the same reasons given in the turn-on explanation. Current from the VDD supply replenishes charge in the decoupling capacitor, CVdd. IN Figure 8. Critical Current Paths for High Driver Outputs The following circuit guidelines should be adhered to for optimum circuit performance: 1. The VCC bypass capacitor must be placed close to the VDD and ground pins. It is critical that the etch length between the decoupling capacitor and the VDD & GND pins be minimized to reduce pin inductance. 2. A ground plane is recommended to minimize parasitic inductance and impedance of the return paths. The MIC44F18 family of drivers is capable of high peak currents and very fast transition times. Any impedance between the driver, the decoupling capacitors and the external MOSFET will degrade the performance of the circuit. 3. Trace out the high di/dt and dv/dt paths, as shown in Figures 7 and 8 and minimize etch length and loop area for these connections. Minimizing these parameters decreases the parasitic inductance and the radiated EMI generated by fast rise and fall times. M9999-011207 Micrel, Inc. MIC44F18/19/20 Package Information 8-Pin ePad MSOP (MME) 8-Pin 2mm x 2mm MLF (ML) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. January 2007 13 M9999-011207