3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD Micrel, Inc. FEATURES SY88983V SY88983V DESCRIPTION ■ Multi-Rate up to 3.2Gbps operation The SY88983V low-power limiting post amplifier is designed for use in fiber optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88983V quantizes these signals and outputs typically 800mVpp voltage-limited waveforms. The SY88983V operates from a single +3.3V ±10% or +5V ±10% power supply, over the industrial temperature of –40°C to +85°C. With its wide bandwidth and high gain, signals with data rates up to 3.2Gbps and as small as 10mVpp can be amplified to drive devices with CML inputs or AC-coupled PECL inputs. The SY88983V generates a signal detect (SD) opencollector TTL output with internal 5kΩ pull-up resistor. A programmable signal detect level set pin (SDLVL) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold set by SDLVL and de-asserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a lossof-signal condition. EN de-asserts the true output signal without removing the input signal. Typically, 4.6dB SD hysteresis is provided to prevent chattering. All support documentation can be found on Micrel’s web site at www.micrel.com. ■ Wide gain-bandwidth product • 38dB differential gain • 2.2GHz 3dB bandwidth ■ Low noise 50Ω CML data outputs • 800mVpp output swing • 60ps edge rates • 5psrms typ. random jitter • 15pspp typ. deterministic jitter ■ Chatter-free Signal Detect (SD) output • 4.6dB electrical hysteresis • OC-TTL output with internal 5kΩ pull-up resistor ■ Programmable SD sensitivity using single external resistor ■ Internal 50Ω data input termination ■ TTL EN input allows feedback from SD ■ Wide operating range • Single 3.3V ±10% or 5V ±10% power supply • –40°C to +85°C industrial temperature range ■ Available in tiny 10-pin MSOP (3mm) and 16-pin MLF™ (3mm × 3mm) packages ■ NOT RECOMMENDED for New Designs! APPLICATIONS ■ 1.25Gbps and 2.5Gbps Gigabit Ethernet ■ 1.062Gbps and 2.125Gbps Fibre Channel ■ 155Mbps, 622Mbps, 1.25Gbps and 2.5Gbps SONET/SDH FUNCTIONAL BLOCK DIAGRAM ■ Gigabit interface converter (GBIC) ■ Small form factor (SFF) and small form factor pluggable (SFP) transceivers ■ Parallel 10G Ethernet DIN ■ High-gain line driver and line receiver 50Ω Limiting Amplifer DOUT CML Buffer /DIN /DOUT TYPICAL PERFORMANCE VREF 3.3V, 25°C, 10mVPP Input @2.5Gbps 223–1 PRBS, RLOAD = 50Ω to VCC VCC GND TTL Buffer VCC —1.3V EN Level Detect VCC 2.8kΩ Output Swing (75mV/div.) 5kΩ SDLVL OC-TTL Buffer SD TIME (100ps/div.) MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. February 2005 1 M9999-020205 [email protected] or (408) 955-1690 Micrel, Inc. SY88983V PACKAGE/ORDERING INFORMATION VCC EN SDLVL VCC Ordering Information 16 15 14 13 DIN 1 12 GND 2 11 GND /DIN 3 4 10 9 DOUT Part Number Package Type Operating Range Package Marking SY88983VKI K10-1 Industrial 983V SY88983VKITR(1) GND GND /DOUT 5 6 7 8 K10-1 Industrial 983V SY88983VMI MLF-16 Industrial 983V SY88983VMITR(1) MLF-16 Industrial 983V VCC VREF SD VCC Note: 1. Tape and Reel. 16-Pin MLF™ (MLF-16) EN 1 10 VCC DIN 2 9 DOUT /DIN 3 8 /DOUT VREF 4 7 SD SDLVL 5 6 GND 10-Pin MSOP (K10-1) PIN DESCRIPTION Pin Number (MSOP) Pin Number (MLF™) Pin Name Type 1 15 EN TTL Input: Default is high. 2, 3 1, 4 DIN, /DIN Differential Data Input 4 6 VREF 5 14 SDLVL Input: Default is maximum sensitivity. 6 2, 3, 10, 11, Exposed Pad GND Ground 7 7 SD Open-Collector: TTL Output with internal 5kΩ pull-up resistor. 8, 9 9, 12 DOUT, /DOUT Differential CML Output 10 5, 8, 13, 16 VCC Power Supply February 2005 Pin Function Enable: De-asserts true data output when low. Differential data input. Each pin internally terminates to VREF through 50Ω. Reference Voltage: Bypass with 0.01µF low ESR capacitor from VREF to VCC to stabilize SDLVL and VREF. Signal Detect Level Set: A resistor from this pin to VCC sets the threshold for the data input amplitude at which the SD output will be asserted. Device ground. Exposed pad must be connected to same potential as ground pins for MLF-16. 2 Signal Detect: Asserts high when the data input amplitude rises above the threshold set by SDLVL. Differential data output. Positive power supply. Bypass with 0.1µF0.01µF low ESR capacitors. 0.01µF capacitors should be as close to VCC pins as possible. M9999-020205 [email protected] or (408) 955-1690 Micrel, Inc. SY88983V Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ....................................... 0V to +7.0V EN, SDLVL Voltage .................................................0 to VCC DIN, /DIN Current ...................................................... ±10mA DOUT, /DOUT Current ................................................ ±25mA SD Current ................................................................. ±5mA VREF Current .............................................................. ±1mA Storage Temperature (TS) ....................... –65°C to +150°C Lead Temperature (soldering, 10 sec.) ..................... 220°C Supply Voltage (VCC) .............................. +3.0V to +3.6V or ............................................................ +4.5V to +5.5V Ambient Temperature (TA) ......................... –40°C to +85°C Junction Temperature (TJ) ....................... –40°C to +120°C Package Thermal Resistance(3) MLF™ (θJA) Still-Air .................................................... 61°C/W (ψJB) ................................................................ 38°C/W MSOP (θJA) Still-Air .................................................. 113°C/W (ψJB) ................................................................ 74°C/W DC ELECTRICAL CHARACTERISTICS VCC = 3.0V to 3.6V or 4.5V to 5.5V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C; typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition Min Typ Max Units ICC Power Supply Current(4) 3.3V 5V 19 21 28 31 mA mA ICC Power Supply Current(5) 3.3V 5V 32 38 53 58 mA mA VREF VREF Voltage SDLVL SDLVL Level VOH Output HIGH Voltage Note 6 VOL Output LOW Voltage Note 6 VOFFSET Differential Output Offset ZO Single-Ended Output Impedance 40 ZI Single-Ended Input Impedance 40 VCC –1.3 VREF VCC–0.020 VCC–0.005 V VCC V VCC V VCC–0.400 VCC–0.275 V ±80 mV 50 60 Ω 50 60 Ω Max Units VCC V 0.5 V TTL DC ELECTRICAL CHARACTERISTICS VCC = 3.0V to 3.6V or 4.5V to 5.5V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C; typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition Min VOH SD Output HIGH Level Sourcing 100µA 2.4 VOL SD Output LOW Level Sinking 2mA VIH EN Input HIGH Voltage VIL EN Input LOW Voltage IIH EN Input HIGH Current VIN = 2.7V VIN = VCC IIL EN Input LOW Current VIN = 0.5V Typ 2.0 V 0.8 V 20 100 µA µA –0.3 mA Notes: 1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Thermal performance assumes use of 4-layer PCB. If applicable, exposed pad must be soldered (or equivalent) to the device’s most negative potential on the PCB. 4. Excludes current of CML output stage. See “Detailed Description.” 5. Total device current with no output load. 6. Output levels are based on a 50Ω to VCC load impedance. If the load impedance is different, the output level will be changed. February 2005 3 M9999-020205 [email protected] or (408) 955-1690 Micrel, Inc. SY88983V AC ELECTRICAL CHARACTERISTICS VCC = 3.0V to 3.6V or 4.5V to 5.5V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C; typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition Min Typ Max Units HYS SD Hysteresis Note 7 2 4.6 8 dB PSRR Power Supply Rejection Ratio 35 tOFF SD Release Time 0.1 0.5 µs tON SD Assert Time 0.2 0.5 µs tr, tf Differential Output Rise/Fall Time (20% to 80%) 60 120 ps dB Note 8 tJITTER Deterministic Random VID Differential Input Voltage Swing VOD Differential Output Voltage Swing Note 10 550 VSR SD Sensitivity Range Note 11 10 AV(Diff) Differential Voltage Gain B–3dB 3dB Bandwidth S21 Single-Ended Small Signal-Gain Note 9 15 5 10 32 26 psp-p psrms 1800 800 mVp-p mVp-p 50 mVp-p 38 dB 2.2 GHz 32 dB Notes: 7. Electrical signal. 8. With input signal VID > 50mVp-p and 50Ω load. 9. Deterministic jitter measured using K28.5 pattern at 2.488Gbps, VID = 10mVp-p. Random jitter measured using K28.7 pattern at 2.488Gbps, VID = 10mVp-p. 10. Input is a 200MHz square wave, tr < 300ps, 50Ω load. VID ≥ 14mVp-p. 11. This is the detectable range of input amplitudes that can de-assert SD. The input amplitude to assert SD is 2–8dB higher than the de-assert amplitude. See “Typical Operating Characteristics” for a graph showing how to choose a particular RSDLVL for a particular SD de-assert, and its associated assert, amplitude. TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, GND = 0V, TA = 25°C unless otherwise stated. 90 SD Assert/Deassert Level vs. RSDLVL 80 VID (mVP-P) 70 ASSERT 60 50 40 30 20 DEASSERT 10 0 10 February 2005 100 1000 10000 100000 RSDLVL 4 M9999-020205 [email protected] or (408) 955-1690 Micrel, Inc. SY88983V DETAILED DESCRIPTION Signal Detect The SY88983V generates a chatter-free signal detect (SD) open-collector TTL output with internal 5kΩ pull-up resistor as shown in Figure 5. SD is used to determine that the input amplitude is large enough to be considered a valid input. SD asserts high if the input amplitude rises above the threshold set by SDLVL and de-asserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a loss-of-signal condition. EN de-asserts low the true output signal without removing the input signals. Typically, 4.6dB SD hysteresis is provided to prevent chattering. Signal Detect-Level Set A programmable signal detect-level set pin (SDLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and SDLVL sets the voltage at SDLVL. This voltage ranges from VCC to VREF. The external resistor creates a voltage divider between VCC and VREF as shown in Figure 6. If desired, an appropriate external voltage may be applied rather than using a resistor. The smaller the external resistor, implying a smaller voltage difference from SDLVL to VCC, lowers the SD sensitivity. Hence, larger input amplitude is required to assert SD. “Typical Operating Characteristics” shows the relationship between the input amplitude detection sensitivity and the SDLVL setting resistor. Hysteresis The SY88983V provides typically 4.6dB SD electrical hysteresis. By definition, a power ratio measured in dB is 10log(power ratio). Power is calculated as V2IN/R for an electrical signal. Hence, the same ratio can be stated as 20log(voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power and hence, the ratios also change linearly. Therefore, the optical hysteresis in dB is half the electrical hysteresis in dB given in the data sheet. The SY88983V provides typically 2.3dB SD optical hysteresis. As the SY88983V is an electrical device, this data sheet refers to hysteresis in electrical terms. With 4.6dB SD hysteresis, a voltage factor of 1.7 is required to assert SD from its de-assert value. The SY88983V low power limiting post amplifier operates from a single +3.3V or +5V power supply, over temperatures from –40°C to +85°C. Signals with data rates up to 3.2Gbps and as small as 10mVp-p can be amplified. Figure 1 shows the allowed input voltage swing. The SY88983V generates an SD output, allowing feedback to EN for output stability. SDLVL sets the sensitivity of the input amplitude detection. Input Amplifier/Buffer The SY88983V’s inputs are internally terminated with 50Ω to VREF. Unless they are not affected by this internal termination scheme, upstream devices need to be AC-coupled to the SY88983V’s inputs. Figure 2 shows a simplified schematic of the input stage. The high sensitivity of the input amplifier allows signals as small as 10mVp-p to be detected and amplified. The input amplifier allows input signals as large as 1800mVp-p. Input signals are linearly amplified with a typically 38dB differential voltage gain. Since it is a limiting amplifier, the SY88983V outputs typically 800mV p-p voltage-limited waveforms for input signals that are greater than 10mVp-p. Applications requiring the SY88983V to operate with highgain should have the upstream TIA placed as close as possible to the SY88983V’s input pins to ensure the best performance of the device. Output Buffer The SY88983V’s CML output buffer is designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external 50Ω resistor to VCC or equivalent for each output pin provides this. Figure 3 shows a simplified schematic of the output stage and includes an appropriate termination method. Of course, driving a downstream device with a CML input that is internally terminated with 50Ω to VCC eliminates the need for external termination. As noted in the previous section, the amplifier outputs typically 800mVp-p waveforms across 25Ω total loads. The output buffer, thus, switches typically 16mA tailcurrent. Figure 4 shows the power supply current measurement, which excludes the 16mA tail-current. February 2005 5 M9999-020205 [email protected] or (408) 955-1690 Micrel, Inc. SY88983V DATA+ 5mV (Min.) DATA– 900mV (Max.) (DATA+) – (DATA–) 10mVp-p (Min.) VIS(mV) VID(mVp-p) 1800mVp-p (Max.) Figure 1. VIS and VID Definition VCC 0.1µF VREF VCC VCC VCC 50Ω 50Ω 50Ω 50Ω 50Ω 0.1µF DOUT Z0 = 50Ω 50Ω /DOUT 0.1µF Z0 = 50Ω DIN AC-Coupling Capacitors 0.1µF AC-Coupling Capacitors /DIN 16mA ESD STRUCTURE ESD STRUCTURE GND GND Figure 2. Input Structure Figure 3. Output Structure VCC VCC 5kΩ SD ICC 50Ω 16mA 50Ω Figure 5. SD Output Structure ESD STRUCTURE VCC RSDLVL SDLVL 16mA 2.8kΩ VREF GND Figure 6. SDLVL Setting Circuit Figure 4. Power Supply Current Measurement February 2005 6 M9999-020205 [email protected] or (408) 955-1690 Micrel, Inc. SY88983V TYPICAL APPLICATIONS CIRCUIT VCC SD EN 0.1µF DIN From Transimpedance Amp. DOUT SY88983V /DIN 0.1µF SDLVL GND February 2005 VCC To CDR /DOUT VREF 200kΩ 7 0.1µF 0.1µF 0.1µF M9999-020205 [email protected] or (408) 955-1690 Micrel, Inc. SY88983V 10 LEAD MSOP (K10-1) Rev. 00 February 2005 8 M9999-020205 [email protected] or (408) 955-1690 Micrel, Inc. SY88983V 16 LEAD MicroLeadFrame™ (MLF-16) Rev.03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. February 2005 9 M9999-020205 [email protected] or (408) 955-1690