[ /Title (CD74H C4049, CD74H C4050) /Subject (High Speed CMOS Logic Hex CD74HC4049, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205A High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised June 1999 Features Description • Typical Propagation Delay: 6ns at VCC = 5V, CL = 15pF, TA = 25oC The CD74HC4049 and CD74HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which convert high-level logic to a low-level logic while operating off the low-level logic supply. For example, 15-V input pulse levels can be downconverted to 0-V to 5-V logic levels. The modified input protection structure protects the input from negative electrostatic discharge. These parts also can be used as simple buffers or inverters without level translation. The CD74HC4049 and CD74HC4050 are enhanced versions of equivalent CMOS types. • High-to-Low Voltage Level Converter for up to Vl = 16V • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . –55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs Ordering Information • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. CD74HC4049E –55 to 125 16 Ld PDIP E16.3 CD74HC4050E –55 to 125 16 Ld PDIP E16.3 CD74HC4049M –55 to 125 16 Ld SOIC M16.15 CD74HC4050M –55 to 125 16 Ld SOIC M16.15 CD74HC4050PW –55 to 125 16 Ld TSSOP NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to the M suffix or the R suffix to the PW package to obtain the variant in the tape and reel. 2. Wafer and die is available which meets all electrical specifications. Please contact your local sales office or customer service for ordering information. Pinout CD74HC4049, CD74HC4050 (PDIP, SOIC, TSSOP) TOP VIEW 4049 4050 VCC VCC 1 16 NC 4050 NC 4049 1Y 1Y 2 15 6Y 6Y 1A 1A 3 14 6A 6A 2Y 2Y 4 13 NC NC 2A 2A 5 12 5Y 5Y 3Y 3Y 6 11 5A 5A 3A 3A 7 10 4Y 4Y GND GND 8 9 4A 4A CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 1999 Texas Instruments Incorporated 1 CD74HC4049, CD74HC4050 Functional Diagram 4050 4049 1 16 VCC 2 6Y 3 6A 4 13 2Y NC 5 NC 12 2A 5Y 6 3Y 6Y 14 1A 2Y 4050 15 1Y 1Y 4049 NC 11 3Y 5A 7 5Y 10 4Y 3A 8 9 GND 4A Logic Diagrams HC4049 A HC4050 A Y 2 Y CD74HC4049, CD74HC4050 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V DC Input Diode Current, IIK For VI < –0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < –0.5V or VO > VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > –0.5V or VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . –65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions VCC Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .–55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) VOLTAGE RELATIONSHIPS MAXIMUM LIMITS Vl +7V +16V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS 25oC –40oC TO 85oC –55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input Voltage VIL 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V High Level Output Voltage CMOS Loads VOH PARAMETER HC TYPES - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC - 6 - - 1.8 - 1.8 - 1.8 V –0.02 2 1.9 - - 1.9 - 1.9 - V –0.02 4.5 4.4 - - 4.4 - 4.4 - V –0.02 6 5.9 - - 5.9 - 5.9 - V –4 4.5 3.98 - - 3.84 - 3.7 - V –5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA 15 - 6 - - ±0.5 - ±5 - ±5 VCC or GND 0 6 - - 2 - 20 - 40 NOTE: For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. 3 µA CD74HC4049, CD74HC4050 Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay, nA to nY HC4049 nA to nY HC4050 Transition Times (Figure 1) Input Capacitance Power Dissipation Capacitance (Notes 4, 5) SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF tTLH, tTHL –40oC TO 85oC 25oC –55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 85 - 105 - 130 ns 4.5 - - 17 - 21 - 26 ns 6 - - 14 - 18 - 22 ns CL = 15pF 5 - 6 - - - - - ns CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns CI - - - - 10 - 10 - 10 pF CPD - 5 - 35 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per gate. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuit and Waveform tr = 6ns tf = 6ns VCC 90% 50% 10% INPUT GND tTHL tTLH 90% 50% 10% INVERTING OUTPUT tPLH tPHL FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 4 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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