TESDH5V0A Ultra low capacitance ESD Protection Array Small Signal Diode 2510P10 (DSON10) A E B Features F Meet IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact) D C Meet IEC61000-4-4 (EFT) rating. 40A (5/50ήs) Meet IEC61000-4-5 (Lightning) rating. 1A (8/20μs) G Protects four high speed I/O lines Low capacitance: 0.5pF typical (I/O to I/O) H Working Voltage : 5V Pb free version, RoHS compliant, and Halogen free I Unit (mm) Unit (inch) Min Max Min A 2.40 2.60 0.094 0.102 B 0.90 1.10 0.035 0.043 Dimensions Mechanical Data Case : 2510P10 (DSON10) standard package, molded plastic Terminal: Matte tin plated, lead free, solderable per MIL-STD-202, Method 202 guaranteed C 0.02 BSC 0.50 BSC D 0.025 BSC 0.53 BSC E High temperature soldering guaranteed: 260°C/10s Max 0.30 0.43 0.01 F 0.45 0.55 0.02 0.02 0.02 Molding Compound Flammability Rating : UL 94V-O G Weight :15 mg (approximately) 0.50 0.65 0.020 0.026 H 0.15 0.25 0.006 0.010 Marking Code : P524 I 0.35 0.45 0.014 0.018 Applications Pin Configutation High Defi nition Multi-Media Interface (HDMI) 10 Output Digital Visual Interface (DVI) 9 8 7 Output GND Output 6 Output PCI Express Serial ATA USB 3.0 Super speed interface Ordering Information Part No. TESDH5V0A Package Packing 2510P10 3K / 7" Reel 1 IN#1 Packing Code Marking RDG P524 2 IN#2 3 GND 4 IN#3 5 IN#4 Note : Output line ( No internal connection) Maximum Ratings and Electrical Characteristics Rating at 25°C ambient temperature unless otherwise specified. Maximum Ratings Type Number Symbol Value Units Peak Pulse Power (tp=8/20μs waveform) PPP 150 W Peak Pulse Current (tp = 8/20μs) IPP 1 A ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) VESD ±15 ±8 KV TJ, TSTG Junction and Storage Temperature Range . -55 to + 150 °C . Electrical Characteristics Type Number Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage Junction Capacitance IR= VR= IPP= 1mA 5V 1A VR=0V, f=1.0MHz Symbol VRWM Min - Max 5 V(BR) 6 - V IR Vc CJ - 1 15 uA V pF 1 (Typ.) Units V Version : B11 TESDH5V0A Ultra low capacitance ESD Protection Array Small Signal Diode Rating and Sharacteristic Curves FIG 1 Non-Repetitive Peak Pulse Power vs. Pulse Time FIG 2 Pulse Waveform 110 10 Waveform Parameters: tr = 8μs, td = 20μs 90 Percent of IPP Peak Pulse Power Ppp (KW) 100 1 80 70 60 e-1 50 40 0.1 td=Ipp/2 30 20 10 0.01 0.1 1 10 100 0 1000 0 5 Pulse Duration (us) 10 15 20 25 30 Time (us) FIG 3 Admissible Power Dissipation Curve FIG 4 Typical Junction Capacitance 120 1.5 Normalized Capacitance Power Rating (%)) 100 80 60 40 1 0.5 20 f f==1.0MHz 1.0MHz 0 0 0 20 40 60 80 100 120 140 160 180 0 1 2 Ambient Tempeatature (oC) 4 30 30 3 25 25 0 3 1 2 4 -3 20 (dB) 20 -6 15 15 10 -9 10 5 -12 Waveform Parameters: tr = 8μs, td = 20μs 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Peak Pulse Current (A) 5 FIG 6 Insertion Loss FIG 5 Clamping Voltage vs. Peak Pulse Current Clamping Voltage (V) 3 Reverse Voltage(V) 5 5.5 6 0 -15 0.1 1.E+06 5 1:-0.073dB 900MHz 2:-0.065dB 1.8GHz 3:-0.107dB 2.5GHz 4: -0.6477dB 3.0GHz 5:-0.18073dB 4.3GHz 1 1.E+07 10 1.E+08 100 1.E+09 1000 1.E+10 f(Hz) Version : B11 TESDH5V0A Ultra low capacitance ESD Protection Array Small Signal Diode Applications Information Designed for protection of high-speed interfaces such as HDMI Ultra low capacitance between the pairs while being rated to handle >±8kV ESD contact discharges and >±15kV air discharge Each device is in a leadless package that is less than 1.1mm wide Designed such that the traces flow straight through the device, The narrow package and flow-through design reduces discontinuities and minimizes impact on signal integrity TESDH5V0A is ultra low capacitance ESD protection array designed to protect high speed data interfaces. This series has been specifically designed to protect sensitive components which are connected to high-speed data and transmission lines from overvoltage caused by ESD, CDE (Cable Discharge Events), and EFT (electrical fast transients) The combination of small size, low capacitance, and high level of ESD protection makes them a flexible solution for applications of high speed interface, ex HDMI, DisplayPortTM, MDDI, and eSATA interfaces. Circuit Board Layout Recommendations for HDMI application The PCB traces are used to connect the pin pairs for each line (pin 1 to pin 10, pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6) Signal line enters at pin 1 and exits at Pin 10 and the PCB trace connects pin 1 and 10 together. Ground is connected at pins 3 and 8. One large ground pad should be used in lieu of two separate pads TESDH5V0A TMDS_D2+ TMDS GND TMDS_GND TMDS_D2- TMDS_D1+ TMDS_GND HDMI Connector TMDS_D1- TMDS_D0+ TMDS_GND TMDS_D0- TMDS_CLK+ TMDS_GND TMDS_CLKTESDH5V0A CEC N/C DDC_CLK DDC_DAT GND +5V Hot Plug Detection TESDS5V0A Version : B11 TESDH5V0A Ultra low capacitance ESD Protection Array Small Signal Diode Tape & Reel specification TSC label Item Top Cover Tape Symbol K 1.22 Max. Sprocket hole D 1.50 +0.10 A 180 ± 1 Reel outside diameter Carieer Tape Any Additional Label (If Required) 10 Pitches Cumulative Tolerance on Tape ±2.0mm ( ±0.008") P0 D P1 T E Dimension (mm) Carrier depth Reel inner diameter D1 50 Min. Feed hole width D2 13.0 ± 0.5 Sprocke hole position E 1.75 ±0.10 Sprocke hole pitch P0 4.00 ±0.10 Embossment center P1 2.00 ±0.10 Overall tape thickness T 0.6 Max. Tape width W 8.30 Max. Reel width W1 14.4 Max. Dimensions Unit (inch) Unit (mm) A 0.034 0.88 B 0.008 0.20 C 0.020 0.50 D 0.039 1.00 E 0.008 0.20 F 0.016 0.40 G 0.027 0.68 H 0.061 1.55 F K0 W BB0 0 B1 D' Top Cover Tape See Note1 For Components 2.0mm X 1.2mm and Larger K A0 Center Lines of Cavity Embossment For Machine Reference Only Including Draft and RADLL Concentric Around B 0 W1 Direction of Feed A D2 D1 Suggested PAD Layout D C G H A B E F Note 1: A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min. to 0.5 mm max. The component cannot rote more than 10o within the determined cavity. Note 2: If B1 exceeds 4.2 mm(0.165'') for 8 mm embossed tape, the tape may not feed through all tape feeders. Note 3: The suggested land pattern dimensions have been provided for reference only, as actual pad layouts may vary despending on application. Version : B11