TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 features D D D D D D D D typical applications Minimum Supply Voltage of 0.75 V Supply Voltage Supervision Range: – 1.2 V, 1.5 V, 1.8 V (TPS3123, TPS3124, TPS3125) – 3 V (TPS3125 Devices only) Power-On Reset Generator With Fixed Delay Time of 180 ms Manual Reset Input (TPS3123 and TPS3125) Watchdog Timer Retriggers the RESET Output at VDD ≥ VIT Supply Current of 14 µA (Typ) SOT23–5 Package Temperature Range . . . – 40°C to 85°C D D D D D D D D Applications Using Low Voltage DSPs, Microcontrollers or Microprocessors Wireless Communication Systems Portable/Battery-Powered Equipment Programmable Controls Intelligent Instruments Industrial Equipment Notebook/Desktop Computers Automotive Systems DBV PACKAGE (TOP VIEW) RESET 2.5 V 1.2 V GND MR VDD MR TPS3125J12 GND MR RESET WDI RESET VDD TPS3823-25 CVDD RESET DVDD GND 1 5 TPS3123 2 VDD 3 4 WDI 1 5 TPS3124 2 VDD TMS320UVC5402 RESET 3 4 WDI XF RESET 1 5 TPS3125 2 VDD 3 MR RESET GND GND GND RESET 4 Figure 1. Typical Dual-Voltage DSP Application description The TPS3123, TPS3124, TPS3125 family of ultra-low voltage processor supervisory circuits provides circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power-on, RESET is asserted when the supply voltage (VDD) becomes higher than 0.75 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, tdtyp = 180 ms starts after VDD has risen above the threshold voltage VIT. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 description (continued) When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage VIT set by an internal voltage divider. The TPS3123-xx and TPS3125-xx devices incorporate a manual reset input, MR. A low level at MR causes RESET to become active. The TPS3124-xx devices do not have the input MR, but include a high-level output RESET same as the TPS3125-xx devices. In addition the TPS3123-xx and TPS3124-xx have a watchdog timer that need to be triggered periodically by a positive or negative transition at WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval ttout = 0.8 s, RESET output becomes active for the time period td. This event also reinitializes the watchdog timer. The circuits are available in a 5-pin SOT23-5 package. The TPS3123, TPS3124, TPS3125 devices are characterized for operation over a temperature range of – 40°C to 85°C. PACKAGE INFORMATION STANDARD VERSIONS TA – 40°C to 85_C DEVICE NAME TPS3123J12DBVR† TPS3123J12DBVT‡ † TPS3123G15DBVR TPS3123G15DBVT‡ THRESHOLD VOLTAGE MARKING 1.08 V PBNI 1.40 V PBOI TPS3123J18DBVR† TPS3124J12DBVR† TPS3123J18DBVT‡ TPS3124J12DBVT‡ 1.62 V PBPI 1.08 V PBQI TPS3124G15DBVR† TPS3124J18DBVR† TPS3124G15DBVT‡ TPS3124J18DBVT‡ 1.40 V PBRI 1.62 V PBSI TPS3125J12DBVR† TPS3125G15DBVR† TPS3125J12DBVT‡ TPS3125G15DBVT‡ 1.08 V PBTI 1.40 V PBUI TPS3125J18DBVR† TPS3125L30DBVR† TPS3125J18DBVT‡ TPS3125L30DBVT‡ 1.62 V PBVI 2.64 V PBXI † The DBVR passive indicates tape and reel of 3000 parts. ‡ The DBVT passive indicates tape and reel of 250 parts. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 ordering information application specific versions TPS312 3 J 12 DBV R Reel Package Nominal Supply Voltage Typical Reset Threshold Voltage Functionality Family DEVICE NAME NOMINAL SUPPLY VOLTAGE, VNOM DEVICE NAME TPS312xx12DBV 1.2 V TPS312xAxxDBV TPS312xx15DBV 1.5 V TPS312xBxxDBV TPS312xx18DBV 1.8 V TPS312xCxxDBV TPS312xx30DBV 3.0 V TPS312xDxxDBV TYPICAL RESET THRESHOLD VOLTAGE–VIT– VNOM–1% VNOM–2% VNOM–3% VNOM–4% VNOM–5% TPS312xExxDBV TPS312xFxxDBV VNOM–6% VNOM–7% TPS312xGxxDBV TPS312xHxxDBV VNOM–8% VNOM–9% TPS312xIxxDBV TPS312xJxxDBV VNOM–10% VNOM–11% TPS312xKxxDBV TPS312xLxxDBV VNOM–12% VNOM–13% TPS312xMxxDBV TPS312xNxxDBV VNOM–14% VNOM–15% TPS312xOxxDBV NOTE: Ten standard versions will be available at product introduction. For the application specific versions contact the local TI sales office for availability and lead time. Function Tables TPS3123 TPS3124 TPS3125 MR VDD > VIT RESET VDD > VIT RESET RESET MR VDD > VIT RESET RESET L 0 L 0 L H L 0 L H 1 H L L 1 L L 1 L H H 0 L H 0 L H H 1 H H 1 H L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 functional block diagram VDD Device Power Supply R1 MR† R2 RESET Reset Logic + Timer RESET§ R3 GND Reference Voltage Watch Dog Logic + Timer Transition Detector WDI‡ † TPS3123 and TPS3125 Only ‡ TPS3123 and TPS3124 Only § TPS3124 and TPS3125 Only timing diagram TPS3123 and TPS3125 A B C D E F G VDD VIT <0,85 V t MR t RESET td td td t Output Undefined 4 POST OFFICE BOX 655303 Output Undefined • DALLAS, TEXAS 75265 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 timing diagram TPS3123 and TPS3124 A B VDD VIT <0,85 V t G MR (TPS3123) t C D E F J H WDI * * * * * t td td td td td RESET ttout ttout ttout t Output Undefined * = WDI Disabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 3.6 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 5 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DBV 437 mW 3.5 mW/°C 280 mW 227 mW recommended operating conditions at specified temperature range TA = 0°C to 85°C TA = – 40°C to 85°C Supply voltage voltage, VDD Input voltage, VI High-level input voltage, VIH MIN MAX 0.75 3.3 0.85 3.3 0 VDD+0.3 0.7×VDD Low-level input voltage, VIL Operating free-air temperature range, TA 6 – 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V V 0.3×VDD 1 Input transition rise and fall rate at WDI, ∆t/∆V UNIT 85 V µs/V °C TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MR pullup resistor (internal) IIH High level input current High-level IIL Low level input current Low-level VOH VOL WDI WDI = VDD = 3.3 V MR MR = 0.7×VDD, WDI WDI = 0 V, MR MR = 0 V, RESET VDD = 1.5 V, VDD = 3.3 V, RESET VDD = 0.75 V, VDD = 1.5 V, RESET VDD = 0.75 V, VDD = 1.5 V, RESET VDD = 1.5 V, VDD = 3.3 V, High level output voltage High-level Low level output voltage Low-level Negative-going g g g input threshold voltage (see Note 2) –1 1 –20 – 55 –1 1 VDD = 3.3 V IOH = –1 mA – 80 –170 IOH = – 4.5 mA IOH = – 8 µA TPS312xG15 TPS312xJ18 Hysteresis at VDD input TPS3123-xx TPS3124-xx IDD Ci TPS3125-xx (see Note 3) 0.8×V 0 8×VDD µA µA V IOH = –1 mA IOL = 15 µA 0.2×VDD IOL = 1.4 mA IOL = 1.4 mA IOL = 3 mA TA = –40°C 40°C to 85°C V 0.4 1.04 1.08 1.12 1.35 1.40 1.45 1.56 1.62 1.68 2.57 2.64 2.71 1 V < VIT– < 1.4 V 15 1.4 V < VIT– <2 V 20 2 V < VIT– < 3 V 30 WDI = VDD, MR unconnected VDD = 0.75 V VDD = 3.3 V 14 MR unconnected VDD = 0.75 V VDD = 3.3 V 14 Supply current UNIT kΩ VDD = 3.3 V VDD = 3.3 V TPS312xL30 Vhys y MAX 27 TPS312xJ12 VIT IT– TYP 22 18 V mV 30 µA 25 Input capacitance at MR, WDI VI = 0 V to 3.3 V 5 pF NOTES: 2. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal. 3. The supply current during delay time td is typical 5 µA higher. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER At VDD tw Pulse width At MR At WDI TEST CONDITIONS MIN VIH = VIT– + 0.2 V, VIL = VIT– – 0,2 V 6 VDD ≥ VIT 0.2 2V V, IT– + 0 VIL = 0.3xV 0 3xVDD, VIH = 0 0.7×V 7×VDD TYP MAX UNIT µs 1 0.1 switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX 0.8 1.4 2.1 s 100 180 260 ms ttout Watchdog time out VDD ≥ VIT– + 0.2 V, See timing diagram td Delay time VDD > VIT–+ 0.2 V, See timing diagram tPHL Propagation delay time, high-to-low-level output MR to RESET delay (TPS3123/25 only) tPLH Propagation delay time, low-to-high-level output MR to RESET delay (TPS3125 only) tPHL Propagation delay time, high-to-low-level output tPLH Propagation delay time, low-to-high-level output 8 VDD to RESET delay VDD to RESET delay (TPS3124/25 only) POST OFFICE BOX 655303 VDD ≥ VIT– + 0.2 V, VIL = 0.2 0 2 × VDD, VIH = 0.8 × VDD VIL = VIT 0 2 V, V IT– – 0.2 VIH = VIT– + 0.2 V • DALLAS, TEXAS 75265 UNIT 0.1 µs 0.1 10 10 µs TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 25 750 VOL – Low-Level Output Voltage – mV TA = 25°C I CC – Supply Current – µ A TPS3123J12 20 15 10 0 0 1 2 VDD – Supply Voltage – V 3 TPS3123J12 VDD = 0.75 V TA = 85°C 500 TA = 25°C TA = 0°C 250 0 3.3 0 200 50 100 150 IOL – Low-Level Output Current – µA Figure 2 Figure 3 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 850 VOL – Low-Level Output Voltage – mV 700 1.5 TA = 85°C VOL – Low-Level Output Voltage – V TPS3123J12 VDD = 0.85 V MR = Open 800 TA = 25°C 600 TA = 0°C 500 TA = – 40°C 400 300 200 100 0 0 250 400 100 200 300 IOL – Low-Level Output Current – µA 500 TPS3125L30 VDD = 1.5 V MR = Open 1.25 TA = 85°C TA = 25°C 1 TA = 0°C TA = – 40°C 0.75 0.5 0.25 0 0 1 2 3 4 5 IOL – Low-Level Output Current – mA Figure 4 6 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.3 2.75 TA = 85°C 2.5 VOH – High-Level Output Voltage – V VOL – Low-Level Output Voltage – V 1.6 TPS3125L30 VDD = 3.3 V MR = Open 3 TA = 25°C TA = 0°C 2.25 TA = – 40°C 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 TPS3123J12 VDD = 1.5 V MR = Open 1.4 1.2 1 TA = 25°C 0.6 0.4 TA = 0°C 0.2 0 0 5 10 15 20 25 IOL – Low-Level Output Current – mA 30 0 –1 TPS3123J12 VDD = 3.3 V MR = Open VOH – High-Level Output Voltage – V 2.5 2.25 2 TA = 85°C 1.75 TA = – 40°C 1.5 TA = 25°C 1.25 1 TA = 0°C 0.75 0.5 0.25 0 0 –5 –10 –15 –20 –25 IOH – High-Level Output Current – mA –30 Normalized Input Threshold Voltage –V IT(T A)/ V IT (25 °C ) 3.4 2.75 –3 –4 –5 Figure 7 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3 –2 IOH – High-Level Output Current – mA Figure 6 NORMALIZED INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE 1.005 TPS312xJ12 1.004 1.003 1.002 1.001 1 0.999 0.998 –40 Figure 8 10 TA = – 40°C TA = 85°C 0.8 –20 0 20 40 60 TA – Free-Air Temperature – °C Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 80 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 NORMALIZED INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE MINIMUM PULSE DURATION vs THRESHOLD OVERDRIVE 1.005 4.5 TPS312xL30 4 t w– Minimum Pulse Duration –µ s 1.004 1.003 1.002 1.001 1 0.999 TPS312xL30 MR = Open VIT = 2.64 V TA = 25°C 3.5 3 2.5 2 1.5 1 0.5 0.998 –40 –20 0 20 40 60 TA – Free-Air Temperature – °C 0 80 200 250 50 100 150 VDD – Threshold Overdrive – mV 0 Figure 10 300 Figure 11 MINIMUM PULSE DURATION vs THRESHOLD OVERDRIVE 3.5 MR = Open VIT = 1.08 V TA = 25°C 3 t w– Minimum Pulse Duration –µ s Normalized Input Threshold Voltage –V IT(T A)/ V IT (25 °C ) TYPICAL CHARACTERISTICS TPS312xJ12 2.5 2 1.5 1 0.5 0 0 50 100 150 200 250 300 VDD – Threshold Overdrive – mV Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS SLVS227 – AUGUST 1999 MECHANICAL DATA DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,50 0,30 0,95 5 0,20 M 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0°–8° 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/E 05/99 NOTES: A. B. C. D. 12 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated