ONSEMI NCV4276DT33RK

NCV4276
Low−Drop Voltage
Regulator
This industry standard linear regulator has the capability to drive
loads up to 400 mA at 5.0, 3.3, 2.5 and 1.8 V. Package options
include DPAK and D2PAK. This device is pin−for−pin compatible
with the Infineon part number TLE4276.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
5.0, 3.3, 2.5 and 1.8 V; ±4%; Output Voltage at 400 mA
500 mV (max) Dropout Voltage
Inhibit Input
Very Low Current Consumption
Fault Protection
♦ +45 V Peak Transient Voltage
♦ −42 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
1
5
DPAK
5−PIN
DT SUFFIX
CASE 175AA
4276
ALYWW
x
1
D2PAK
5−PIN
DS SUFFIX
CASE 936A
1
NCV4276
AWLYYWW
5
I
Q
Bandgap
Reference
Error
Amplifier
Pin 1. I
1
2. INH
Tab, 3. GND*
4. NC
5. Q
* Tab is connected to
Pin 3 on all packages.
Current Limit and
Saturation Sense
−
+
A
WL, L
YY, Y
WW
Thermal
Shutdown
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 9 of this data sheet.
INH
GND
NC
Figure 1. Block Diagram
 Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. 7
1
Publication Order Number:
NCV4276/D
NCV4276
PIN FUNCTION DESCRIPTION
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ÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑ
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ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑ
ÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
Pin No.
Symbol
Description
1
I
2
INH
Inhibit; Set low−to inhibit.
3
GND
Ground; Pin 3 internally connected to heatsink.
4
NC
5
Q
Input; Battery Supply Input Voltage.
Not Connected for fixed voltage versions.
Output; ±4.0%, 400 mA output. Use 22 F, ESR < 2.0 at 10 kHz to ground. See Figure 3.
MAXIMUM RATINGS†
Rating
Min
Max
Unit
−42
45
V
−
−
V
Inhibit INH
−42
45
V
Output (Q)
−1.0
40
V
−
100
mA
Q + 0.5
40
V
ESD Susceptibility (Human Body Model)
(Machine Model)
4.0
200
−
−
kV
V
Junction Temperature
−40
150
°C
−50
150
°C
−
−
240 Peak
(Note 3)
260 Peak
°C
Input [I (DC)]
Input [I (Peak Transient Voltage)]
Ground (GND)
Operating Range (I)
Storage Temperature
Lead Temperature Soldering
Reflow (SMD styles only) Note 1
Wave Solder (through hole styles only) Note 2
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Parameter
Test Conditions (Typical Value)
Unit
DPAK 5−PIN PACKAGE
Min Pad Board (Note 4)
1″ Pad Board (Note 5)
Junction−to−Tab (psi−JLx, JLx)
4.2
4.7
C/W
Junction−to−Ambient (RJA, JA)
100.9
46.8
C/W
D2PAK 5−PIN PACKAGE
0.4 sq. in. Spreader Board (Note 6)
1.2 sq. in. Spreader Board (Note 7)
Junction−to−Tab (psi−JLx, JLx)
3.8
4.0
C/W
Junction−to−Ambient (RJA, JA)
74.8
41.6
C/W
1. 10 seconds max.
2. 60 seconds max above 183°C.
3. −5°C/+0°C allowable conditions.
4. 1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.62″ thick FR4.
5. 1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.62″ thick FR4.
6. 1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.62″ thick FR4.
7. 1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.62″ thick FR4.
†During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal
dissipation must be observed closely.
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NCV4276
ELECTRICAL CHARACTERISTICS (VI = 13.5 V; −40°C < TJ < 150°C; unless otherwise noted)
Characteristic
Test Conditions
Min
Typ
Max
Unit
4.8
5.0
5.2
V
Output
Output Voltage, 5.0 V Version
5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V
Output Voltage, 5.0 V Version
5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V
4.8
5.0
5.2
V
Output Voltage, 3.3 V Version
5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V
3.168
3.300
3.432
V
Output Voltage, 3.3 V Version
5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V
3.168
3.300
3.432
V
Output Voltage, 2.5 V Version
5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V
2.4
2.5
2.6
V
Output Voltage, 2.5 V Version
5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V
2.4
2.5
2.6
V
Output Voltage, 1.8 V Version
5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V
1.728
1.800
1.872
V
Output Voltage, 1.8 V Version
5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V
1.728
1.800
1.872
V
400
630
1100
mA
A
Output Current Limitation
−
Output Current Limitation (Sleep Mode)
Iq = II − IQ
INH = 0 V, TJ < 100°C
−
0.5
10
Quiescent Current, Iq = II − IQ
IQ = 1.0 mA
−
130
220
A
Quiescent Current, Iq = II − IQ
IQ = 250 mA
−
10
15
mA
Quiescent Current, Iq = II − IQ
IQ = 400 mA
−
20
35
mA
IQ = 250 mA, Vdr = VI − VQ
−
−
−
−
250
−
−
−
500
1.2
2.0
2.7
mV
V
V
V
Dropout Voltage,
5.0 V Version
3.3 V Version
2.5 V Version
1.8 V Version
Load Regulation
IQ = 5.0 mA to 400 mA
−35
10
35
mV
Line Regulation
∆V = 12 V to 32 V, IQ = 5.0 mA
−25
2.5
25
mV
Power Supply Ripple Rejection
fr = 100 Hz, Vr = 0.5 Vpp
−
60
−
dB
−
0.5
−
mV/K
Temperature Output Voltage Drift
−
Inhibit
Inhibit On Voltage
VQ 4.8 V
−
2.8
3.5
V
Inhibit Off Voltage
VQ 0.1 V
0.5
1.7
−
V
Input Current
VINH = 5.0 V
5.0
10
20
A
II
Input
CI1
100 F
I 1
CI2
100 nF
Output
CQ
NCV4276
INH
IINH
IQ
5 Q
2
4
3
NC
GND
Figure 2. Measuring Circuit
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3
RL
NCV4276
TYPICAL PERFORMANCE CHARACTERISTICS
1000
Unstable ESR Region for
CVout = 1 F − 22 F
ESR ()
100
10
1
Maximum ESR for
CVout = 1 F − 22 F
0.1
Stable ESR Region
0.01
0
50
100
150
200
250
300
350
400
450
OUTPUT CURRENT (mA)
Figure 3. Output Stability with Output
Capacitor ESR
Circuit Description
The error amplifier compares a temperature−stable
reference voltage to a voltage that is proportional to the
output voltage (Q) (generated from a resistor divider) and
drives the base of a series transistor via a buffer. Saturation
control as a function of the load current prevents any
oversaturation of the output power device preventing
excessive substrate current (quiescent current).
VI
Iq
Figure 4. Single Output Regulator with Key
Performance Parameters Labeled
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of RJA:
(1)
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
application,
is the quiescent current the regulator
consumes at IQ(max).
RJA RJC RCS RSA
(3)
where
RJC is the junction−to−case thermal resistance,
RCS is the case−to−heatsink thermal resistance,
RSA is the heatsink−to−ambient thermal
resistance.
Once the value of PD(max) is known, the maximum
permissible value of RJA can be calculated:
T
RJA 150°C A
PD
VQ
Iq
VI(max)Iq
where
VI(max)
VQ(min)
IQ(max)
SMART
REGULATOR
} Control
Features
Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 4) is:
PD(max) [VI(max) VQ(min)] IQ(max)
IQ
II
RJC appears in the package section of the data sheet.
Like RJA, it too is a function of package type. RCS and
RSA are functions of the package type, heatsink and the
interface between them. These values appear in data sheets
of heat sink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
(2)
The value of RJA can then be compared with those in the
package section of the data sheet. Those packages with
RJA less than the calculated value in Equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
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4
NCV4276
Table 1. DPAK 5−Lead Thermal RC Network Models
Drain Copper Area (1 oz thick)
168 mm2
(SPICE Deck Format)
736 mm2
168 mm2
Cauer Network
168
mm2
736 mm2
Foster Network
736
mm2
Units
Tau
Tau
Units
C_C1
Junction
Gnd
1.00E−06
1.00E−06
W−s/C
1.36E−08
1.361E−08
sec
C_C2
node1
Gnd
1.00E−05
1.00E−05
W−s/C
7.41E−07
7.411E−07
sec
C_C3
node2
Gnd
6.00E−05
6.00E−05
W−s/C
1.04E−05
1.029E−05
sec
C_C4
node3
Gnd
1.00E−04
1.00E−04
W−s/C
3.91E−05
3.737E−05
sec
C_C5
node4
Gnd
4.36E−04
3.64E−04
W−s/C
1.80E−03
1.376E−03
sec
C_C6
node5
Gnd
6.77E−02
1.92E−02
W−s/C
3.77E−01
2.851E−02
sec
C_C7
node6
Gnd
1.51E−01
1.27E−01
W−s/C
3.79E+00
9.475E−01
sec
C_C8
node7
Gnd
4.80E−01
1.018
W−s/C
2.65E+01
1.173E+01
sec
C_C9
node8
Gnd
3.740
2.955
W−s/C
8.71E+01
8.59E+01
sec
C_C10
node9
Gnd
10.322
0.438
W−s/C
168
mm2
736
mm2
sec
R’s
R’s
R_R1
Junction
node1
0.015
0.015
C/W
0.0123
0.0123
C/W
R_R2
node1
node2
0.08
0.08
C/W
0.0585
0.0585
C/W
R_R3
node2
node3
0.4
0.4
C/W
0.0304
0.0287
C/W
R_R4
node3
node4
0.2
0.2
C/W
0.3997
0.3772
C/W
R_R5
node4
node5
2.97519
2.6171
C/W
3.115
2.68
C/W
R_R6
node5
node6
8.2971
1.6778
C/W
3.571
1.38
C/W
R_R7
node6
node7
25.9805
7.4246
C/W
12.851
5.92
C/W
R_R8
node7
node8
46.5192
14.9320
C/W
35.471
7.39
C/W
R_R9
node8
node9
17.7808
19.2560
C/W
46.741
28.94
C/W
node9
Gnd
0.1
0.1758
C/W
R_R10
NOTE:
Bold face items represent the package without the external thermal system.
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5
C/W
NCV4276
Table 2. D2PAK 5−Lead Thermal RC Network Models
Drain Copper Area (1 oz thick)
241 mm2
(SPICE Deck Format)
788 mm2
241 mm2
Cauer Network
241
mm2
788 mm2
Foster Network
653
mm2
Units
Tau
Tau
Units
C_C1
Junction
Gnd
1.00E−06
1.00E−06
W−s/C
1.361E−08
1.361E−08
sec
C_C2
node1
Gnd
1.00E−05
1.00E−05
W−s/C
7.411E−07
7.411E−07
sec
C_C3
node2
Gnd
6.00E−05
6.00E−05
W−s/C
1.005E−05
1.007E−05
sec
C_C4
node3
Gnd
1.00E−04
1.00E−04
W−s/C
3.460E−05
3.480E−05
sec
C_C5
node4
Gnd
2.82E−04
2.87E−04
W−s/C
7.868E−04
8.107E−04
sec
C_C6
node5
Gnd
5.58E−03
5.95E−03
W−s/C
7.431E−03
7.830E−03
sec
C_C7
node6
Gnd
4.25E−01
4.61E−01
W−s/C
2.786E+00
2.012E+00
sec
C_C8
node7
Gnd
9.22E−01
2.05
W−s/C
2.014E+01
2.601E+01
sec
C_C9
node8
Gnd
1.73
4.88
W−s/C
1.134E+02
1.218E+02
sec
C_C10
node9
Gnd
7.12
1.31
W−s/C
241
mm2
653
mm2
sec
R’s
R’s
R_R1
Junction
node1
0.015
0.0150
C/W
0.0123
0.0123
C/W
R_R2
node1
node2
0.08
0.0800
C/W
0.0585
0.0585
C/W
R_R3
node2
node3
0.4
0.4000
C/W
0.0257
0.0260
C/W
R_R4
node3
node4
0.2
0.2000
C/W
0.3413
0.3438
C/W
R_R5
node4
node5
1.85638
1.8839
C/W
1.77
1.81
C/W
R_R6
node5
node6
1.23672
1.2272
C/W
1.54
1.52
C/W
R_R7
node6
node7
9.81541
5.3383
C/W
4.13
3.46
C/W
R_R8
node7
node8
33.1868
18.9591
C/W
6.27
5.03
C/W
R_R9
node8
node9
27.0263
13.3369
C/W
60.80
29.30
C/W
node9
gnd
1.13944
0.1191
C/W
R_R10
NOTE:
C/W
Bold face items represent the package without the external thermal system.
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior
due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear
a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily
implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical
tools (for instance, in a spreadsheet program), according to the following formula:
n
R(t) Ri 1−e−ttaui i1
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110
110
100
100
90
90
80
80
70
JA (C°/W)
JA (C°/W)
NCV4276
1 oz
60
2 oz
70
60
1 oz
2 oz
50
50
40
40
30
150 200 250 300 350 400 450 500 550 600 650 700 750
30
150 200 250 300 350 400 450 500 550 600 650 700 750
COPPER AREA (mm2)
COPPER AREA (mm2)
Figure 5. JA vs. Copper Spreader Area,
DPAK 5−Lead
Figure 6. JA vs. Copper Spreader Area,
D2PAK 5−Lead
100
Cu Area 167 mm2
Cu Area 736 mm2
R(t) C°/W
10
1.0
sqrt(t)
0.1
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
TIME (sec)
Figure 7. Single−Pulse Heating Curves, DPAK 5−Lead
100
Cu Area 167 mm2
Cu Area 736 mm2
R(t) C°/W
10
1.0
0.1
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
TIME (sec)
Figure 8. Single−Pulse Heating Curves, D2PAK 5−Lead
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7
10
100
1000
NCV4276
100
50% Duty Cycle
RJA 736 mm2 C°/W
20%
10
1.0
10%
5%
2%
1%
0.1
Non−normalized Response
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
10
100
1000
PULSE WIDTH (sec)
Figure 9. Duty Cycle for 1” Spreader Boards, DPAK 5−Lead
100
RJA 788 mm2 C°/W
50% Duty Cycle
10
20%
10%
5%
1.0
2%
1%
0.1
Non−normalized Response
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
PULSE WIDTH (sec)
Figure 10. Duty Cycle for 1” Spreader Boards, D2PAK 5−Lead
R1
Junction
C1
R2
C2
R3
C3
Rn
Cn
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 11. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R1
C1
R2
C2
R3
C3
Rn
Cn
Each rung is exactly characterized by its RC−product
time constant; amplitudes are the resistances.
Ambient
(thermal ground)
Figure 12. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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NCV4276
ORDERING INFORMATION
Device
Output Voltage
NCV4276DT50RK
NCV4276DS50
5.0 V
NCV4276DT33RK
3.3 V
2500 Tape & Reel
D2PAK,
PAK 5
5−Pin
Pin
NCV4276DT25RK
DPAK, 5−Pin
2.5 V
D2PAK,
PAK 5
5−Pin
Pin
NCV4276DS25R4
NCV4276DT18RK
NCV4276DS18
DPAK, 5−Pin
DPAK, 5−Pin
NCV4276DS33R4
NCV4276DS25
Shipping
D2PAK,
PAK 5
5−Pin
Pin
NCV4276DS50R4
NCV4276DS33
Package
DPAK, 5−Pin
1.8 V
D2PAK,
PAK 5
5−Pin
Pin
NCV4276DS18R4
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50 Units / Rail
800 Tape & Reel
2500 Tape & Reel
50 Units / Rail
800 Tape & Reel
2500 Tape & Reel
50 Units / Rail
800 Tape & Reel
2500 Tape & Reel
50 Units / Rail
800 Tape & Reel
NCV4276
PACKAGE DIMENSIONS
DPAK 5 CENTER LEAD CROP
DT SUFFIX
CASE 175AA−01
ISSUE O
−T−
SEATING
PLANE
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
R1
Z
A
S
1 2 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
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10
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
NCV4276
PACKAGE DIMENSIONS
D2PAK
5 LEAD
DS SUFFIX
CASE 936A−02
ISSUE B
−T−
OPTIONAL
CHAMFER
A
B
V
H
1 2 3 4 5
M
D
M
U
S
K
0.010 (0.254)
TERMINAL 6
E
T
L
P
N
G
R
C
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11
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
A AND K.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 6.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAXIMUM.
DIM
A
B
C
D
E
G
H
K
L
M
N
P
R
S
U
V
INCHES
MIN
MAX
0.386
0.403
0.356
0.368
0.170
0.180
0.026
0.036
0.045
0.055
0.067 BSC
0.539
0.579
0.050 REF
0.000
0.010
0.088
0.102
0.018
0.026
0.058
0.078
5 REF
0.116 REF
0.200 MIN
0.250 MIN
MILLIMETERS
MIN
MAX
9.804 10.236
9.042
9.347
4.318
4.572
0.660
0.914
1.143
1.397
1.702 BSC
13.691 14.707
1.270 REF
0.000
0.254
2.235
2.591
0.457
0.660
1.473
1.981
5 REF
2.946 REF
5.080 MIN
6.350 MIN
NCV4276
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