NCV4290 5.0 V, 450 mA Low-Dropout Voltage Regulator with Power Good The NCV4290 is an integrated low dropout regulator designed for use in harsh automotive environments. It includes wide operating temperature and input voltage ranges. The output is regulated at 5.0 V and is rated to 450 mA of output current. It also provides a number of features, including overcurrent protection, overtemperature protection and a programmable microprocessor power good signal. The NCV4290 is available in the DPAK and D2PAK surface mount packages. The output is stable over a wide output capacitance and ESR range. http://onsemi.com MARKING DIAGRAMS 1 DPAK, 5−PIN DT SUFFIX CASE 175AA 5 V4290xG ALYWW Features • • • • • • • 5.0 V, ±2% Output Voltage Options 450 mA Output Current Very Low Current Consumption Active Power Good Output Power Good Low Down to VQ = 1.0 V 500 mV (max) Dropout Voltage Fault Protection ♦ +45 V Peak Transient Voltage ♦ −42 V Reverse Voltage ♦ Short Circuit Protection ♦ Thermal Overload Protection AEC−Q100 Qualified These are Pb−Free Devices • • 1 1 NC V4290x AWLYWWG 5 1 x A WL, L Y WW G = 5 (5.0 V Output) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Pin Applications • Auto Body Electronics I Q Bandgap Reference D2PAK, 5−PIN DS SUFFIX CASE 936A Error Amplifier 1. I 2. PG Tab, 3. GND* 4. D 5. Q * Tab is connected to Pin 3 on all packages Current Limit and Saturation Sense ORDERING INFORMATION + − See detailed ordering and shipping information in the dimensions section on page 13 of this data sheet. Thermal Shutdown Power Good Generator D GND PG Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2012 August, 2012 − Rev. 0 1 Publication Order Number: NCV4290D NCV4290 PIN FUNCTION DESCRIPTION ÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑ ÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑ ÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑ ÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Pin # Symbol Description 1 I 2 PG 3, Tab GND 4 D Power Good Delay; timing capacitor to GND for Power Good Delay function. 5 Q Output; ±2.0%, 450 mA output. Bypass with 22 F capacitor, ESR < 4.0 . Input; Battery Supply Input Voltage. Bypass to ground with a ceramic capacitor. Power Good Output; Open Collector Active Power Good (accurate when VQ > 1.0 V). Ground; Pin 3 internally connected to tab. MAXIMUM RATINGS Rating Symbol Min Max Unit Input Voltage VI −42 45 V Input Peak Transient Voltage VI − 45 V Output Voltage VQ −1.0 16 V Power Good Output Voltage VPG −0.3 25 V Power Good Output Current IPG −5.0 5.0 mA Power Good Delay Voltage VD −0.3 7.0 V Power Good Delay Current ID −2.0 2.0 mA ESDHBM ESDMM ESDCDM 4.0 200 1000 − − − kV V V Junction Temperature TJ −40 150 °C Storage Temperature Tstg −55 150 °C ESD Susceptibility (Note 1) − Human Body Model − Machine Model − Charge Device Model Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002, ESD Machine Model tested per AEC−Q100−003, ESD Charged Device Model tested per AEC−Q100−011, Latch−up tested per AEC−Q100−004. http://onsemi.com 2 NCV4290 OPERATING RANGE Rating Symbol Min Max Unit Input Voltage Operating Range, 5.0 V Option VI 5.5 42 V Junction Temperature TJ −40 150 °C Symbol Min Max Unit Lead Free, 60 sec−150 sec above 217°C TSLD − 265 Peak °C Moisture Sensitivity Level MSL LEAD TEMPERATURE SOLDERING REFLOW AND MSL (Note 2) Rating 1 2. PRR IPC / JEDEC J−STD−020C THERMAL CHARACTERISTICS Characteristic Test Conditions (Typical Value) Unit DPAK 5−PIN PACKAGE 0.3 sq. in. Spreader Board (Note 3) 1.2 sq. in. Spreader Board (Note 4) Junction−to−Tab (RJT) 4.5 4.8 °C/W Junction−to−Ambient (RJA) 76 53 °C/W 0.4 sq. in. Spreader Board (Note 5) 1.2 sq. in. Spreader Board (Note 6) Junction−to−Tab (RJT) 3.8 4.1 °C/W Junction−to−Ambient (RJA) 60 50 °C/W D2PAK 3. 4. 5. 6. 5−PIN PACKAGE inch2 inch2 1 oz. copper, 0.26 1 oz. copper, 1.14 1 oz. copper, 0.373 1 oz. copper, 1.222 (168 mm2) copper area, 0.062″ thick FR4. (736 mm2) copper area, 0.062″ thick FR4. inch2 (241 mm2) copper area, 0.062″ thick FR4. inch2 (788 mm2) copper area, 0.062″ thick FR4. http://onsemi.com 3 NCV4290 ELECTRICAL CHARACTERISTICS (VI = 13.5 V, CQ = 22 F, ESR = 1.5 ; −40°C < TJ < 150°C; unless otherwise noted.) Characteristic Symbol Test Conditions Min Typ Max Unit OUTPUT Output Voltage (5.0 V Option) VQ 100 A v IQ v 400 mA 6.0 V v VI v 28 V 4.9 5.0 5.1 V Output Voltage (5.0 V Option) VQ 100 A v IQ v 200 mA 6.0 V v VI v 40 V 4.9 5.0 5.1 V Output Current Limitation IQ VQ = 0.9 x VQ,typ 450 1000 − mA Quiescent Current Iq = II − IQ Iq IQ = 1.0 mA − 170 230 A IQ = 1.0 mA, TJ = 25°C − 170 200 A IQ = 250 mA − 10 15 mA IQ = 400 mA − 23 35 mA Vdr IQ = 300 mA Vdr = VI − VQ (Note 7) − 250 500 mV Load Regulation VQ IQ = 5.0 mA to 400 mA −30 5.0 30 mV Line Regulation VQ VI = 8.0 V to 32 V, IQ = 5.0 mA −15 5.0 15 mV Dropout Voltage (5.0 V Option) Power Supply Ripple Rejection PSRR fr = 100 Hz, Vr = 0.5 Vpp − 60 − dB Temperature Output Voltage Drift dVQ/dT −− − 0.5 − mV/K DELAY TIMING D AND POWER GOOD OUTPUT PG Switching Threshold (5.0 V Option) VQ,pgt−i VQ increasing 4.45 4.65 4.8 V PG Switching Threshold (5.0 V Option) VQ,pgt−d VQ decreasing 3.5 3.65 3.8 V − 0.1 0.4 V VPG Rext ≥ 5.0 k, VQ ≥ 1.0 V PG Output Leakage Current IPG VPGH > 4.5 V − 0 10 A PG Charging Current ID,C VD = 1.0 V 3.0 6.0 9.0 A Upper Timing Threshold VDU −− 1.5 1.8 2.2 V Lower Timing Threshold VDL −− 0.6 0.85 1.1 V PG Output Low Voltage PG Delay Time trd CD = 47 nF 10 16 22 ms PG Reaction Time trr CD = 47 nF 0.2 0.75 2.0 s −− 150 − 210 °C THERMAL SHUTDOWN Shutdown Temperature (Note 8) TSD 7. Measured when output voltage VQ falls 100 mV below the regulated voltage at VI = 13.5 V. Vdr = VI − VQ. 8. Guaranteed by design, not tested in production. http://onsemi.com 4 NCV4290 100 100 10 10 1 ESR () ESR () TYPICAL PERFORMANCE CHARACTERISTICS Stable Region VI = 13.5 V CQ = 22 F 0.1 0.01 0 50 100 150 200 250 300 350 400 Stable Region 1 0.1 VI = 13.5 V CQ = 1 F 0.01 0 450 50 100 IQ, OUTPUT CURRENT (mA) 250 300 350 400 450 Figure 3. Output Stability with Output Capacitor ESR 5.2 6.0 VQ, OUTPUT VOLTAGE (V) VQ, OUTPUT VOLAGE (V) 200 IQ, OUTPUT CURRENT (mA) Figure 2. Output Stability with Output Capacitor ESR VI = 13.5 V, RL = 25 5.1 5.0 4.9 4.8 −40 0 40 80 120 RL = 25 TJ = 25°C 5.0 4.0 3.0 2.0 1.0 0.0 0 160 2 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Output Voltage VQ vs. Temperature TJ 1.2 VI = 13.5 V 1.0 0.8 0.6 0.4 0.2 0.0 −40 0 40 80 120 160 4 6 VI, INPUT VOLTAGE (V) 8 10 Figure 5. Output Voltage VQ vs. Input Voltage VI IQ, OUTPUT CURRENT LIMITATION (A) IQ, OUTPUT CURRENT LIMITATION (A) 150 1.2 TJ = 25°C 1.0 0.8 TJ = 125°C 0.6 0.4 0.2 0.0 0 10 20 30 40 VI, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Output Current IQ vs. Temperature TJ Figure 7. Output Current IQ vs. Input Voltage VI http://onsemi.com 5 50 NCV4290 TYPICAL PERFORMANCE CHARACTERISTICS 80 Iq, CURRENT CONSUMPTION (mA) Iq, CURRENT CONSUMPTION (mA) 3.5 VI = 13.5 V, TJ = 25°C 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 VI = 13.5 V, TJ = 25°C 70 60 50 40 30 20 10 0 120 0 100 IQ, OUTPUT CURRENT (mA) 1.8 VDU/VDL, UPPER/LOWER TIMING THRESHOLD (V) 7 6 5 VI = 13.5 V, VD = 1.0 V 3 2 1 40 80 120 1.4 1.0 VDL 0.8 0.6 0.4 0.2 0.0 −40 160 0 40 120 160 Figure 11. Delay Switching Threshold VDU, VDL vs. Temperature TJ 600 500 TJ = 125°C 400 300 TJ = 25°C 200 100 100 80 TJ, JUNCTION TEMPERATURE (°C) 700 0 600 VI = 13.5 V 1.2 Figure 10. Charge Current ID,C vs. Temperature TJ 0 500 VDU 1.6 TJ, JUNCTION TEMPERATURE (°C) Vdr, DROPOUT VOLTAGE (mV) IDC, CHARGE CURRENT (A) 2.0 0 400 Figure 9. Current Consumption Iq vs. Output Current IQ 8 0 −40 300 IQ, OUTPUT CURRENT (mA) Figure 8. Current Consumption Iq vs. Output Current IQ 4 200 200 300 400 500 600 IQ, OUTPUT CURRENT (mA) Figure 12. Drop Voltage Vdr vs. Output Current IQ http://onsemi.com 6 700 NCV4290 APPLICATION INFORMATION VI II CI1 1000 F I CI2 100 nF ID CD 47 nF 1 5 IQ Q CQ 22 F NCV4290 D 4 2 3 PG IPG VQ Rext 5.0 k VPG GND Iq Figure 13. Test Circuit Circuit Description The NCV4290 is an integrated low dropout regulator that provides 5.0 V, 450 mA protected output and a signal for power on power good. The regulation is provided by a PNP pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. The output current capability is 450 mA, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. The regulator is protected by both current limit and thermal shutdown. Thermal shutdown occurs above 150°C to protect the IC during overloads and extreme ambient temperatures. The delay time for the power good output is adjustable by selection of the timing capacitor. See Figure 13, Test Circuit, for circuit element nomenclature illustration. capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the capacitance and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor CQ shown in Figure 13, Test Circuit, should work for most applications; however, it is not necessarily the optimized solution. Stability is guaranteed for CQ ≥ 22 F and an ESR ≤ 4.0 . ESR characteristics were measured with ceramic capacitors and additional resistors to emulate ESR. Murata ceramic capacitors were used, GRM32ER71C226ME18 (22 F, 16 V, X7R, 1210), GRM219R71E105KA88 (1 F, 25 V, X7R, 0805). Power Good Output The power good output is used as the power on indicator to the microcontroller. This signal indicates when the output voltage is suitable for reliable operation of the controller. It pulls low when the output is not considered to be ready. PG is pulled up to VQ by an external resistor, typically 5.0 k in value. Hysteresis is implemented for PG signal. When output voltage is decreasing PG goes Low at VQ typ 3.65 V and when output voltage is increasing PG goes High at VQ typ 4.65 V. The input and output conditions that control the Power Good Output and the relative timing are illustrated in Figure 14, Power Good Timing. Output voltage regulation must be maintained for the delay time before the power good output signals a valid condition. The delay for the power good output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0.0 V to the upper timing threshold voltage VDU. The charging current for this is ID,C and D pin voltage in steady state is typically 2.85 V. By using typical IC parameters with a 47 nF capacitor on the D pin, the following time delay for 5.0 V regulator is derived: Regulator The error amplifier compares the reference voltage to a sample of the output voltage (VQ) and drives the base of a PNP series pass transistor by a buffer. The reference is a bandgap design to give it a temperature−stable output. Saturation control of the PNP is a function of the load current and input voltage. Over saturation of the output power device is prevented, and quiescent current in the ground pin is minimized. Regulator Stability Considerations The input capacitors (CI1 and CI2) are necessary to stabilize the input impedance to avoid voltage line influences. Using a resistor of approximately 1.0 in series with CI2 can stop potential oscillations caused by stray inductance and capacitance. The output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum, aluminum or ceramic capacitors can be used. The range of stability versus capacitance, load current and capacitive ESR is illustrated in Figures 2 and 3. Minimum ESR for CQ = 22 F is native ESR of ceramic capacitors. The aluminum electrolytic tRD = CDVDU / ID,C tRD = 47 nF (1.8 V) / 6.0 A = 14.1 ms Other time delays can be obtained by changing the capacitor value. http://onsemi.com 7 NCV4290 VI < trr (PG Reaction Time) VQ VQ,pgt_i VQ,pgt_d I D,C dV + dt CD VD Upper Timing Threshold VDU Lower Timing Threshold VDL trd VPG trr PG Delay Time PG Reaction Time Power−on Power Good Signal Thermal Shutdown Voltage Dip Undervoltage at Input Not Lower than 4 V Secondary Overload Spike at Output Figure 14. Power Good Timing http://onsemi.com 8 NCV4290 Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 15) is: PD(max) + [VI(max) * VQ(min)] IQ(max) Heatsinks A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RJA: (1) ) VI(max)Iq where VI(max) is the maximum input voltage, VQ(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RJA can be calculated: T RJA + 150° C * A PD RJA + RJC ) RCS ) RSA where RJC is the junction−to−case thermal resistance, RCS is the case−to−heatsink thermal resistance, RSA is the heatsink−to−ambient thermal resistance. RJC appears in the package section of the data sheet. Like RJA, it too is a function of package type. RCS and RSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D. (2) The value of RJA can then be compared with those in the package section of the data sheet. Those packages with RJA’s less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IQ II VI SMART REGULATOR® (3) VQ } Control Features Iq Figure 15. Single Output Regulator with Key Performance Parameters Labeled http://onsemi.com 9 NCV4290 Thermal Model A discussion of thermal modeling is in the ON Semiconductor web site: http://www.onsemi.com/pub/collateral/BR1487−D.PDF. Table 1. DPAK 5−Lead Thermal RC Network Models Drain Copper Area (1 oz thick) 168 mm2 (SPICE Deck Format) 736 mm2 168 mm2 Cauer Network 736 mm2 Foster Network 168 mm2 736 mm2 Units Tau Tau Units C_C1 Junction Gnd 9.5059E−06 9.5059E−06 W−s/C 1.000E−06 1.000E−06 sec C_C2 node1 Gnd 3.7125E−05 3.7125E−05 W−s/C 1.000E−05 1.000E−05 sec C_C3 node2 Gnd 1.1233E−05 1.1233E−05 W−s/C 1.000E−04 1.000E−04 sec C_C4 node3 Gnd 6.5344E−04 6.5339E−04 W−s/C 4.893E−04 4.893E−04 sec C_C5 node4 Gnd 2.1647E−02 2.1606E−02 W−s/C 4.770E−03 4.770E−03 sec C_C6 node5 Gnd 2.1471E−02 2.1361E−02 W−s/C 4.129E−02 4.129E−02 sec C_C7 node6 Gnd 7.9135E−02 7.8444E−02 W−s/C 4.237E−01 4.237E−01 sec C_C8 node7 Gnd 2.8534E−01 3.1338E−01 W−s/C 3.499 3.499 sec C_C9 node8 Gnd 6.6085E−01 1.5496 W−s/C 8.532 49.601 sec C_C10 node9 Gnd 8.7266E−01 24.4877 W−s/C 77.552 88.429 sec R’s R’s 168 mm2 736 mm2 R_R1 Junction node1 1.3480E−01 1.3480E−01 C/W 0.0803 0.0803 C/W R_R2 node1 node2 3.0852E−01 3.0853E−01 C/W 0.1736 0.1736 C/W R_R3 node2 node3 8.0674E−01 8.0676E−01 C/W 0.5491 0.5491 C/W R_R4 node3 node4 5.8520E−01 5.8528E−01 C/W 0.9733 0.9733 C/W R_R5 node4 node5 4.7850E−01 4.8022E−01 C/W 0.1096 0.1096 C/W R_R6 node5 node6 1.3832 1.3916 C/W 0.7361 0.7361 C/W R_R7 node6 node7 4.8520 4.8196 C/W 2.8713 2.8713 C/W R_R8 node7 node8 18.0698 10.0128 C/W 3.0988 8.1070 C/W R_R9 node8 node9 15.7788 31.8880 C/W 10.1005 14.0987 C/W R_R10 node9 Gnd 33.5404 2.7829 C/W 57.2455 25.5115 C/W NOTE: Bold face items represent the package without the external thermal system. R1 Junction C1 R2 C2 R3 C3 Rn Cn Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Ambient (thermal ground) Figure 16. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 C1 R2 C2 R3 C3 Rn Cn Each rung is exactly characterized by its RC−product time constant; amplitudes are the resistances. Ambient (thermal ground) Figure 17. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 10 NCV4290 Table 2. D2PAK 5−Lead Thermal RC Network Models Drain Copper Area (1 oz thick) 241 mm2 (SPICE Deck Format) 788 mm2 241 mm2 Cauer Network 241 mm2 788 mm2 Foster Network 788 mm2 Units Tau Tau Units C_C1 Junction Gnd 9.5070E−06 9.5071E−06 W−s/C 1.000E−06 1.000E−06 sec C_C2 node1 Gnd 3.7150E−05 3.7151E−05 W−s/C 1.000E−05 1.000E−05 sec C_C3 node2 Gnd 1.1261E−04 1.1262E−04 W−s/C 1.000E−04 1.000E−04 sec C_C4 node3 Gnd 6.6126E−04 6.6143E−04 W−s/C 4.893E−04 4.893E−04 sec C_C5 node4 Gnd 2.9986E−02 3.0234E−02 W−s/C 4.770E−03 4.770E−03 sec C_C6 node5 Gnd 5.2806E−02 5.4409E−02 W−s/C 4.129E−02 4.129E−02 sec C_C7 node6 Gnd 3.9578E−01 4.6168E−01 W−s/C 1.294E+00 1.294E+00 sec C_C8 node7 Gnd 9.6950E−01 1.66 W−s/C 2.089E+01 6.008E+01 sec C_C9 node8 Gnd 2.26 37.44 W−s/C 5.824E+01 7.069E+01 sec C_C10 node9 Gnd 231.58 4089.09 W−s/C 241 mm2 788 mm2 sec R’s R’s R_R1 Junction node1 1.3476E−01 1.3476E−01 C/W 0.0803 0.0803 C/W R_R2 node1 node2 3.0817E−01 3.0817E−01 C/W 0.1736 0.1736 C/W R_R3 node2 node3 8.0361E−01 8.0355E−01 C/W 0.5491 0.5491 C/W R_R4 node3 node4 5.7370E−01 5.7346E−01 C/W 0.9733 0.9733 C/W R_R5 node4 node5 2.6250E−01 2.5833E−01 C/W 0.1096 0.1096 C/W R_R6 node5 node6 5.6022E−01 5.3623E−01 C/W 0.5367 0.5367 C/W R_R7 node6 node7 4.0655 3.1454 C/W 1.8971 1.8971 C/W R_R8 node7 node8 38.4592 42.3515 C/W 2.9679 2.9679 C/W R_R9 node8 node9 14.9707 1.9244 C/W 1.9498 4.0572 C/W R_R10 node9 gnd 2.5618E−01 1.6530E−02 C/W NOTE: C/W Bold face items represent the package without the external thermal system. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: n R(t) + Ri ǒ1−e−tńtaui Ǔ i+1 http://onsemi.com 11 110 110 100 100 90 90 80 80 JA (C°/W) JA (C°/W) NCV4290 70 1 oz 60 50 70 1 oz 60 50 2 oz 2 oz 40 40 30 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 30 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) COPPER AREA (mm2) Figure 18. qJA vs. Copper Spreader Area, DPAK 5−Lead Figure 19. qJA vs. Copper Spreader Area, D2PAK 5−Lead 100 Cu Area 168 mm2 Cu Area 736 mm2 R(t) C°/W 10 1.0 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 TIME (sec) Figure 20. Single−Pulse Heating Curves, DPAK 5−Lead 100 Cu Area 241 mm2 10 R(t) C°/W Cu Area 788 mm2 1.0 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 TIME (sec) Figure 21. Single−Pulse Heating Curves, D2PAK 5−Lead http://onsemi.com 12 10 100 1000 NCV4290 100 RJA 736 mm2 C°/W 50% Duty Cycle 10 1.0 20% 10% 5% 2% 1% 0.1 Non−normalized Response Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 10 100 1000 PULSE WIDTH (sec) Figure 22. Duty Cycle for 1” Spreader Boards, DPAK 5−Lead 100 RJA 788 mm2 C°/W 50% Duty Cycle 10 1.0 20% 10% 5% 2% 1% 0.1 0.01 0.000001 Single Pulse Non−normalized Response 0.00001 0.0001 0.001 0.01 0.1 1.0 PULSE WIDTH (sec) Figure 23. Duty Cycle for 1” Spreader Boards, D2PAK 5−Lead ORDERING INFORMATION Device NCV4290DS50R4G Output Voltage Package 5.0 V D2PAK (Pb−Free) NCV4290DT50RKG DPAK (Pb−Free) Shipping† 800 / Tape & Reel 2500 / Tape & Reel †For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 13 NCV4290 PACKAGE DIMENSIONS DPAK 5, CENTER LEAD CROP DT SUFFIX CASE 175AA ISSUE A −T− SEATING PLANE C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R R1 Z A S DIM A B C D E F G H J K L R R1 S U V Z 1 2 3 4 5 U K F J L H D G 5 PL 0.13 (0.005) M T SOLDERING FOOTPRINT* 6.4 0.252 2.2 0.086 0.34 5.36 0.013 0.217 5.8 0.228 10.6 0.417 0.8 0.031 SCALE 4:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.020 0.028 0.018 0.023 0.024 0.032 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.045 BSC 0.170 0.190 0.185 0.210 0.025 0.040 0.020 −−− 0.035 0.050 0.155 0.170 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.51 0.71 0.46 0.58 0.61 0.81 4.56 BSC 0.87 1.01 0.46 0.58 2.60 2.89 1.14 BSC 4.32 4.83 4.70 5.33 0.63 1.01 0.51 −−− 0.89 1.27 3.93 4.32 NCV4290 PACKAGE DIMENSIONS D2PAK, 5 LEAD DS SUFFIX CASE 936A−02 ISSUE C −T− OPTIONAL CHAMFER A E U S K B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. TERMINAL 6 V H 1 2 3 4 5 M D 0.010 (0.254) M T DIM A B C D E G H K L M N P R S U V P N G L R C SOLDERING FOOTPRINT* 8.38 0.33 INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN 1.702 0.067 10.66 0.42 16.02 0.63 3.05 0.12 SCALE 3:1 1.016 0.04 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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