NCV4275 5.0 V Low−Drop Voltage Regulator This industry standard linear regulator has the capability to drive loads up to 450 mA at 5.0 V. It is available in DPAK and D2PAK. This device is pin−for−pin compatible with Infineon part number TLE4275. http://onsemi.com Features • • • • • • 5.0 V, ±2%, 450 mA Output Voltage Very Low Current Consumption Active RESET Reset Low Down to VQ = 1.0 V 500 mV (max) Dropout Voltage Fault Protection ♦ +45 V Peak Transient Voltage ♦ −42 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes • MARKING DIAGRAMS DPAK 5−PIN DT SUFFIX CASE 175AA 1 5 4275 ALYWW x 1 D2PAK 5−PIN DS SUFFIX CASE 936A 1 NCV4275 AWLYYWW 5 Pin 1. I 1 2. RO Tab, 3. GND* 4. D 5. Q * Tab is connected to Pin 3 on all packages I Q Bandgap Reference Error Amplifier A WL, L YY, Y WW Current Limit and Saturation Sense + − Thermal Shutdown ORDERING INFORMATION Reset Generator D RO Figure 1. Block Diagram Semiconductor Components Industries, LLC, 2004 Package Shipping† NCV4275DT DPAK 75 Units/Rail NCV4275DTRK DPAK 2500 Tape & Reel NCV4275DS D2PAK 50 Units/Rail NCV4275DSR4 D2PAK 800 Tape & Reel Device GND August, 2004 − Rev. 8 = Assembly Location = Wafer Lot = Year = Work Week 1 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NCV4275/D NCV4275 PIN FUNCTION DESCRIPTION ÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑ ÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑ ÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Pin No. Symbol 1 I 2 RO 3 GND Description Input; Battery Supply Input Voltage. Bypass to ground with a ceramic capacitor. Reset Output; Open Collector Active Reset (accurate when I > 1.0 V). Ground; Pin 3 internally connected to tab. 4 D Reset Delay; timing capacitor to GND for Reset Delay function. 5 Q Output; ±2.0%, 450 mA output. Use 22 F, ESR < 5.0 Ω to ground. MAXIMUM RATINGS† Rating Min Max Unit −42 45 V − 45 V Output (Q) −1.0 16 V Reset Output (RO) −0.3 25 V Reset Output (RO) −5.0 5.0 mA Reset Delay (D) −0.3 7.0 V Reset Delay (D) −2.0 2.0 mA Operating Range (I) 5.5 42 V ESD Susceptibility (Human Body Model) 2.0 − kV Junction Temperature −40 150 °C Storage Temperature −55 150 °C Reflow (SMD styles only) Note 1 − °C Wave Solder (through hole styles only) Note 2 − 240 Peak (Note 3) 260 Peak Input [I (DC)] Input [I (Peak Transient Voltage)] Lead Temperature Soldering °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. THERMAL CHARACTERISTICS Parameter Test Conditions (Typical Value) Unit DPAK 5−PIN PACKAGE Min Pad Board (Note 4) 1″ Pad Board (Note 5) Junction−to−Tab (psi−JLx, JLx) 4.2 4.7 C/W Junction−to−Ambient (RJA, JA) 100.9 46.8 C/W 0.4 sq. in. Spreader Board (Note 6) 1.2 sq. in. Spreader Board (Note 7) Junction−to−Tab (psi−JLx, JLx) 3.8 4.0 C/W Junction−to−Ambient (RJA, JA) 74.8 41.6 C/W D2PAK 5−PIN PACKAGE 1. 60 seconds max above 183°C. 2. 10 seconds max. 3. −5°C/+0°C allowable conditions. 4. 1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.62″ thick FR4. 5. 1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.62″ thick FR4. 6. 1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.62″ thick FR4. 7. 1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.62″ thick FR4. †During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely. http://onsemi.com 2 NCV4275 ELECTRICAL CHARACTERISTICS (I = 13.5 V; −40°C < TJ < 150°C; unless otherwise noted) Characteristic Test Conditions Min Typ Max Unit Output Voltage 5.0 mA < IQ < 400 mA, 6.0 V < VI < 28 V 4.9 5.0 5.1 V Output Voltage 5.0 mA < IQ < 200 mA, 6.0 V < VI < 40 V 4.9 5.0 5.1 V − 450 700 − mA Output Output Current Limitation Quiescent Current, Iq = II − IQ IQ = 1.0 mA − 150 200 A Quiescent Current, Iq = II − IQ IQ = 250 mA − 10 15 mA Quiescent Current, Iq = II − IQ IQ = 400 mA − 23 35 mA Dropout Voltage IQ = 300 mA, Vdr = VI − VQ − 250 500 mV Load Regulation IQ = 5.0 mA to 400 mA −30 15 30 mV Line Regulation ∆V = 8.0 V to 32 V, IQ = 5.0 mA −25 5.0 25 mV Power Supply Ripple Rejection fr = 100 Hz, Vr = 0.5 Vpp − 60 − dB − − 0.5 − mV/k − 4.5 4.65 4.8 V − 0.2 0.4 V Temperature Output Voltage Drift Reset Timing D and Output RO Reset Switching Threshold Reset Output Low Voltage Rext > 5.0 k, VQ > 1.0 V Reset Output Leakage Current VROH = 5.0 V Reset Charging Current VD = 1.0 V − 0 10 A 3.0 5.5 9.0 A Upper Timing Threshold − 1.5 1.8 2.2 V Lower Timing Threshold − 0.2 0.4 0.7 V Reset Delay Time CD = 47 nF 10 16 22 ms Reset Reaction Time CD = 47 nF − 1.5 4.0 s TYPICAL PERFORMANCE CHARACTERISTICS 1000 Unstable ESR Region for CVout = 1 F − 22 F ESR () 100 Maximum ESR for CVout = 1 F − 22 F 10 Stable ESR Region 1 Minimum ESR for CVout = 1 F 0.1 Unstable Region for CVout = 1 F 0.01 0 100 200 300 400 OUTPUT CURRENT (mA) Figure 2. Output Stability with Output Capacitor ESR http://onsemi.com 3 500 NCV4275 APPLICATION INFORMATION VI II CI1 1000 µF I 1 CI2 100 nF ID 5 IQ Q NCV4275 D 4 CD 47 nF VQ CQ 22 µF 2 3 Rext 5.0 k IRO RO VRO GND Figure 3. Test Circuit Circuit Description The error amplifier compares a temperature−stable reference voltage to a voltage that is proportional to the output voltage (Q) (generated from a resistor divider) and drives the base of a series transistor via a buffer. Saturation control as a function of the load current prevents oversaturation of the output power device, thus preventing excessive substrate current (quiescent current). Typical drop out voltage at 300 mA load is 250 mV, 500 mV maximum. Test voltage for drop out is 5.0 V input. Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 4) is: PD(max) [VI(max) VQ(min)] IQ(max) (1) VI(max)Iq where VI(max) VQ(min) IQ(max) is the maximum input voltage, is the minimum output voltage, is the maximum output current for the application, Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RJA can be calculated: Stability Considerations The input capacitors (CI1 and CI2) are necessary to control line influences. Using a resistor of approximately 1.0 Ω in series with CI2 can solve potential oscillations due to stray inductance and capacitance. The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor CQ shown in Figure 3 should work for most applications, however it is not necessarily the optimized solution. Stability is guaranteed for CQ > 22 F and an ESR ≤ 5.0 Ω. T RJA 150°C A PD (2) The value of RJA can then be compared with those in the package section of the data sheet. Those packages with RJA’s less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IQ II VI SMART REGULATOR VQ } Control Features Iq Figure 4. Single Output Regulator with Key Performance Parameters Labeled http://onsemi.com 4 NCV4275 Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RJA: RJA RJC RCS RSA where RJC is the junction−to−case thermal resistance, RCS is the case−to−heatsink thermal resistance, RSA is the heatsink−to−ambient thermal resistance. RJC appears in the package section of the data sheet. Like RJA, it too is a function of package type. RCS and RSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D. (3) VI t < Reset Reaction Time VQ VQ,rt t Reset Charge Current dVD dt CD VD Upper Timing Threshold Lower Timing Threshold t Reset Delay Time Reset Reaction Time VRO t Power−on−Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Figure 5. Reset Timing http://onsemi.com 5 Overload at Output NCV4275 Table 1. DPAK 5−Lead Thermal RC Network Models Drain Copper Area (1 oz thick) 168 mm2 (SPICE Deck Format) 736 mm2 168 mm2 Cauer Network 168 mm2 736 mm2 Foster Network 736 mm2 Units Tau Tau Units C_C1 Junction Gnd 1.00E−06 1.00E−06 W−s/C 1.36E−08 1.361E−08 sec C_C2 node1 Gnd 1.00E−05 1.00E−05 W−s/C 7.41E−07 7.411E−07 sec C_C3 node2 Gnd 6.00E−05 6.00E−05 W−s/C 1.04E−05 1.029E−05 sec C_C4 node3 Gnd 1.00E−04 1.00E−04 W−s/C 3.91E−05 3.737E−05 sec C_C5 node4 Gnd 4.36E−04 3.64E−04 W−s/C 1.80E−03 1.376E−03 sec C_C6 node5 Gnd 6.77E−02 1.92E−02 W−s/C 3.77E−01 2.851E−02 sec C_C7 node6 Gnd 1.51E−01 1.27E−01 W−s/C 3.79E+00 9.475E−01 sec C_C8 node7 Gnd 4.80E−01 1.018 W−s/C 2.65E+01 1.173E+01 sec C_C9 node8 Gnd 3.740 2.955 W−s/C 8.71E+01 8.59E+01 sec C_C10 node9 Gnd 10.322 0.438 W−s/C 168 mm2 736 mm2 sec R’s R’s R_R1 Junction node1 0.015 0.015 C/W 0.0123 0.0123 C/W R_R2 node1 node2 0.08 0.08 C/W 0.0585 0.0585 C/W R_R3 node2 node3 0.4 0.4 C/W 0.0304 0.0287 C/W R_R4 node3 node4 0.2 0.2 C/W 0.3997 0.3772 C/W R_R5 node4 node5 2.97519 2.6171 C/W 3.115 2.68 C/W R_R6 node5 node6 8.2971 1.6778 C/W 3.571 1.38 C/W R_R7 node6 node7 25.9805 7.4246 C/W 12.851 5.92 C/W R_R8 node7 node8 46.5192 14.9320 C/W 35.471 7.39 C/W R_R9 node8 node9 17.7808 19.2560 C/W 46.741 28.94 C/W node9 Gnd 0.1 0.1758 C/W R_R10 NOTE: Bold face items represent the package without the external thermal system. http://onsemi.com 6 C/W NCV4275 Table 2. D2PAK 5−Lead Thermal RC Network Models Drain Copper Area (1 oz thick) 241 mm2 (SPICE Deck Format) 788 mm2 241 mm2 Cauer Network 241 mm2 788 mm2 Foster Network 653 mm2 Units Tau Tau Units C_C1 Junction Gnd 1.00E−06 1.00E−06 W−s/C 1.361E−08 1.361E−08 sec C_C2 node1 Gnd 1.00E−05 1.00E−05 W−s/C 7.411E−07 7.411E−07 sec C_C3 node2 Gnd 6.00E−05 6.00E−05 W−s/C 1.005E−05 1.007E−05 sec C_C4 node3 Gnd 1.00E−04 1.00E−04 W−s/C 3.460E−05 3.480E−05 sec C_C5 node4 Gnd 2.82E−04 2.87E−04 W−s/C 7.868E−04 8.107E−04 sec C_C6 node5 Gnd 5.58E−03 5.95E−03 W−s/C 7.431E−03 7.830E−03 sec C_C7 node6 Gnd 4.25E−01 4.61E−01 W−s/C 2.786E+00 2.012E+00 sec C_C8 node7 Gnd 9.22E−01 2.05 W−s/C 2.014E+01 2.601E+01 sec C_C9 node8 Gnd 1.73 4.88 W−s/C 1.134E+02 1.218E+02 sec C_C10 node9 Gnd 7.12 1.31 W−s/C 241 mm2 653 mm2 sec R’s R’s R_R1 Junction node1 0.015 0.0150 C/W 0.0123 0.0123 C/W R_R2 node1 node2 0.08 0.0800 C/W 0.0585 0.0585 C/W R_R3 node2 node3 0.4 0.4000 C/W 0.0257 0.0260 C/W R_R4 node3 node4 0.2 0.2000 C/W 0.3413 0.3438 C/W R_R5 node4 node5 1.85638 1.8839 C/W 1.77 1.81 C/W R_R6 node5 node6 1.23672 1.2272 C/W 1.54 1.52 C/W R_R7 node6 node7 9.81541 5.3383 C/W 4.13 3.46 C/W R_R8 node7 node8 33.1868 18.9591 C/W 6.27 5.03 C/W R_R9 node8 node9 27.0263 13.3369 C/W 60.80 29.30 C/W node9 gnd 1.13944 0.1191 C/W R_R10 NOTE: C/W Bold face items represent the package without the external thermal system. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: n R(t) Ri 1−e−ttaui i1 http://onsemi.com 7 110 110 100 100 90 90 80 80 70 JA (C°/W) JA (C°/W) NCV4275 1 oz 60 2 oz 70 60 1 oz 2 oz 50 50 40 40 30 150 200 250 300 350 400 450 500 550 600 650 700 750 30 150 200 250 300 350 400 450 500 550 600 650 700 750 COPPER AREA (mm2) COPPER AREA (mm2) Figure 6. JA vs. Copper Spreader Area, DPAK 5−Lead Figure 7. JA vs. Copper Spreader Area, D2PAK 5−Lead 100 Cu Area 167 mm2 Cu Area 736 mm2 R(t) C°/W 10 1.0 sqrt(t) 0.1 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 TIME (sec) Figure 8. Single−Pulse Heating Curves, DPAK 5−Lead 100 Cu Area 167 mm2 Cu Area 736 mm2 R(t) C°/W 10 1.0 0.1 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 TIME (sec) Figure 9. Single−Pulse Heating Curves, D2PAK 5−Lead http://onsemi.com 8 10 100 1000 NCV4275 100 50% Duty Cycle RJA 736 mm2 C°/W 20% 10 1.0 10% 5% 2% 1% 0.1 Non−normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 10 100 1000 PULSE WIDTH (sec) Figure 10. Duty Cycle for 1” Spreader Boards, DPAK 5−Lead 100 RJA 788 mm2 C°/W 50% Duty Cycle 10 20% 10% 5% 1.0 2% 1% 0.1 Non−normalized Response 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 PULSE WIDTH (sec) Figure 11. Duty Cycle for 1” Spreader Boards, D2PAK 5−Lead R1 Junction C1 R2 C2 R3 C3 Rn Cn Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Ambient (thermal ground) Figure 12. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 C1 R2 C2 R3 C3 Rn Cn Each rung is exactly characterized by its RC−product time constant; amplitudes are the resistances. Ambient (thermal ground) Figure 13. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 9 NCV4275 PACKAGE DIMENSIONS DPAK 5 CENTER LEAD CROP DT SUFFIX CASE 175AA−01 ISSUE O −T− SEATING PLANE C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R R1 Z A S 1 2 3 4 5 U K F J L H D G 5 PL 0.13 (0.005) M T http://onsemi.com 10 DIM A B C D E F G H J K L R R1 S U V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.020 0.028 0.018 0.023 0.024 0.032 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.045 BSC 0.170 0.190 0.185 0.210 0.025 0.040 0.020 −−− 0.035 0.050 0.155 0.170 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.51 0.71 0.46 0.58 0.61 0.81 4.56 BSC 0.87 1.01 0.46 0.58 2.60 2.89 1.14 BSC 4.32 4.83 4.70 5.33 0.63 1.01 0.51 −−− 0.89 1.27 3.93 4.32 NCV4275 PACKAGE DIMENSIONS D2PAK 5 LEAD DS SUFFIX CASE 936A−02 ISSUE B −T− OPTIONAL CHAMFER A B V H 1 2 3 4 5 M D M U S K 0.010 (0.254) TERMINAL 6 E T L P N G R C http://onsemi.com 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. DIM A B C D E G H K L M N P R S U V INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 REF 2.946 REF 5.080 MIN 6.350 MIN NCV4275 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 12 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCV4275/D