ONSEMI NTLJD4150PTBG

NTLJD4150P
Power MOSFET
−30 V, −3.4 A, mCoolt Dual P−Channel,
2x2 mm WDFN Package
Features
http://onsemi.com
• WDFN 2x2 mm Package Provides Exposed Drain Pad for
•
•
•
•
Excellent Thermal Conduction
Footprint Same as SC−88 Package
Low Profile (< 0.8 mm) for Easy Fit in Thin Environments
Bidirectional Current Flow with Common Source Configuration
This is a Pb−Free Device
RDS(on) Max
V(BR)DSS
ID Max (Note 1)
135 mW @ 10 V
−30 V
−3.4 A
200 mW @ 4.5 V
S1
S2
Applications
• Li−Ion Battery Charging and Protection Circuits
• LED Backlight, Flashlight
• Dual−High Side Load Switch
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−30
V
Gate−to−Source Voltage
VGS
±20
V
ID
−2.7
A
Continuous Drain Current
(Note 1)
Power Dissipation
(Note 1)
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Steady
State
TA = 85°C
Power Dissipation
(Note 2)
Pulsed Drain Current
1.5
ID
TA = 85°C
Operating Junction and Storage Temperature
Source Current (Body Diode) (Note 2)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
D2
MARKING
DIAGRAM
D1
1
2
3
WDFN6
CASE 506AN
JE
M
G
2.3
tp = 10 ms
D2
P−CHANNEL MOSFET
JE M G 6
5
G
4
W
TA = 25°C
TA = 25°C
D1
P−CHANNEL MOSFET
Pin 1
−3.4
PD
TA = 25°C
Steady
State
G2
−2.0
t≤5s
Continuous Drain Current
(Note 2)
G1
−1.8
= Specific Device Code
= Date Code
= Pb−Free Package
A
(Note: Microdot may be in either location)
PIN CONNECTIONS
−1.4
PD
0.7
W
IDM
−14
A
TJ,
TSTG
−55 to
150
°C
IS
−1.8
A
TL
°C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size.
D1
S1
1
G1
2
6
D1
5
G2
4
S2
D2
D2
3
(Top View)
ORDERING INFORMATION
Device
Package
Shipping †
NTLJD4150PTBG
WDFN6
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 0
1
Publication Order Number:
NTLJD4150P/D
NTLJD4150P
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
Junction−to−Ambient – Steady State (Note 3)
RqJA
83
Junction−to−Ambient – Steady State Min Pad (Note 4)
RqJA
177
Junction−to−Ambient – t ≤ 5 s (Note 3)
RqJA
54
Unit
SINGLE OPERATION (SELF−HEATED)
°C/W
DUAL OPERATION (EQUALLY HEATED)
Junction−to−Ambient – Steady State (Note 3)
RqJA
58
Junction−to−Ambient – Steady State Min Pad (Note 3)
RqJA
133
Junction−to−Ambient – t ≤ 5 s (Note 3)
RqJA
40
°C/W
3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu).
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Conditions
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
−30.0
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = −250 mA, Ref to 25°C
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
VDS = −24 V, VGS = 0 V
1.9
mV/°C
TJ = 25°C
−1.0
TJ = 85°C
−5.0
IGSS
VDS = 0 V, VGS = ±20 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = −250 mA
Gate Threshold
Temperature Coefficient
VGS(TH)/TJ
Gate−to−Source Leakage Current
V
mA
±100
nA
−2.0
V
ON CHARACTERISTICS (Note 5)
Drain−to−Source On−Resistance
−1.5
0.4
RDS(on)
Forward Transconductance
−1.0
gFS
mV/°C
VGS = −10 V, ID = −4.0 A
95
135
mW
VGS = −4.5 V, ID = −3.0 A
156
200
mW
VDS = −10 V, ID = −1.0 A
1.5
S
300
pF
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
VGS = 0 V, f = 1 MHz, VDS = −15 V
50
CRSS
30
Total Gate Charge
QG(TOT)
3.6
Threshold Gate Charge
QG(TH)
4.5
nC
0.44
VGS =−4.5 V, VDS = −15 V, ID = −2.0 A
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
1.54
RG
10.6
W
td(ON)
7.0
ns
Gate Resistance
0.79
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = −4.5 V, VDD = −24 V,
ID = −3.0 A, RG = 2 W
tf
16.2
11.8
8.8
5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
NTLJD4150P
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued)
Parameter
Symbol
Test Conditions
Min
Typ
Max
TJ = 25°C
−0.85
−1.0
TJ = 85°C
−0.77
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Recovery Voltage
Reverse Recovery Time
VSD
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V,
IS = −2.0 A
V
8.9
VGS = 0 V, dISD/dt = 100 A/ms,
IS = −2.0 A
QRR
6.2
2.9
3.0
5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
3
ns
nC
NTLJD4150P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
−6 V
−ID, DRAIN CURRENT (AMPS)
−10V
9 to
8 −7V
−4.8 V
8
TJ = 25°C
VDS ≥ 10 V
−ID, DRAIN CURRENT (AMPS)
10
−4.6 V
−4.2 V
7
6
−3.8 V
5
−3.4 V
4
3
−3.0 V
2
1
−2.6 V
7
6
5
4
3
TJ = 125°C
2
TJ = 85°C
TJ = 25°C
1
TJ = −55°C
0
0
5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
VGS = −10 V
0.16
0.14
TJ = 125°C
0.12
TJ = 85°C
0.10
0.08
TJ = 25°C
0.06
TJ = −55°C
0.04
1.0
2.0
3.0
4.0
1.0
TJ = 25°C
0.9
0.8
0.7
0.6
0.5
0.4
VGS = −4.5 V
0.3
0.2
VGS = −10 V
0.1
0
1
2
3
−ID, DRAIN CURRENT (AMPS)
4
5
6
7
8
9
10
−ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.6
1000
VGS = 0 V
I = −3.0 A
1.5 D
VGS = −10 V
1.4
−IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
4
3
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.20
0.18
2
1
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8
1.3
1.2
1.1
1.0
0.9
100
TJ = 125°C
TJ = 100°C
10
1
TJ = 85°C
0.8
0.7
−50
−25
0
25
50
75
100
125
150
0.1
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
http://onsemi.com
4
30
NTLJD4150P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
VGS = 0 V
TJ = 25°C
400
Ciss
300
200
Coss
100
0
0
Crss
5
10
15
20
25
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
6
5
VDS
16
4
QGS
QGD
VGS
12
3
8
2
4
1
0
30
Figure 7. Capacitance Variation
ID = −3.0 A
TJ = 25°C
0
0 0.2 0.40.60.8 1 1.21.41.61.8 2 2.2 2.4 2.62.8 3 3.23.43.6
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
4
−Is, SOURCE CURRENT (AMPS)
VDD = −24 V
ID = −3.0 A
VGS = −4.5 V
tr
td(off)
tf
td(on)
10
VGS = 0 V
TJ = 25°C
3
2
1
0
1
1
10
RG, GATE RESISTANCE (OHMS)
100
0
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
10
−ID, DRAIN CURRENT (AMPS)
t, TIME (ns)
20
QT
−VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
500
10 ms
100 ms
1
1 ms
10 ms
*See Note 2 on Page 1
0.1
TC = 25°C
TJ = 150°C
SINGLE PULSE
dc
0.01
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1
10
100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
5
NTLJD4150P
EFFECTIVE TRANSIENT THERMAL RESISTANCE
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
1000
100
D = 0.5
0.2
0.1
*See Note 2 on Page 1
10
P(pk)
0.05
0.02
1 0.01
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
t, TIME (s)
Figure 12. Thermal Response
http://onsemi.com
6
1
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TA = P(pk) RqJA(t)
10
100
1000
NTLJD4150P
PACKAGE DIMENSIONS
WDFN6 2x2
CASE 506AN−01
ISSUE C
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
ÍÍÍ
ÍÍÍ
E
PIN ONE
REFERENCE
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
J
0.10 C
2X
0.10 C
2X
A3
0.10 C
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
2.00 BSC
0.57
0.77
2.00 BSC
0.90
1.10
0.65 BSC
0.25 REF
0.20
0.30
0.15 REF
A
6X
0.08 C
C
SEATING
PLANE
D2
D2
6X
SOLDERMASK DEFINED
MOUNTING FOOTPRINT*
A1
e
L
1
2.30
6X
6X
0.35
0.43
4X
3
1
0.65
PITCH
2X E2
6X
K
4
6
6X
J
BOTTOM VIEW
b
0.25
6X
0.10 C A
0.05 C
B
2X
NOTE 3
0.72
1.05
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTLJD4150P/D