ONSEMI NTLUS4930N

NTLUS4930N
Power MOSFET
30 V, 6.1 A, Single N−Channel,
2.0x2.0x0.55 mm mCoolt UDFN6 Package
Features
• UDFN Package with Exposed Drain Pads for Excellent Thermal
•
•
•
•
•
Conduction
Low Profile UDFN 2.0 x 2.0 x 0.55 mm for Board Space Saving
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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MOSFET
V(BR)DSS
30 V
RDS(on) MAX
ID MAX
36 mW @ 4.5 V
6.1 A
28.5 mW @ 10 V
5.5 A
D
Applications
• Battery Switch
• Power Load Switch
• DC−DC Converters
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain
Current (Note 1)
Continuous Drain
Current (Note 1)
Steady
State
Power Dissipation (Note 1)
Continuous Drain
Current (Note 2)
TA = 25°C
Symbol
Value
Unit
VDSS
30
V
VGS
±20
V
ID
6.1
A
TA = 85°C
4.4
t≤5s
TA = 25°C
9.3
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Steady
State
TA = 25°C
PD
S
D
W
1.65
Pin 1
ID
A
3.8
MARKING DIAGRAM
1
UDFN6
AD MG
(mCOOL])
G
CASE 517BG
AD = Specific Device Code
M = Date Code
G = Pb−Free Package
3.8
TA = 85°C
(*Note: Microdot may be in either location)
2.8
Power Dissipation (Note 2)
TA = 25°C
PD
0.65
W
Pulsed Drain Current
tp = 10 ms
IDM
19
A
TJ,
TSTG
-55 to
150
°C
Source Current (Body Diode) (Note 1)
IS
1.65
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
MOSFET Operating Junction and Storage
Temperature
S
N−CHANNEL MOSFET
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size
of 30 mm2, 2 oz. Cu.
PIN CONNECTIONS
D
1
D
2
G
3
6
D
5
D
4
S
D
S
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
February, 2013 − Rev. 1
1
Publication Order Number:
NTLUS4930N/D
NTLUS4930N
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
Junction-to-Ambient – Steady State (Note 3)
RθJA
75.7
Junction-to-Ambient – t ≤ 5 s (Note 3)
RθJA
32.9
Junction-to-Ambient – Steady State min Pad (Note 4)
RθJA
191.4
Unit
°C/W
3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = 250 mA, ref to 25°C
Typ
Max
Units
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V,
VDS = 24 V
Gate-to-Source Leakage Current
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
V
+16
TJ = 25°C
mV/°C
1.0
mA
10
mA
2.2
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temp. Coefficient
Drain-to-Source On Resistance
VGS(TH)/TJ
1.8
4.4
RDS(on)
Forward Transconductance
1.2
gFS
mV/°C
mW
VGS = 10 V, ID = 6.1 A
19
28.5
VGS = 4.5 V, ID = 5.5 A
27
36
VDS = 1.5 V, ID = 6.0 A
16
S
476
pF
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VGS = 0 V, f = 1 MHz,
VDS = 15 V
197
100
Total Gate Charge
QG(TOT)
4.8
Threshold Gate Charge
QG(TH)
0.4
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
VGS = 4.5 V, VDS = 15 V;
ID = 5.5 A
nC
1.54
2.15
QG(TOT)
VGS = 10 V, VDS = 15 V;
ID = 5.5 A
8.7
nC
8.7
ns
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
tr
td(OFF)
Fall Time
VGS = 4.5 V, VDD = 15 V,
ID = 5.5 A, RG = 3 W
tf
14.4
9.1
3.3
SWITCHING CHARACTERISTICS, VGS = 10 V (Note 6)
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
tr
td(OFF)
Fall Time
ns
4.1
VGS = 10 V, VDD = 15 V,
ID = 6.1 A, RG = 3 W
tf
12.2
11.6
2.2
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
VGS = 0 V,
IS = 1.65 A
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
TJ = 25°C
0.80
TJ = 125°C
0.67
1.0
V
NTLUS4930N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
14.6
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 3.3 A
QRR
ns
6.8
7.8
5.4
nC
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
DEVICE ORDERING INFORMATION
Package
Shipping†
NTLUS4930NTAG
UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS4930NTBG
UDFN6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NTLUS4930N
TYPICAL CHARACTERISTICS
3.2 V
12
10
3.0 V
8
6
2.8 V
4
VGS = 2.6 V
0
1
2
3
4
5
12
10
8
TJ = 25°C
6
4
TJ = 125°C
TJ = −55°C
0
0.030
0.026
0.022
4
5
4.5
5.5
6.5
7.5
8.5
9.5
VGS, GATE VOLTAGE (V)
0.032
0.030
TJ = 25°C
VGS = 4.5 V
0.028
0.026
0.024
0.022
VGS = 10 V
0.020
0.018
0.016
0.014
0.012
0.010
4
5
6
7
8
9
10
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10,000
1.6
VGS = 0 V
VGS = 10 V
ID = 6 A
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
3
Figure 2. Transfer Characteristics
0.034
1.4
2
Figure 1. On−Region Characteristics
ID = 6 A
1.5
1
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.038
3.5
14
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.042
0.018
VDS = 5 V
16
2
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
18
3.4 V
TJ = 25°C
14
2
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
3.8 V
16
20
3.6 V
4.0 V to 10 V
18
ID, DRAIN CURRENT (A)
20
1.3
1.2
1.1
1.0
0.9
TJ = 150°C
1000
TJ = 125°C
100
10
0.8
0.7
−50
−25
0
25
50
75
100
125
150
1
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTLUS4930N
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
600
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
700
Ciss
500
400
300
Coss
200
Crss
100
0
0
5
10
15
20
30
25
10
QT
8
6
QGS
4
QGD
VGS = 10 V
VDD = 15 V
ID = 6 A
TJ = 25°C
2
0
0
2
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
8
10
12
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
20
VGS = 10 V
VDD = 15 V
ID = 6 A
18
IS, SOURCE CURRENT (A)
td(off)
tr
10
td(on)
tf
1
VGS = 0 V
16
14
12
TJ = 125°C
TJ = 25°C
10
8
6
4
2
0.1
1
10
0
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
ID, DRAIN CURRENT (A)
t, TIME (ns)
6
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
100
4
0 V < VGS < 10 V
10 ms
10
100 ms
1 ms
1
10 ms
0.1
0.01
RDS(on) Limit
Thermal Limit
Package Limit
0.01
0.1
1
dc
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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5
100
NTLUS4930N
R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
(NORMALIZED)
TYPICAL CHARACTERISTICS
1.1
1.0
0.9
0.8
0.7
0.6
0.5
Duty Cycle = 0.5
0.4
0.3
0.2
0.1
0
0.2
0.05
0.02
0.01
0.1
Single Pulse
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
t, TIME (s)
Figure 12. FET Thermal Response
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6
1E+00
1E+01
1E+02
1E+03
NTLUS4930N
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517BG−01
ISSUE A
D
B
A
ÍÍÍ
ÍÍÍ
ÍÍÍ
PIN ONE
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. CENTER TERMINAL LEAD IS OPTIONAL. CENTER TERMINAL
IS CONNECTED TO TERMINAL LEAD # 4.
6. LEADS 1, 2, 5 AND 6 ARE TIED TO THE FLAG.
ÇÇ ÉÉ
ÉÉ
ÇÇ
ÉÉ
EXPOSED Cu
PLATING
E
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTIONS
0.10 C
0.10 C
L
TOP VIEW
DETAIL B
A
A3
0.10 C
L
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
0.08 C
NOTE 4
A1
L
SEATING
PLANE
D2
DETAIL A
6X
C
SIDE VIEW
1
L2
3
RECOMMENDED
MOUNTING FOOTPRINT*
e
2.30
b1
0.10 C A
E2
0.05 C
K
6
4
J
J1
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.25
0.35
0.51
0.61
2.00 BSC
1.00
1.20
2.00 BSC
1.10
1.30
0.65 BSC
0.15 REF
0.27 BSC
0.65 BSC
0.20
0.30
--0.10
0.20
0.30
DIM
A
A1
A3
b
b1
D
D2
E
E2
e
K
J
J1
L
L1
L2
B
1.10
6X
NOTE 5
6X
0.35
0.43
1
6X
b
0.60
1.25
0.10 C A
0.05 C
B
0.35
NOTE 3
BOTTOM VIEW
0.34
0.65
PITCH
PACKAGE
OUTLINE
0.66
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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NTLUS4930N/D