NTTD1P02R2 Power MOSFET −1.45 Amps, −20 Volts P−Channel Enhancement Mode Dual Micro8t Package http://onsemi.com Features • • • • • • • −1.45 AMPERES −20 VOLTS 160 mW @ VGS = −4.5 Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided Pb−Free Package is Available Dual P−Channel D Applications • Power Management in Portable and Battery−Powered Products, G i.e.: Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating MARKING DIAGRAM & PIN ASSIGNMENT Symbol Value Unit Drain−to−Source Voltage VDSS −20 V Gate−to−Source Voltage − Continuous VGS "8.0 V Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Pulsed Drain Current (Note 3) RqJA PD ID ID IDM 250 0.50 −1.45 −1.15 −10 °C/W W A A A Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ TA = 25°C Continuous Drain Current @ TA = 70°C Pulsed Drain Current (Note 3) RqJA PD ID ID IDM 125 1.0 −2.04 −1.64 −16 °C/W W A A A TJ, Tstg −55 to +150 °C (Note: Microdot may be in either location) Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = −20 Vdc, VGS = −4.5 Vdc, Peak IL = −3.5 Apk, L = 5.6 mH, RG = 25 W) EAS 35 mJ ORDERING INFORMATION Maximum Lead Temperature for Soldering Purposes for 10 seconds TL Operating and Storage Temperature Range 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Minimum FR−4 or G−10 PCB, Steady State. 2. Mounted onto a 2” square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick single sided), Steady State. 3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 2 1 D1 D1 D2 D2 8 8 WW BCG G 1 Micro8 CASE 846A STYLE 2 BC WW G 1 S1 G1 S2 G2 = Specific Device Code = Work Week = Pb−Free Package Device Package Shipping† NTTD1P02R2 Micro8 4000/Tape & Reel Micro8 (Pb−Free) 4000/Tape & Reel NTTD1P02R2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTTD1P02R2/D NTTD1P02R2 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Note 4) Characteristic Symbol Min Typ Max Unit −20 − − −12 − − − − − − −1.0 −10 − − −100 − − 100 −0.7 − −0.95 2.3 −1.4 − − − − 0.130 0.175 0.190 0.160 0.250 − gFS − 2.5 − Mhos Ciss − 265 − pF Coss − 100 − Crss − 60 − td(on) − 10 − tr − 25 − td(off) − 30 − OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = −250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = −20 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = −20 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = −8 Vdc, VDS = 0 Vdc) IGSS Gate−Body Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = −250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = −4.5 Vdc, ID = −1.45 Adc) (VGS = −2.7 Vdc, ID = −0.7 Adc) (VGS = −2.5 Vdc, ID = −0.7 Adc) RDS(on) Forward Transconductance (VDS = −10 Vdc, ID = −0.7 Adc) Vdc W DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = −16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) SWITCHING CHARACTERISTICS (Notes 5 & 6) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = −16 Vdc, ID = −1.45 Adc, VGS = −4.5 Vdc, RG = 6.0 W) Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = −16 Vdc, ID = −0.7 Adc, VGS = −4.5 Vdc, RG = 6.0 W) Fall Time Total Gate Charge Gate−Source Charge Gate−Drain Charge (VDS = −16 Vdc, VGS = −4.5 Vdc, ID = −1.45 Adc) tf − 25 − td(on) − 10 − tr − 20 − td(off) − 30 − tf − 20 − Qtot − 5.0 10 ns ns nC Qgs − 1.5 − Qgd − 2.0 − VSD − − −0.91 −0.72 −1.1 − Vdc trr − 25 − ns ta − 13 − tb − 12 − QRR − 0.015 − BODY−DRAIN DIODE RATINGS (Note 5) Diode Forward On−Voltage (IS = −1.45 Adc, VGS = 0 Vdc) (IS = −1.45 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = −1.45 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge are mandatory. 5. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 mC NTTD1P02R2 −2.3 V TJ = 25°C −2.1 V −8 V −1.9 V 1 −1.7 V VGS = −1.5 V 0 0.25 0.5 0.75 1 1.25 1.5 2 TJ = −55°C 1 0 2 1.5 2.5 3 Figure 2. Transfer Characteristics 0.2 0.1 0 4 2 6 8 12 10 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C VGS = −2.5 V 0.2 VGS = −2.7 V VGS = −4.5 V 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 −ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.6 100 −IDSS, LEAKAGE (nA) ID = −1.45 A VGS = −4.5 V 1.2 1 0.8 −25 3.5 0.3 Figure 3. On−Resistance versus Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1 Figure 1. On−Region Characteristics ID = −1.45 A TJ = 25°C 0.6 −50 TJ = 25°C −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.3 1.4 0.5 TJ = 100°C −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.4 0 VDS ≥ −10 V 0 1.75 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 3 −2.5 V −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) 3 −2.7 V −2.9 V −3.1 V −3.3 V −3.7 V −4.5 V 2 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 VGS = 0 V TJ = 125°C TJ = 100°C 10 1 4 Figure 5. On−Resistance Variation with Temperature 8 12 16 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 20 VDS = 0 V C, CAPACITANCE (pF) Ciss 600 VGS = 0 V TJ = 25°C Crss 400 Ciss 200 Coss 0 Crss 5 10 0 −VGS −VDS 5 10 15 20 5 20 QT 18 16 4 14 −VGS 3 Q1 12 10 Q2 8 2 1 0 −VDS 0 1 2 6 ID = −1.45 A TJ = 25°C 3 4 5 4 6 2 0 Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 800 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTTD1P02R2 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation 100 tr td (off) tf 10 td (on) 1 10 1 100 ID , DRAIN CURRENT (AMPS) −IS, SOURCE CURRENT (AMPS) t, TIME (ns) VDD = −16 V ID = −1.45 A VGS = −4.5 V 10 1.2 0.8 0.4 0 100 VGS = 0 V TJ = 25°C 1.6 0.4 0.5 0.6 0.7 0.8 1 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current VGS = 8 V SINGLE PULSE TC = 25°C di/dt IS 100 ms trr 1 ms 1 ta tb TIME 10 ms 0.25 IS tp 0.1 0.01 0.9 RG, GATE RESISTANCE (OHMS) IS RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 dc 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 12. Diode Reverse Recovery Waveform Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 NTTD1P02R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (°C/W) 1000 100 10 D = 0.5 0.2 0.1 0.05 P(pk) 0.02 0.01 1 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.1 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 t, TIME (s) Figure 13. Thermal Response http://onsemi.com 5 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E+01 1.0E+02 1.0E+03 NTTD1P02R2 PACKAGE DIMENSIONS Micro8t CASE 846A−02 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A−01 OBSOLETE, NEW STANDARD 846A−02. D HE PIN 1 ID −T− E e b 8 PL 0.08 (0.003) T B M S A DIM A A1 b c D E e L HE STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. S SEATING PLANE A 0.038 (0.0015) A1 L c MILLIMETERS NOM MAX −− 1.10 0.08 0.15 0.33 0.40 0.18 0.23 3.00 3.10 3.00 3.10 0.65 BSC 0.40 0.55 0.70 4.75 4.90 5.05 MIN −− 0.05 0.25 0.13 2.90 2.90 INCHES NOM −− 0.003 0.013 0.007 0.118 0.118 0.026 BSC 0.016 0.021 0.187 0.193 MIN −− 0.002 0.010 0.005 0.114 0.114 MAX 0.043 0.006 0.016 0.009 0.122 0.122 0.028 0.199 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 3.20 0.126 6X 8X 4.24 0.167 0.65 0.0256 5.28 0.208 SCALE 8:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro8 is a registered trademark of International Rectifier Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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