ONSEMI NTMD3P03R2G

NTMD3P03R2
Power MOSFET
−3.05 Amps, −30 Volts
Dual P−Channel SOIC−8
Features
•
•
•
•
•
•
•
•
High Efficiency Components in a Dual SOIC−8 Package
High Density Power MOSFET with Low RDS(on)
Miniature SOIC−8 Surface Mount Package − Saves Board Space
Diode Exhibits High Speed with Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for the SOIC−8 Package is Provided
Pb−Free Package is Available
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VDSS
RDS(ON) Typ
ID Max
−30 V
85 mW @ −10 V
−3.05 A
Applications
P−Channel
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery−Powered Products, i.e.:
D
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
G
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−30
V
Gate−to−Source Voltage − Continuous
VGS
±20
V
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
RqJA
PD
ID
ID
IDM
171
0.73
−2.34
−1.87
−8.0
°C/W
W
A
A
A
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
RqJA
PD
ID
ID
IDM
100
1.25
−3.05
−2.44
−12
°C/W
W
A
A
A
Thermal Resistance −
Junction−to−Ambient (Note 3)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
RqJA
PD
ID
ID
IDM
62.5
2.0
−3.86
−3.1
−15
°C/W
W
A
A
A
TJ, Tstg
−55 to
+150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = −30 Vdc, VGS = −4.5 Vdc, Peak IL
= −7.5 Apk, L = 5 mH, RG = 25 W)
EAS
140
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
Rating
Operating and Storage
Temperature Range
February, 2006 − Rev. 2
MARKING DIAGRAM*
AND PIN ASSIGNMENT
8
D1 D1 D2 D2
1
SOIC−8
SUFFIX NB
CASE 751
STYLE 11
8
ED3P03
AYWW G
G
1
S1 G1 S2 G2
ED3P03= Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Minimum FR−4 or G−10 PCB, t = Steady State.
2. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick
single sided), t = steady state.
3. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick
single sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
© Semiconductor Components Industries, LLC, 2006
S
1
Shipping†
Device
Package
NTMD3P03R2
SOIC−8
2500/Tape & Reel
SOIC−8
(Pb−Free)
2500/Tape & Reel
NTMD3P03R2G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
Publication Order Number:
NTMD3P03R2/D
NTMD3P03R2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5)
Characteristic
Symbol
Min
Typ
Max
Unit
−30
−
−
−30
−
−
−
−
−
−
−
−
−1.0
−20
−2.0
−
−
−100
−
−
100
−1.0
−
−1.7
3.6
−2.5
−
−
−
0.063
0.090
0.085
0.125
gFS
−
5.0
−
Mhos
Ciss
−
520
750
pF
Coss
−
170
325
Crss
−
70
135
td(on)
−
12
22
tr
−
16
30
td(off)
−
45
80
tf
−
45
80
td(on)
−
16
−
tr
−
42
−
td(off)
−
32
−
tf
−
35
−
Qtot
−
16
25
Qgs
−
2.0
−
Qgd
−
4.5
−
VSD
−
−
−0.96
−0.78
−1.25
−
Vdc
trr
−
34
−
ns
ta
−
18
−
tb
−
16
−
QRR
−
0.03
−
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = −250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = −24 Vdc, VGS = 0 Vdc, TJ = 25°C)
(VDS = −24 Vdc, VGS = 0 Vdc, TJ = 125°C)
(VDS = −30 Vdc, VGS = 0 Vdc, TJ = 25°C)
IDSS
Gate−Body Leakage Current
(VGS = −20 Vdc, VDS = 0 Vdc)
IGSS
Gate−Body Leakage Current
(VGS = +20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = −250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = −10 Vdc, ID = −3.05 Adc)
(VGS = −4.5 Vdc, ID = −1.5 Adc)
RDS(on)
Forward Transconductance (VDS = −15 Vdc, ID = −3.05 Adc)
Vdc
W
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = −24 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 6 and 7)
Turn−On Delay Time
(VDD = −24 Vdc, ID = −3.05 Adc,
VGS = −10 Vdc,
RG = 6.0 W)
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
(VDD = −24 Vdc, ID = −1.5 Adc,
VGS = −4.5 Vdc,
RG = 6.0 W)
Rise Time
Turn−Off Delay Time
Fall Time
Total Gate Charge
(VDS = −24 Vdc,
VGS = −10 Vdc,
ID = −3.05 Adc)
Gate−Source Charge
Gate−Drain Charge
ns
ns
nC
BODY−DRAIN DIODE RATINGS (Note 6)
Diode Forward On−Voltage
(IS = −3.05 Adc, VGS = 0 V)
(IS = −3.05 Adc, VGS = 0 V, TJ = 125°C)
Reverse Recovery Time
(IS = −3.05 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
5. Handling precautions to protect against electrostatic discharge is mandatory.
6. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.
7. Switching characteristics are independent of operating junction temperature.
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2
mC
NTMD3P03R2
TYPICAL ELECTRICAL CHARACTERISTICS
−ID, DRAIN CURRENT (AMPS)
VGS = −4 V
VGS = −4.6 V
VGS = −6 V
4
VGS = −4.8 V
TJ = 25°C
VGS = −3.6 V
VGS = −2.8 V
VGS = −3.2 V
VGS = −5 V
3
2
VGS = −2.6 V
1
0
0.25
0.5
0.75
1
1.25
VGS = −3 V
1.5
1.75
TJ = −55°C
1
1
2
3
4
5
Figure 2. Transfer Characteristics
ID = −3.05 A
TJ = 25°C
0.4
0.3
0.2
0.1
5
4
6
7
8
0.7
ID = −1.5 A
TJ = 25°C
0.6
0.5
0.4
0.3
0.2
0.1
0
2
4
3
5
6
7
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Gate−to−Source
Voltage
0.25
TJ = 25°C
0.2
VGS = −4.5 V
0.15
VGS = −10 V
0.1
1
TJ = 25°C
2
Figure 1. On−Region Characteristics
0.5
0.05
TJ = 100°C
3
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.6
3
4
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.7
0
VDS > = −10 V
5
0
2
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = −4.4 V
VGS = −8 V
5
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
6
VGS = −10 V
2
3
4
5
6
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
−ID, DRAIN CURRENT (AMPS)
6
1.6
1.4
ID = −3.05 A
VGS = −10 V
1.2
1
0.8
0.6
−50
−25
0
25
50
75
100
125
−ID, DRAIN CURRENT (AMPS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance vs. Drain Current and
Gate Voltage
Figure 6. On Resistance Variation with
Temperature
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3
150
NTMD3P03R2
VGS = 0 V
VDS = 0 V
1200
C, CAPACITANCE (pF)
IDSS, LEAKAGE (nA)
10000
TJ = 150°C
1000
TJ = 125°C
100
VGS = 0 V
Ciss
1000
800
Ciss
Crss
600
400
Coss
200
10
6
10
14
18
22
26
0
10
30
5
QT
15
6
10
Q2
2
4
6
8
10
12
0
16
14
30
100
td(off)
tf
tr
10
1
1
100
10
RG, GATE RESISTANCE (W)
Figure 9. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
3
VDS = −24 V
ID = −1.5 A
VGS = −4.5 V
tr
tf
1
25
Qg, TOTAL GATE CHARGE (nC)
100
10
20
5
ID = −3.05 A
TJ = 25°C
0
15
td(on)
2
1000
t, TIME (ns)
20
t, TIME (ns)
VDS
VGS
0
10
VDS = −24 V
ID = −3.05 A
VGS = −10 V
25
10
IS, SOURCE CURRENT (AMPS)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
30 1000
4
−VDS
Figure 8. Capacitance Variation
12
Q1
5
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
Figure 7. Drain−to−Source Leakage Current
vs. Voltage
8
0
−VGS
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
Crss
TJ = 25°C
td(off)
td(on)
100
VGS = 0 V
TJ = 25°C
2.5
2
1.5
1
0.5
0
0.2
0.4
0.6
0.8
1
RG, GATE RESISTANCE (W)
−VSD, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
Figure 12. Diode Forward Voltage vs. Current
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4
1.2
NTMD3P03R2
VGS = 12 V
SINGLE PULSE
TC = 25°C
10
1.0 ms
di/dt
10 ms
IS
dc
1.0
trr
ta
0.1
0.01
1
1.0
tb
TIME
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.25 IS
tp
10
IS
100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
Figure 14. Diode Reverse Recovery Waveform
1.0
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESPONSE
−ID, DRAIN CURRENT (AMPS)
100
D = 0.5
0.2
0.1
0.1
Normalized to RqJA at Steady State (1″ pad)
Chip
Junction 2.32 W
18.5 W
50.9 W
37.1 W
56.8 W
0.05
0.02
0.01
1E−03
0.0014 F
0.01
0.0073 F
0.022 F
0.105 F
0.484 F
3.68 F
Ambient
Single Pulse
1E−02
24.4 W
1E−01
1E+00
1E+01
t, TIME (s)
Figure 15. FET Thermal Response
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5
1E+02
1E+03
NTMD3P03R2
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AG
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
MILLIMETERS
DIM MIN
MAX
A
4.80
5.00
B
3.80
4.00
C
1.35
1.75
D
0.33
0.51
G
1.27 BSC
H
0.10
0.25
J
0.19
0.25
K
0.40
1.27
M
0_
8_
N
0.25
0.50
S
5.80
6.20
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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6
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For additional information, please contact your
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NTMD3P03R2/D