TI TPS54340DDA

TPS54340
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SLVSBK0A – OCTOBER 2012 – REVISED FEBRUARY 2013
42 V Input, 3.5 A, Step Down DC-DC Converter with Eco-mode™
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FEATURES
1
•
•
2
•
•
•
•
•
•
•
•
4.5 V to 42 V (45 V Abs Max) Input Range
3.5 A Continuous Current, 4.5 A Minimum Peak
Inductor Current Limit
Current Mode Control DC-DC Converter
92-mΩ High-Side MOSFET
High Efficiency at Light Loads with Pulse
Skipping Eco-mode™
Low Dropout at Light Loads with Integrated
BOOT Recharge FET
146 μA Operating Quiescent Current
1 μA Shutdown Current
100 kHz to 2.5 MHz Fixed Switching Frequency
Synchronizes to External Clock
•
•
•
•
Adjustable UVLO Voltage and Hysteresis
Internal Soft-Start
Accurate Cycle-by-Cycle Current Limit
Thermal, Overvoltage, and Frequency
Foldback Protection
0.8 V 1% Internal Voltage Reference
8-Pin HSOIC with PowerPAD™ Package
–40°C to 150°C TJ Operating Range
Supported by WEBENCH™ Software Tool
•
•
•
•
APPLICATIONS
•
12 V, 24 V and 48 V Industrial, Automotive and
Communications Power Systems
DESCRIPTION
The TPS54340 is a 42 V, 3.5 A, step down regulator with an integrated high side MOSFET. The device survives
load dump pulses up to 45 V per ISO 7637. Current mode control provides simple external compensation and
flexible component selection. A low ripple pulse skip mode reduces the no load supply current to 146 μA.
Shutdown supply current is reduced to 1 μA when the enable pin is pulled low.
Undervoltage lockout is internally set at 4.3 V but can be increased using the enable pin. The output voltage start
up ramp is internally controlled to provide a controlled start up and eliminate overshoot.
A wide switching frequency range allows either efficiency or external component size to be optimized. Frequency
foldback and thermal shutdown protects internal and external components during an overload condition.
The TPS54340 is available in an 8-pin thermally enhanced HSOIC PowerPAD™ package.
SIMPLIFIED SCHEMATIC
EFFICIENCY vs LOAD CURRENT
100
VIN
VIN
90
80
TPS54340
BOOT
VOUT
RT/CLK
SW
R1
Efficiency - %
70
EN
60
VIN = 12V
fsw = 600 kHz
50
40
30
20
COMP
VOUT = 3.3V
VOUT = 5V
10
FB
0
R3
GND
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IO - Output Current - A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Eco-mode, PowerPAD, WEBENCH are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS54340
SLVSBK0A – OCTOBER 2012 – REVISED FEBRUARY 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
(1)
TJ
PACKAGE
PART NUMBER
–40°C to 150°C
8 Pin HSOIC
TPS54340DDA
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com..
DEVICE INFORMATION
PIN CONFIGURATION
HSOIC PACKAGE
(TOP VIEW)
8
SW
7
GND
3
6
COMP
4
5
FB
BOOT
1
VIN
2
EN
RT/CLK
Thermal
Pad
9
PIN FUNCTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
BOOT
1
O
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high side MOSFET, the output is switched off until the capacitor is
refreshed.
VIN
2
I
Input supply voltage with 4.5 V to 42 V operating range.
EN
3
I
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
RT/CLK
4
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is reenabled and the operating mode returns to resistor frequency programming.
FB
5
I
Inverting input of the transconductance (gm) error amplifier.
COMP
6
O
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
GND
7
–
Ground
SW
8
I
The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad
9
–
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
2
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FUNCTIONAL BLOCK DIAGRAM
EN
VIN
Shutdown
OV
Thermal
Shutdown
UVLO
Enable
Comparator
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Current
Sense
PWM
Comparator
FB
BOOT
Logic
Shutdown
6
Slope
Compensation
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft- Start
Maximum
Clamp
Oscillator
with PLL
8/8/ 2012 A 0192789
GND
POWERPAD
RT/ CLK
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
MAX
VIN
–0.3
45
EN
–0.3
8.4
BOOT
Input voltage
53
FB
–0.3
3
COMP
–0.3
3
RT/CLK
–0.3
3.6
–0.6
45
–2
45
BOOT-SW
Output voltage
UNIT
V
8
SW
SW, 10-ns Transient
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)
2
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)
V
kV
500
V
Operating junction temperature
–40 to 150
°C
Storage temperature
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1) (2)
TPS54340
DDA (8 PINS)
θJA
Junction-to-ambient thermal resistance (standard board)
ψJT
Junction-to-top characterization parameter
5.9
ψJB
Junction-to-board characterization parameter
23.4
θJCtop
Junction-to-case(top) thermal resistance
45.8
θJCbot
Junction-to-case(bottom) thermal resistance
3.6
θJB
Junction-to-board thermal resistance
23.4
(1)
(2)
4
UNITS
42.0
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
42
V
4.3
4.48
V
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout threshold
4.5
Rising
4.1
Internal undervoltage lockout threshold
hysteresis
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V
1.3
3.5
Operating: nonswitching supply current
FB = 0.83 V, TA = 25°C
146
175
1.2
1.3
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling
1.1
Enable threshold +50 mV
–4.6
Enable threshold –50 mV
Hysteresis current
Enable to COMP active
–0.58
–1.2
-1.8
–2.2
–3.4
-4.5
VIN = 12 V , TA = 25°C
V
μA
μA
540
µs
INTERNAL SOFT-START TIME
Soft-Start Time
fSW = 500 kHz, 10% to 90%
2.1
ms
Soft-Start Time
fSW = 2.5 MHz, 10% to 90%
0.42
ms
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
0.808
92
190
V
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
Minimum controllable on time
VIN = 12 V, TA = 25°C
135
mΩ
50
nA
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
350
μMhos
77
μMhos
ns
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gM)
Error amplifier transconductance (gM) during
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
soft-start
Error amplifier dc gain
VFB = 0.8 V
Min unity gain bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to SW current transconductance
10,000
V/V
2500
kHz
±30
μA
12
A/V
CURRENT LIMIT
All VIN and temperatures, Open Loop (1)
Current limit threshold
All temperatures, VIN = 12 V, Open Loop
(1)
VIN = 12 V, TA = 25°C, Open Loop (1)
4.5
5.5
6.8
4.5
5.5
6.25
5.2
5.5
5.85
Current limit threshold delay
A
60
ns
176
°C
12
°C
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
fSW
Switching frequency
100
RT = 200 kΩ
Switching frequency range using CLK mode
450
160
Minimum CLK input pulse width
2500
kHz
550
kHz
2300
kHz
15
RT/CLK high threshold
1.55
RT/CLK low threshold
(1)
500
0.5
ns
1.7
V
1.2
V
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with RT resistor in series
55
ns
PLL lock in time
Measured at 500 kHz
78
μs
Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
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TYPICAL CHARACTERISTICS
ON RESISTANCE vs JUNCTION TEMPERATURE
VOLTAGE REFERENCE vs JUNCTION TEMPERATURE
0.25
0.814
VIN = 12 V
VFB − Voltage Reference (V)
RDS(ON) − On-State Resistance (Ω)
BOOT-SW = 3 V
BOOT-SW = 6 V
0.2
0.15
0.1
0.05
0
−50
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
0.809
0.804
0.799
0.794
0.789
0.784
−50
150
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
G001
Figure 1.
SWITCH CURRENT LIMIT vs INPUT VOLTAGE
VIN = 12 V
TJ = −40°C
TJ = 25°C
TJ = 150°C
6.3
High-Side Switch Current (A)
High-Side Switch Current (A)
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
4.5
0
10
5
G003
Figure 3.
RT = 200 kΩ, VIN = 12 V
ƒSW − Switching Frequency (kHz)
ƒSW − Switching Frequency (kHz)
500
530
520
510
500
490
480
470
460
−25
35
40
45
G004
SWITCHING FREQUENCY vs RT/CLK RESISTANCE
HIGH FREQUENCY RANGE
550
540
15
20
25
30
VIN − Input Voltage (V)
Figure 4.
SWITCHING FREQUENCY vs JUNCTION TEMPERATURE
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
ƒSW (kHz) = 92417 × RT (kΩ)−0.991
RT (kΩ) = 101756 × fSW (kHz)−1.008
450
400
350
300
250
200
150
100
50
0
200
G005
Figure 5.
6
G002
6.5
6.5
450
−50
150
Figure 2.
SWITCH CURRENT LIMIT vs JUNCTION TEMPERATURE
4.5
−50
125
300
400
500
600
700
800
RT/CLK − Resistance (kΩ)
900
1000
G006
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY vs RT/CLK RESISTANCE
LOW FREQUENCY RANGE
EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE
2500
500
ƒSW − Switching Frequency (kHz)
VIN = 12 V
450
2000
400
gm (dB)
1500
1000
350
300
500
0
250
0
50
100
150
RT/CLK − Resistance (kΩ)
200
−50
200
−25
G007
Figure 7.
EA TRANSCONDUCTANCE DURING SOFT-START vs
JUNCTION TEMPERATURE
VIN = 12 V
EN − Threshold (V)
gm (uA/V)
90
80
70
60
50
40
30
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
−50
−25
G009
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
G010
Figure 10.
EN PIN CURRENT vs JUNCTION TEMPERATURE
EN PIN CURRENT vs JUNCTION TEMPERATURE
−0.5
−4
VIN = 5 V, I EN = Threshold+50mV
−0.7
−0.9
−4.2
−1.1
−4.3
−1.3
−4.4
−1.5
−1.7
−4.5
−4.6
−1.9
−4.7
−2.1
−4.8
−2.3
−4.9
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
VIN = 12 V, I EN = Threshold+50mV
−4.1
IEN (µA)
IEN (µA)
G008
VIN = 12 V
Figure 9.
−2.5
−50
150
EN PIN VOLTAGE vs JUNCTION TEMPERATURE
100
20
−50
125
Figure 8.
120
110
0
25
50
75
100
TJ − Junction Temperature (°C)
150
−5
−50
G011
Figure 11.
−25
0
25
50
75
100
Tj − Junction Temperature (°C)
125
150
G012
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
EN PIN CURRENT HYSTERESIS vs JUNCTION
TEMPERATURE
SWITCHING FREQUENCY vs FB
100
% of Nominal Switching Frequency
EN PIN Current Hysteresis (µA)
−2.5
−2.7
−2.9
−3.1
−3.3
−3.5
−3.7
−3.9
−4.1
−4.3
VIN = 12 V
−4.5
−50
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
VFB Falling
VFB Rising
75
50
25
0
150
0
0.1
0.2
G112
0.3
0.4
VFB (V)
0.5
0.6
G013
Figure 14.
SHUTDOWN SUPPLY CURRENT vs JUNCTION
TEMPERATURE
SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (VIN)
3
TJ = 25°C
Shutdown Supply Current (µA)
Shutdown Supply Current (µA)
VIN = 12 V
2.5
2
1.5
1
0.5
0
−50
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
2.5
2
1.5
1
0.5
0
150
0
5
10
G014
Figure 15.
15
20
25
30
VIN − Input Voltage (V)
35
VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE
45
G016
VIN SUPPLY CURRENT vs INPUT VOLTAGE
210
VIN = 12 V
TJ = 25°C
190
VIN − Supply Current (µA)
190
170
150
130
110
90
70
−50
40
Figure 16.
210
VIN − Supply Current (dB)
0.8
Figure 13.
3
170
150
130
110
90
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
70
0
G016
Figure 17.
8
0.7
5
10
15
20
25
30
VIN − Input Voltage (V)
35
40
45
G018
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
BOOT-SW UVLO vs JUNCTION TEMPERATURE
INPUT VOLTAGE UVLO vs JUNCTION TEMPERATURE
2.6
4.4
2.4
4.3
Input Voltage (V)
VIN − (BOOT−SW) (dB)
2.5
4.5
BOOT-SW UVLO Falling
BOOT-SW UVLO Rising
2.3
2.2
2.1
4.2
4.1
4
2
3.9
1.9
3.8
1.8
−50
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
3.7
−50
150
G018
UVLO Start Switching
UVLO Stop Switching
−25
0
25
50
75
100
Tj − Junction Temperature (°C)
Figure 19.
125
150
G019
Figure 20.
SOFT-START TIME vs SWITCHING FREQUENCY
10
VIN = 12V,
o
TJ = 25 C
9
Soft-Start Time (ms)
8
7
6
5
4
3
2
1
0
100 300 500 700 900 11001300 1500 17001900 2100 2300 2500
Switching Frequency (KHz)
G021
Figure 21.
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OVERVIEW
The TPS54340 is a 42 V, 3.5 A, step-down (buck) regulator with an integrated high side n-channel MOSFET.
The device implements constant frequency, current mode control which reduces output capacitance and
simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows
either efficiency or size optimization when selecting the output filter components. The switching frequency is
adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop
(PLL) connected to the RT/CLK pin that will synchronize the power switch turn on to a falling edge of an external
clock signal.
The TPS54340 has a default input start-up voltage of approximately 4.3 V. The EN pin can be used to adjust the
input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up current
source enables operation when the EN pin is floating. The operating current is 146 μA under no load condition
(not switching). When the device is disabled, the supply current is 1 μA.
The integrated 92mΩ high side MOSFET supports high efficiency power supply designs capable of delivering 3.5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54340 reduces the external
component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a
UVLO circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a preset
threshold. An automatic BOOT capacitor recharge circuit allows the TPS54340 to operate at high duty cycles
approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the
application. The minimum output voltage is the internal 0.8 V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Transient Protection (OVP) comparator. When
the OVP comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is
less than 106% of the desired output voltage.
The TPS54340 includes an internal soft-start circuit that slows the output rise time during start-up to reduce inrush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54340 uses fixed frequency, peak current mode control with adjustable switching frequency. The output
voltage is compared through external resistors connected to the FB pin to an internal voltage reference by an
error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
at the COMP pin controls the high side power switch current. When the high side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will
increase and decrease as the output current increases and decreases. The device implements current limiting by
clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a
minimum voltage clamp on the COMP pin.
Slope Compensation Output Current
The TPS54340 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
Pulse Skip Eco-mode
The TPS54340 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing
switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end
of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse
skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.
10
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DETAILED DESCRIPTION (continued)
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high side MOSFET is inhibited. Since
the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling
output voltage by increasing the COMP pin voltage. The high side MOSFET is enabled and switching resumes
when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the
regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54340 senses and controls peak switch current, not the average load
current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. The circuit in Figure 33 enters Eco-mode at about TBD mA output current. As the load current approaches
zero, the device enters a pulse skip mode during which it draws only 146 μA input quiescent current.
Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54340 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW
pins provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high
side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT capacitor is
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54340 will
operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1V. When the voltage from
BOOT to SW drops below 2.1V, the high side MOSFET is turned off and an integrated low side MOSFET pulls
SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high output
voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.
Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.
The start and stop voltage for a typical 5 V output application is shown in Figure 22 where the Vin voltage is
plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is
being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle
PWM control.
spacer
5.6
5.5
VI - Input Voltage - V
5.4
5.3
5.2
5.1
Dropout
Voltage
5
4.9
Dropout
Voltage
4.8
4.7
Start
4.6
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Stop
0.4
0.45
0.5
Load Current - A
Figure 22. 5V Start/Stop Voltage
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DETAILED DESCRIPTION (continued)
Error Amplifier
The TPS54340 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8 V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start
operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal softstart voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. It is recommended to use 1% tolerance or better divider resistors.
Select the low side resistor RLS for the desired divider current and use Equation 1 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator
will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(1)
Enable and Adjusting Undervoltage Lockout
The TPS54340 is enabled when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54340 is disabled when the VIN pin voltage falls below 4 V or when the EN
pin voltage is below 1.2 V. The EN pin has an internal pull-up current source, I1, of 1.2 μA that enables operation
of the TPS54340 when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 23 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4
μA Ihys current is removed. This addional current facilitates adjustable input voltage UVLO hysteresis. Use
Equation 2 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 3 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (e.g., 4.5 V) and withstand high input voltages
(e.g., 40 V), the EN pin may experience a voltage greater than the absolute maximum voltage of 8.4 V during the
high input voltage condition. It is recommended to use a zener diode to clamp the pin voltage below the absolute
maximum rating.
VIN
TPS54340
i1
ihys
RUVLO1
EN
Optional
VEN
RUVLO2
Figure 23. Adjustable Undervoltage Lockout (UVLO)
- VSTOP
V
RUVLO1 = START
IHYS
12
(2)
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DETAILED DESCRIPTION (continued)
VENA
RUVLO2 =
VSTART - VENA
+ I1
RUVLO1
(3)
Internal Soft-Start
The TPS54340 has an internal digital soft-start that ramps the reference voltage from zero volts to its final value
in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 4
1024
tSS (ms) =
fSW (kHz)
(4)
If the EN pin is pulled below the stop threshold of 1.2 V, switching stops and the internal soft-start resets. The
soft-start also resets in thermal shutdown.
Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54340 is adjustable over a wide range from 100 kHz to 2500 kHz by placing
a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 5 or Equation 6 or the curves in Figure 5 and Figure 6. To reduce the solution size one
would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency,
maximum input voltage and minimum controllable on time should be considered. The minimum controllable on
time is typically 135 ns which limits the maximum operating frequency in applications with high input to output
step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more
detailed discussion of the maximum switching frequency is provided in the next section.
92417
RT (kW) =
f sw (kHz)0.991
(5)
f sw (kHz) =
101756
RT (kW)1.008
(6)
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DETAILED DESCRIPTION (continued)
Selecting the Switching Frequency
The TPS54340 implements peak current mode control in which the COMP pin voltage controls the peak current
of the high side MOSFET. A signal proportional to the high side switch current and the COMP pin voltage are
compared each cycle. When the peak switch current intersects the COMP control voltage, the high side switch is
turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch
current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the
peak switch current limit. The TPS54340 provides an accurate current limit threshold with a typical current limit
delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current. The
relationship between the inductor value and the peak inductor current is shown in Figure 24.
Inductor Current (A)
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = VIN/L x tCLdelay
tCLdelay
tON
Figure 24. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54340
implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls
from 0.8 V to 0 V. The TPS54340 uses a digital frequency foldback to enable synchronization to an external
clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the
peak current limit because of the high input voltage and the minimum controllable on time. When the output
voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The
frequency foldback effectively increases the off time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 8 calculates the maximum switching frequency at which
the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating frequency
should not exceed the calculated value.
Equation 7 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
14
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DETAILED DESCRIPTION (continued)
fSW (max skip ) =
fSW(shift) =
æ I ´R + V
dc
OUT + Vd
´ç O
ç VIN - IO ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(7)
æ ICL ´ Rdc + VOUT(sc ) + Vd
´ç
ç VIN - ICL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(8)
1
tON
fDIV
tON
IO
Output current
ICL
Current limit
Rdc
inductor resistance
VIN
maximum input voltage
VOUT
output voltage
VOUTSC
output voltage during short
Vd
diode voltage drop
RDS(on)
switch on resistance
tON
controllable on time
ƒDIV
frequency divide equals (1, 2, 4, or 8)
Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 25. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 1.7 V and
have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising
edge of the SW will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit
should be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground
when the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is
connected in parallel with an ac coupling capacitor to a termination resistor (e.g., 50 Ω) as shown in Figure 25.
The two resistors in series provide the default frequency setting resistance when the signal source is turned off.
The sum of the resistance should set the switching frequency close to the external CLK frequency. It is
recommended to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin.
The first time the RT/CLK is pulled above the PLL threshold the TPS54340 switches from the RT resistor freerunning frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency
can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor
mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During the transition
from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz and then
increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to the
RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 volts. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 26, Figure 27 and Figure 28 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER
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DETAILED DESCRIPTION (continued)
TPS54340
TPS54340
RT/CLK
RT/CLK
PLL
PLL
RT
Clock
Source
Hi-Z
Clock
Source
RT
Figure 25. Synchronizing to a System Clock
16
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DETAILED DESCRIPTION (continued)
SW
SW
EXT
EXT
IL
IL
Figure 26. Plot of Synchronizing in CCM
Figure 27. Plot of Synchronizing in DCM
SW
EXT
IL
Figure 28. Plot of Synchronizing in Eco-Mode
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DETAILED DESCRIPTION (continued)
Overvoltage Protection
The TPS54340 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable
time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak current limit
threshold. When the overload condition is removed, the regulator output rises and the error amplifier output
transitions to the normal operating level. In some applications, the power supply output voltage can increase
faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin
voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the
internal voltage reference, the high side MOSFET resumes normal operation.
Thermal Shutdown
The TPS54340 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence controlled
by the internal soft-start circuitry.
Small Signal Model for Loop Response
Figure 29 shows an equivalent model for the TPS54340 control loop which can be simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of
3350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Ro
and capacitor Co model the open loop gain and frequency response of the amplifier. The 1mV ac voltage source
between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.
SW
VO
Power Stage
gmps 12 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
CO
R3
C2
RO
FB
COUT
gmea
350 mA/V
R2
C1
Figure 29. Small Signal Model for Loop Response
18
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DETAILED DESCRIPTION (continued)
Simple Small Signal Model for Peak Current Mode Control
Figure 30 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54340 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown in
Equation 9 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP pin voltage (node c in Figure 29) is the power stage transconductance,
gmPS. The gmPS for the TPS54340 is 12 A/V. The low-frequency gain of the power stage is the product of the
transconductance and the load resistance as shown in Equation 10.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 11). The combined effect is highlighted by the dashed line in the right half of
Figure 30. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 12).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 30. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
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DETAILED DESCRIPTION (continued)
æ
s ö
ç1 +
÷
2p ´ fZ ø
VOUT
= Adc ´ è
VC
æ
s ö
ç1 +
÷
2
p
´ fP ø
è
Adc = gmps ´ RL
(10)
1
fP =
COUT ´ RL ´ 2p
(11)
1
fZ =
COUT ´ RESR ´ 2p
(12)
(9)
Small Signal Model for Frequency Compensation
The TPS54340 uses a transconductance amplifier for the error amplifier and supports three of the commonlyused frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in
Figure 31. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR
output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 13 and Equation 14 relate the frequency response of the amplifier to the small
signal model in Figure 31. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 31. See the application section for a design example using a Type 2A network with a low ESR output
capacitor.
Equation 13 through Equation 22 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
VO
R1
FB
gmea
COMP
Type 2A
Type 2B
Type 1
Vref
R2
RO
CO
R3
C2
C1
R3
C2
C1
Figure 31. Types of Frequency Compensation
20
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DETAILED DESCRIPTION (continued)
Aol
A0
P1
Z1
P2
A1
BW
Figure 32. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
Ro =
CO
(13)
(14)
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2
2
p
´
p
´
f
f
P1 ø è
P2 ø
è
A0 = gmea
A1 = gmea
P1 =
Z1 =
P2 =
P2 =
P2 =
(15)
R2
´ Ro ´
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
(16)
(17)
1
2p ´ Ro ´ C1
(18)
1
2p ´ R3 ´ C1
(19)
1
2p ´ R3 | | RO ´ (C2 + CO )
type 2a
(20)
1
type 2b
2p ´ R3 | | RO ´ CO
2p ´ R O
(21)
1
type 1
´ (C2 + C O )
(22)
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APPLICATION INFORMATION
Design Guide — Step-By-Step Design Procedure
This guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. For this example, we will start with the following known parameters:
Output Voltage
3.3 V
Transient Response 0.875 A to 2.625 A load step
ΔVOUT = 4 %
Maximum Output Current
3.5 A
Input Voltage
12 V nom. 6 V to 42 V
Output Voltage Ripple
0.5% of VOUT
Start Input Voltage (rising VIN)
5.75 V
Stop Input Voltage (falling VIN)
4.5 V
Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible since this produces the smallest solution size. High switching frequency allows for
lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
Equation 7 and Equation 8 should be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54340. For this example, the output voltage is 3.3 V
and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to avoid
pulse skipping from Equation 7. To ensure overcurrent runaway is not a concern during short circuits use
Equation 8 to determine the maximum switching frequency for frequency foldback protection. With a maximum
input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 mΩ, switch resistance of 92
mΩ, a current limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is
1260 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 5 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 33. For 600 kHz operation, the closest
standard value resistor is 162 kΩ.
1
æ 3.5 A x 21 mW + 3.3 V + 0.7 V ö
fSW(max skip) =
´ ç
÷ = 712 kHz
135ns
è 42 V - 3.5 A x 92 mW + 0.7 V ø
(23)
8
æ 4.7 A x 21 mW + 0.1 V + 0.7 V ö
´ ç
÷ = 1260 kHz
135 ns
è 42 V - 4.7 A x 92 mW + 0.7 V ø
92417
RT (kW) =
= 163 kW
600 (kHz)0.991
fSW(shift) =
22
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(24)
(25)
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L1
5.6uH
3.3V, 3.5A VOUT
C4 0.1uF
U1
TPS54340DDA
VIN
6V to 42V
2
3
C1
C2
2.2uF
2.2uF
R1
365k
4
BOOT
SW
VIN
GND
EN
COMP
RT/CLK
PWRPD
1
9
GND
R2
86.6k
R3
162k
FB
C6
D1
8
100uF
B560C
R5
31.6k
7
6
5
GND
FB
R4
11.5k
C8
R6
10.2k
47pF
GND
FB
C5
5600pF
GND
GND
Figure 33. 3.3 V Output TPS54340 Design Example.
Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 26.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to
or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,
however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 4.8 μH. The nearest
standard value is 5.6 μH. It is important that the RMS current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found from Equation 28 and Equation 29. For this design,
the RMS inductor current is 3.5 A and the peak inductor current is 3.95 A. The chosen inductor is a WE
7443552560, which has a saturation current rating of 7.5 A and an RMS current rating of 6.7 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54340 which is nominally 5.5 A.
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LO(min ) =
VIN(max ) - VOUT
IOUT ´ KIND
´
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VOUT
42 V - 3.3 V
3.3 V
=
´
= 4.8 mH
VIN(max ) ´ fSW
3.5 A x 0.3
42 V ´ 600 kHz
(26)
spacer
IRIPPLE =
VOUT ´ (VIN(max ) - VOUT )
VIN(max ) ´ LO ´ fSW
=
3.3 V x (42 V - 3.3 V)
= 0.905 A
42 V x 5.6 mH x 600 kHz
(27)
spacer
IL(rms ) =
(IOUT )
2
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
+
´
12 çç
VIN(max ) ´ LO ´ fSW
è
)÷ö
2
÷ =
÷
ø
2
(3.5 A )
2
æ 3.3 V ´ (42 V - 3.3 V ) ö
1
+
´ ç
÷ = 3.5 A
ç 42 V ´ 5.6 mH ´ 600 kHz ÷
12
è
ø
(28)
spacer
IL(peak ) = IOUT +
IRIPPLE
0.905 A
= 3.5 A +
= 3.95 A
2
2
(29)
Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 30 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 0.875 A to 2.625 A.
Therefore, ΔIOUT is 2.625 A - 0.875 A = 1.75 A and ΔVOUT = 0.04 × 3.3 = 0.13 V. Using these numbers gives a
minimum capacitance of 44.9 μF. This value does not take the ESR of the output capacitor into account in the
output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum
electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure 34. The excess energy absorbed in the output capacitor will increase the voltage on the
capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.
Equation 31 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, Vf is the peak output voltage, and VI is the initial voltage. For this example, the worst case load step
will be from 2.625 A to 0.875 A. The output voltage increases during this load transition and the stated maximum
in our specification is 4 % of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. Vi is the initial capacitor
voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 31 yields a minimum
capacitance of 38.6 μF.
Equation 32 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 32 yields 11.4 μF.
Equation 33 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 33 indicates the ESR should be less than 18 mΩ.
The most stringent criteria for the output capacitor is 44.9 μF required to maintain the output voltage within
regulation tolerance during a load transient.
24
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Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 100
μF ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 70 µF, well above the minimum
required capacitance of 44.9 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 34 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 34 yields 261 mA.
2 ´ DIOUT
2 ´ 1.75 A
=
= 44.9 mF
COUT >
fSW ´ DVOUT 600 kHz x 0.13 V
(30)
((I ) - (I ) ) = 5.6 mH x (2.625 A - 0.875 A ) = 38.6 mF
x
(3.432 V - 3.3 V )
((V ) - (V ) )
2
2
OH
COUT > LO
2
2
OL
2
2
f
2
2
I
1
1
1
1
´
=
= 11.4 mF
COUT >
x
8 ´ fSW æ VORIPPLE ö 8 x 600 kHz
æ 16.5 mV ö
ç 0.905 A ÷
ç
÷
è
ø
è IRIPPLE ø
V
16.5 mV
= 18 mW
RESR < ORIPPLE =
IRIPPLE
0.905 A
ICOUT(rms) =
(
VOUT ´ VIN(max ) - VOUT
)=
12 ´ VIN(max ) ´ LO ´ fSW
3.3 V ´
(42 V
(31)
(32)
(33)
- 3.3 V )
12 ´ 42 V ´ 5.6 mH ´ 600 kHz
= 261 mA
(34)
Catch Diode
The TPS54340 requires an external catch diode between the SW pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than
the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low
forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
42 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54340.
For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.70 volts
at 5 A.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 35 is
used to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 35, the total loss in the diode is
2.42 Watts.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD
(V
=
IN(max ) - VOUT
(42 V
)´ I
OUT
2
´ Vf d
VIN(max )
- 3.3 V ) ´ 3.5 A x 0.7 V
42 V
+
C j ´ fSW ´ (VIN + Vf d)
2
+
=
300 pF x 600 kHz x (42 V + 0.7 V)2
= 2.42 W
2
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Input Capacitor
The TPS54340 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of
effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance
includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
input current ripple of the TPS54340. The input ripple current can be calculated using Equation 36.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V. For this example, two 2.2 μF, 100 V capacitors in parallel are used. Table 2 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 37. Using the design example values, IOUT = 3.5 A, CIN = 4.4 μF, ƒsw = 600 kHz,
yields an input voltage ripple of 331 mV and a rms input ripple current of 1.74 A.
ICI(rms ) = IOUT x
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 3.5 A
3.3 V
´
6V
(6 V
- 3.3 V )
6V
= 1.74 A
(36)
´ 0.25
I
3.5 A ´ 0.25
DVIN = OUT
=
= 331 mV
CIN ´ fSW
4.4 mF ´ 600 kHz
(37)
Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 to 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIALECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
50 V
100 V
50 V
X7R
C series C4532
C series C3225
50 V
100 V
50 V
X7R dielectric series
100 V
Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or higher
voltage rating.
26
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Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54340. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between Vin and
ground connected to the EN pin. Equation 2 and Equation 3 calculate the resistance values necessary. For the
example application, a 365 kΩ between Vin and EN (RUVLO1) and a 86.6 kΩ between EN and ground (RUVLO2)
are required to produce the 8 V and 6.25 V start and stop voltages.
V
- VSTOP
5.75 V - 4.5 V
=
= 368 kW
RUVLO1 = START
IHYS
3.4 mA
(38)
RUVLO2 =
VENA
1.2 V
=
= 87.8 kW
VSTART - VENA
5.75 V - 1.2 V
+ 1.2 mA
+ I1
365 kW
RUVLO1
(39)
Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 1, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain
the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
V
- 0.8 V
æ 3.3 V - 0.8 V ö
= 10.2 kW x ç
RHS = RLS x OUT
÷ = 31.9 kW
0.8 V
0.8 V
è
ø
(40)
Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 41 and
Equation 42. For COUT, use a derated value of 70 μF. Use equations Equation 43 and Equation 44 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 2411 Hz and ƒz(mod) is 455 kHz.
Equation 42 is the geometric mean of the modulator pole and the ESR zero and Equation 44 is the mean of
modulator pole and the switching frequency. Equation 43 yields 33.1 kHz and Equation 44 gives 26.9 kHz. Use
the lower value of Equation 43 or Equation 44 for an initial crossover frequency. For this example, the target ƒco
is 26.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT(max )
3.5 A
fP(mod) =
=
= 2411 Hz
2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 70 mF
(41)
f Z(mod) =
1
2 ´ p ´ RESR ´ COUT
fco =
fp(mod) x f z(mod) =
fco =
fp(mod) x
fSW
2
=
=
1
= 455 kHz
2 ´ p ´ 5 mW ´ 70 mF
2411 Hz x 455 kHz
2411 Hz x
600 kHz
2
(42)
= 33.1 kHz
(43)
= 26.9 kHz
(44)
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To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 11.6 kΩ and a standard value of 11.5 kΩ is selected.
Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 5740 pF for
compensating capacitor C5. 5600 pF is used for this design.
ö
VOUT
æ 2 ´ p ´ fco ´ COUT ö æ
ö
3.3 V
æ 2 ´ p ´ 26.9 kHz ´ 70 mF ö æ
R4 = ç
xç
÷ = ç
÷ x ç
÷ = 11.6 kW
÷
gmps
12 A / V
è
ø è 0.8 V x 350 mA / V ø
è
ø è VREF x gmea ø
(45)
C5 =
1
1
=
= 5740 pF
2 ´ p ´ R4 x fp(mod)
2 ´ p ´ 11.5 kW x 2411 Hz
(46)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 47 and Equation 48 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x RESR
70 mF x 5 mW
=
= 30.4 pF
C8 = OUT
R4
11.5 kW
(47)
1
1
=
= 46.1 pF
C8 =
R4 x f sw x p
11.5 kW x 600 kHz x p
(48)
Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 342 mA. The power supply enters Eco-mode when the output current is lower than 31.4 mA. The
input current draw is 237 μA with no load.
28
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10 V/div
1 A/div
APPLICATION CURVES
C4: IOUT
VIN
C3
C3: VOUT ac coupled
20 mV/div
100 mV/div
C4
VOUT
Time = 4 ms/div
Time = 100 ms/div
Figure 35. Line Transient (8 V to 40 V)
5 V/div
Figure 34. Load Transient
5 V/div
-3.3 V offset
C1: VIN
C1: VIN
C3: EN
C3
2 V/div
C1
C2: VOUT
2 V/div
2 V/div
2 V/div
C1
C2
C3: EN
C3
C2: VOUT
C2
Time = 2 ms/div
Time = 2 ms/div
Figure 36. Start-up With VIN
Figure 37. Start-up With EN
10 V/div
C4: IL
C2: VOUT ac coupled
10 mV/div
20 mV/div
IOUT = 3.5 A
500 mA/div
C1
1 A/div
10 V/div
C1: SW
C2
C4
C1: SW
C1
C4: IL
C4
IOUT = 100 mA
C2
C2: VOUT ac coupled
Time = 2 ms/div
Time = 2 ms/div
Figure 38. Output Ripple CCM
Figure 39. Output Ripple DCM
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10 V/div
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C1: SW
C1
C1: SW
C1
1 A/div
C4: IL
C4: IL
C4
IOUT = 3.5 A
C2: VOUT ac coupled
C3: VIN ac coupled
C2
No Load
200 mV/div
20 mV/div
200 mA/div
10 V/div
SLVSBK0A – OCTOBER 2012 – REVISED FEBRUARY 2013
C2
C4
Time = 2 ms/div
Time = 2 ms/div
Figure 41. Input Ripple CCM
C1: SW
C1
C4: IL
C4
IOUT = 100 mA
C3: VIN ac coupled
200 mA/div
2 V/div
C1: SW
20 mV/div
50 mV/div
500 mA/div
10 V/div
Figure 40. Output Ripple PSM
C3
C4
C4: IL
C3
C3: VOUT ac coupled
VIN = 5.5 V
VOUT = 5 V
Time = 2 ms/div
Time = 20 ms/div
Figure 42. Input Ripple DCM
Figure 43. Low Dropout Operation
IOUT = 1 A
EN Floating
2 V/div
2 V/div
IOUT = 100 mA
EN Floating
VIN
VOUT
VIN
VOUT
Time = 40 ms/div
Time = 40 ms/div
Figure 44. Low Dropout Operation
30
No Load
EN Floating
Figure 45. Low Dropout Operation
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90
90
80
80
70
70
Efficiency - %
100
Efficiency - %
100
60
50
40
VOUT = 3.3V, fsw = 600 kHz
30
20
VOUT = 3.3V, fsw = 600 kHz
60
50
40
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0
0.5
1.0
1.5
2.5
2.0
3.0
6Vin
12Vin
24Vin
10
0
0.001
3.5
Figure 47. Light Load Efficiency
90
80
80
70
70
Efficiency - %
100
90
Efficiency - %
100
60
50
40
VOUT = 5V, fsw = 600 kHz
20
60
50
40
VOUT = 5V, fsw = 600 kHz
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
6Vin
12Vin
24Vin
10
0
0
0.001
4.0
Figure 49. Light Load Efficiency
1
180
60
Gain - dB
20
Gain
0
0
-60
-20
VIN = 12V,
VOUT = 3.3V,
IOUT = 3.5A
10
100
-120
-180
1000
10000
100000
1000000
Phase - degree
120
Output Voltage Deviation - %
Phase
-60
VIN = 12V, VOUT = 3.3V,
fsw = 600 kHz
0.8
40
1
IO - Output Current - A
Figure 48. Efficiency vs Load Current
60
36Vin
42Vin
0.1
0.01
IO - Output Current - A
-40
1
IO - Output Current - A
Figure 46. Efficiency vs Load Current
30
0.1
0.01
IO - Output Current - A
36Vin
42Vin
0.6
0.4
0.2
0
-0.2
0.4
-0.6
-0.8
-1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IO - Output Current - A
Frequency - Hz
Figure 50. Overall Loop Frequency Response
Figure 51. Regulation vs Load Current
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Output Voltage Deviation - %
0.3
VOUT = 3.3V, IOUT = 3.5A
fsw = 600 kHz
0.2
0.1
0
-0.1
0.2
-0.3
5
10
15
20
25
30
35
40
45
VIN - Input Voltage - V
Figure 52. Regulation vs Input Voltage
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Power Dissipation Estimate
The following formulas show how to estimate the TPS54340 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.
æV
ö
3.3 V
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 3.5 A 2 ´ 92 mW ´
= 0.31 W
12 V
è VIN ø
(49)
spacer
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 600 kHz ´ 3.5 A ´ 4.9 ns = 0.123 W
(50)
spacer
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 600 kHz = 0.022 W
(51)
spacer
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W
(52)
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.31 W + 0.123 W + 0.022 W + 0.0018 W = 0.457 W
(53)
For given TA,
TJ = TA + RTH ´ PTOT
(54)
For given TJMAX = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
(55)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
RTH is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
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Layout
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR
ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by
the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 53 for a PCB layout
example. The GND pin should be tied directly to the power pad under the IC and the power pad.
The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The
SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW connection
is the switching node, the catch diode and output inductor should be located close to the SW pins, and the area
of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top
side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT
resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional
external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
Vout
Output
Capacitor
Topside
Ground
Area
Input
Bypass
Capacitor
Vin
UVLO
Adjust
Resistors
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
BOOT
Catch
Diode
SW
VIN
GND
EN
COMP
RT/CLK
FB
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 53. PCB Layout Example
Estimated Circuit Area
Boxing in the components in the design of Figure 33 the estimated printed circuit board area is 1.025 in2 (661
mm2). This area does not include test points or connectors.
34
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Product Folder Links: TPS54340
TPS54340
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SLVSBK0A – OCTOBER 2012 – REVISED FEBRUARY 2013
VIN
+
Cin
Cboot
Lo
Cd
GND
SW
BOOT
VIN
R1
+
GND
TPS54340
Co
R2
FB
VOUT
EN
COMP
Rcomp
RT/CLK
Czero
RT
Cpole
Figure 54. TPS54340 Inverting Power Supply from SLVA317 Application Note
VOPOS
+
VIN
Copos
+
Cin
VIN
Cboot
BOOT
GND
SW
Lo
Cd
R1
GND
+
Coneg
R2
TPS54340
VONEG
FB
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
Figure 55. TPS54340 Split Rail Power Supply Based on SLVA369 Application Note
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Product Folder Links: TPS54340
35
TPS54340
SLVSBK0A – OCTOBER 2012 – REVISED FEBRUARY 2013
www.ti.com
REVISION HISTORY
Changes from Original (October 2012) to Revision A
Page
•
Changed Figure 11 From: IEN (µV) To: IEN (µA) .................................................................................................................... 7
•
Changed Figure 12 From: IEN (µV) To: IEN (µA) .................................................................................................................... 7
36
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Product Folder Links: TPS54340
PACKAGE OPTION ADDENDUM
www.ti.com
1-Feb-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPS54340DDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 150
54340
TPS54340DDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 150
54340
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS54340DDAR
Package Package Pins
Type Drawing
SO
Power
PAD
DDA
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54340DDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
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