ETC NJU6820

NJU6820
Preliminary
40-common x 128RGB-Segment, in 4096-Color
4096-Color STN LCD DRIVER
■ GENERAL DESCRIPTION
The NJU6820 is a STN LCD driver with 40common x 128RGB-segment in 4096-color. It
consists of 384(128xRGB)-segment segment, 40common drivers, serial and parallel MPU interface
circuits, internal power supply circuits, gradation
palettes and 61,440-bit for graphic display data RAM.
Each segment driver outputs 16-gradation level out
of 32-gradation level of gradation palette.
Since the NJU6820 provides a low operating
voltage of 1.7V and low operating current, it is ideally
suited for battery-powered handheld applications.
■ PACKAGE OUTLINE
NJU6820CJ
■ FEATURES
●
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4096-color STN LCD driver
LCD drivers
40 commons, 128 RGB-segments,
Display data RAM (DDRAM)
61,440-bit for graphic display
Color display mode
16 gradation level out of 32 gradation level of gradation palette
Black & white display mode
40 x 384 pixels in 16 gradation level or 40 x 384 pixels in B&W display
256-color driving mode
8/16bit Parallel interface directly-connective to 68/80 series MPU
Programmable 8- or 16-bit data bus length for display data
3-/4-line Serial interface
Programmable duty and bias ratios
Programmable internal voltage booster (maximum 5-times)
Programmable contrast control using 128-step EVR
Various instructions
Display data read/write, Display ON/OFF, Reverse display ON/OFF, All pixels ON/OFF,
Column address, row address, N-line inversion, Initial display line, Initial COM line,
Read-modify-write, Gradation mode control, Increment control, Data bus length,
Discharge ON/OFF, Duty cycle ratio, LCD bias ratio, Boost level, EVR control,
Power save ON/OFF, etc
Internal voltage regulator
Low operating current
Low logic supply voltage
1.7V to 3.3V
LCD driving supply voltage
5.0V to 18.0V
C-MOS technology
Rectangle out look for COG
Package
Bumped chip
02/11/22
-1-
NJU6820
DMY100
DMY102
■ PAD LOCATION
1
DMY1
DMY48
DMY49
D14
DMY50
DMY51
D15
DMY52
DMY53
VDD
VDD
DMY54
DMY55
CL
DMY56
DMY57
FLM
DMY58
DMY59
FR
DMY60
DMY61
CLK
DMY62
DMY63
OSC1
DMY64
OSC2
DMY65
VSS
VSS
DMY66
VLCD
VLCD
DMY67
V1
V1
V2
V2
DMY68
V3
V3
V4
V4
DMY69
VREG
VREG
DMY70
VREF
VREF
DMY71
VBA
VBA
DMY72
VSS
VSS
VOUT
VOUT
DMY73
VEE
DMY99
DMY2
VSSA
DMY3
SEL68
DMY4
VDDA
DMY5
PS
DMY6
VSSA
DMY7
RESb
DMY8
DMY9
DMY10
CSb
DMY11
DMY12
DMY13
RS
DMY14
DMY15
DMY16
WRb
DMY17
DMY18
DMY19
RDb
DMY20
VDDA
DMY21
D0
DMY22
DMY23
D1
DMY24
DMY25
D2
DMY26
DMY27
D3
DMY28
DMY29
D4
DMY30
DMY31
D5
DMY32
DMY33
D6
DMY34
DMY35
D7
DMY36
VSSA
DMY37
D8
DMY38
DMY39
D9
DMY40
DMY41
D10
DMY42
DMY43
D11
DMY44
DMY45
D12
DMY46
DMY47
D13
DMY97
COM39
COM38
COM37
COM36
25µm
50µm
25µm
50µm
COM24
COM23
COM21
COM20
DMY96
DMY94
SEGC127
SEGB127
SEGA127
Alignment mark 2
Alignment mark coordinates
(9062µm, -990µm)
50µm
Y
Alignment mark 3
Alignment mark coordinates
(-9062µm, -990µm)
X
20µm
VEE
DMY74
C1+
C1+
DMY75
C1-
50µm
SEGC0
SEGB0
SEGA0
DMY93
C1DMY76
C2+
DMY91
COM0
COM1
COM2
COM3
C2+
DMY77
C2C2DMY78
C3+
C3+
DMY79
C3C3DMY80
C4+
C4+
DMY81
C4-
COM16
COM17
COM18
COM19
DMY90
C4DMY82
DMY83
DMY84
DMY88
DMY87
DMY85
-2-
Alignment mark 1
Alignment mark coordinates
(-9248µm, 1013µm)
( 9248µm, -1013µm)
Chip Center
Chip Size
Chip Thickness
Bump Pitch
Bump Size
Bump hight
Bump Material
:X=0um, Y=0um
:X=18.86mm, Y= 2.39mm
:625um + 25um
:42um(Min)
:24um x 140um
:17.5um(Typ)
:Au
NJU6820
■ PAD COORDINATES 1
Chip Size 18860µm x 2390µm (Chip Center 0µm x 0µm )
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Terminal
DMY0
DMY1
DMY2
VSSA
VSSA
DMY3
SEL68
SEL68
DMY4
VDDA
VDDA
DMY5
PS
PS
DMY6
VSSA
VSSA
DMY7
RESb
RESb
DMY8
DMY9
DMY10
CSb
CSb
DMY11
DMY12
DMY13
RS
RS
DMY14
DMY15
DMY16
WRb
WRb
DMY17
DMY18
DMY19
RDb
RDb
DMY20
VDDA
VDDA
DMY21
D0
D0
DMY22
DMY23
D1
D1
X(µm)
Y(µm)
-8967
-8925
-8883
-8841
-8799
-8757
-8715
-8673
-8631
-8589
-8547
-8505
-8463
-8421
-8379
-8337
-8295
-8253
-8211
-8169
-8127
-8085
-8043
-8001
-7959
-7917
-7875
-7833
-7791
-7749
-7707
-7665
-7623
-7581
-7539
-7497
-7455
-7413
-7371
-7329
-7287
-7245
-7203
-7077
-7035
-6993
-6951
-6825
-6783
-6741
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Terminal
DMY24
DMY25
D2
D2
DMY26
DMY27
D3
D3
DMY28
DMY29
D4
D4
DMY30
DMY31
D5
D5
DMY32
DMY33
D6
D6
DMY34
DMY35
D7
D7
DMY36
VSSA
VSSA
DMY37
D8
D8
DMY38
DMY39
D9
D9
DMY40
DMY41
D10
D10
DMY42
DMY43
D11
D11
DMY44
DMY45
D12
D12
DMY46
DMY47
D13
D13
X(µm)
-6699
-6573
-6531
-6489
-6447
-6321
-6279
-6237
-6195
-6069
-6027
-5985
-5943
-5817
-5775
-5733
-5691
-5565
-5523
-5481
-5439
-5313
-5271
-5229
-5187
-5061
-5019
-4893
-4851
-4809
-4767
-4641
-4599
-4557
-4515
-4389
-4347
-4305
-4263
-4137
-4095
-4053
-4011
-3885
-3843
-3801
-3759
-3633
-3591
-3549
Y(µm)
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Terminal
DMY48
DMY49
D14
D14
DMY50
DMY51
D15
D15
DMY52
DMY53
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DMY54
DMY55
CL
CL
DMY56
DMY57
FLM
FLM
DMY58
DMY59
FR
FR
DMY60
DMY61
CLK
CLK
DMY62
DMY63
OSC1
OSC1
DMY64
OSC2
OSC2
DMY65
VSS
VSS
VSS
VSS
VSS
X(µm)
-3507
-3381
-3339
-3297
-3255
-3129
-3087
-3045
-3003
-2877
-2835
-2793
-2751
-2709
-2667
-2625
-2583
-2541
-2499
-2457
-2415
-2289
-2163
-2121
-2079
-2037
-1911
-1869
-1827
-1785
-1659
-1617
-1575
-1533
-1407
-1365
-1323
-1281
-1155
-1113
-1071
-1029
-903
-861
-735
-693
-651
-609
-567
-525
Y(µm)
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-3-
NJU6820
■ PAD COORDINATES 2
Chip Size 18860µm x 2390µm (Chip Center 0µm x 0µm )
PAD
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
-4-
Terminal
VSS
VSS
VSS
VSS
VSS
VSS
DMY66
VLCD
VLCD
VLCD
VLCD
VLCD
VLCD
VLCD
VLCD
VLCD
DMY67
V1
V1
V1
V1
V1
V1
V1
V1
V1
V2
V2
V2
V2
V2
V2
V2
V2
V2
DMY68
V3
V3
V3
V3
V3
V3
V3
V3
V3
V4
V4
V4
V4
V4
X(µm)
Y(µm)
-483
-441
-399
-357
-315
-273
-147
-21
21
63
105
147
189
231
273
315
357
399
441
483
525
567
609
651
693
735
861
903
945
987
1029
1071
1113
1155
1197
1239
1281
1323
1365
1407
1449
1491
1533
1575
1617
1743
1785
1827
1869
1911
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Terminal
V4
V4
V4
V4
DMY69
VREG
VREG
VREG
VREG
VREG
VREG
VREG
VREG
VREG
VREG
DMY70
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
DMY71
VBA
VBA
VBA
VBA
VBA
VBA
VBA
VBA
VBA
VBA
DMY72
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VOUT
VOUT
X(µm)
1953
1995
2037
2079
2121
2163
2205
2247
2289
2331
2373
2415
2457
2499
2541
2583
2625
2667
2709
2751
2793
2835
2877
2919
2961
3003
3045
3087
3129
3171
3213
3255
3297
3339
3381
3423
3465
3507
3549
3591
3633
3675
3717
3759
3801
3843
3885
3927
4095
4137
Y(µm)
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
PAD
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Terminal
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
DMY73
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
DMY74
C1+
C1+
C1+
C1+
C1+
C1+
C1+
C1+
C1+
C1+
DMY75
C1C1C1C1C1C1C1C1C1C1DMY76
C2+
C2+
C2+
C2+
C2+
C2+
C2+
C2+
X(µm)
4179
4221
4263
4305
4347
4389
4431
4473
4641
4683
4725
4767
4809
4851
4893
4935
4977
5019
5061
5187
5229
5271
5313
5355
5397
5439
5481
5523
5565
5607
5649
5691
5733
5775
5817
5859
5901
5943
5985
6027
6069
6111
6153
6195
6237
6279
6321
6363
6405
6447
Y(µm)
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
NJU6820
■ PAD COORDINATES 3
Chip Size 18860µm x 2390µm (Chip Center 0µm x 0µm )
PAD
No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
Terminal
C2+
C2+
DMY77
C2C2C2C2C2C2C2C2C2C2DMY78
C3+
C3+
C3+
C3+
C3+
C3+
C3+
C3+
C3+
C3+
DMY79
C3C3C3C3C3C3C3C3C3C3DMY80
C4+
C4+
C4+
C4+
C4+
C4+
C4+
C4+
C4+
C4+
DMY81
C4C4C4-
X(µm)
Y(µm)
6489
6531
6573
6615
6657
6699
6741
6783
6825
6867
6909
6951
6993
7035
7077
7119
7161
7203
7245
7287
7329
7371
7413
7455
7497
7539
7581
7623
7665
7707
7749
7791
7833
7875
7917
7959
8001
8043
8085
8127
8169
8211
8253
8295
8337
8379
8421
8463
8505
8547
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
PAD
No.
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
Terminal
C4C4C4C4C4C4C4DMY82
DMY83
DMY84
DMY85
DMY86
DMY86
DMY86
DMY87
DMY88
DMY89
DMY90
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
DMY91
DMY92
DMY93
SEGA0
SEGB0
SEGC0
SEGA1
SEGB1
SEGC1
SEGA2
SEGB2
SEGC2
X(µm)
8589
8631
8673
8715
8757
8799
8841
8883
8925
8967
9225
9225
9225
9225
9225
9135
9093
9051
9009
8967
8925
8883
8841
8799
8757
8715
8673
8631
8589
8547
8505
8463
8421
8379
8337
8295
8253
8211
8169
8127
8085
8043
8001
7959
7917
7875
7833
7791
7749
7707
Y(µm)
-990
-990
-990
-990
-990
-990
-990
-990
-990
-990
-910
-868
-826
-784
-742
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
PAD
No.
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
Terminal
SEGA3
SEGB3
SEGC3
SEGA4
SEGB4
SEGC4
SEGA5
SEGB5
SEGC5
SEGA6
SEGB6
SEGC6
SEGA7
SEGB7
SEGC7
SEGA8
SEGB8
SEGC8
SEGA9
SEGB9
SEGC9
SEGA10
SEGB10
SEGC10
SEGA11
SEGB11
SEGC11
SEGA12
SEGB12
SEGC12
SEGA13
SEGB13
SEGC13
SEGA14
SEGB14
SEGC14
SEGA15
SEGB15
SEGC15
SEGA16
SEGB16
SEGC16
SEGA17
SEGB17
SEGC17
SEGA18
SEGB18
SEGC18
SEGA19
SEGB19
X(µm)
7665
7623
7581
7539
7497
7455
7413
7371
7329
7287
7245
7203
7161
7119
7077
7035
6993
6951
6909
6867
6825
6783
6741
6699
6657
6615
6573
6531
6489
6447
6405
6363
6321
6279
6237
6195
6153
6111
6069
6027
5985
5943
5901
5859
5817
5775
5733
5691
5649
5607
Y(µm)
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
-5-
NJU6820
■ PAD COORDINATES 4
Chip Size 18860µm x 2390µm (Chip Center 0µm x 0µm )
PAD
No.
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
-6-
Terminal
SEGC19
SEGA20
SEGB20
SEGC20
SEGA21
SEGB21
SEGC21
SEGA22
SEGB22
SEGC22
SEGA23
SEGB23
SEGC23
SEGA24
SEGB24
SEGC24
SEGA25
SEGB25
SEGC25
SEGA26
SEGB26
SEGC26
SEGA27
SEGB27
SEGC27
SEGA28
SEGB28
SEGC28
SEGA29
SEGB29
SEGC29
SEGA30
SEGB30
SEGC30
SEGA31
SEGB31
SEGC31
SEGA32
SEGB32
SEGC32
SEGA33
SEGB33
SEGC33
SEGA34
SEGB34
SEGC34
SEGA35
SEGB35
SEGC35
SEGA36
X(µm)
Y(µm)
5565
5523
5481
5439
5397
5355
5313
5271
5229
5187
5145
5103
5061
5019
4977
4935
4893
4851
4809
4767
4725
4683
4641
4599
4557
4515
4473
4431
4389
4347
4305
4263
4221
4179
4137
4095
4053
4011
3969
3927
3885
3843
3801
3759
3717
3675
3633
3591
3549
3507
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
PAD
No.
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
Terminal
SEGB36
SEGC36
SEGA37
SEGB37
SEGC37
SEGA38
SEGB38
SEGC38
SEGA39
SEGB39
SEGC39
SEGA40
SEGB40
SEGC40
SEGA41
SEGB41
SEGC41
SEGA42
SEGB42
SEGC42
SEGA43
SEGB43
SEGC43
SEGA44
SEGB44
SEGC44
SEGA45
SEGB45
SEGC45
SEGA46
SEGB46
SEGC46
SEGA47
SEGB47
SEGC47
SEGA48
SEGB48
SEGC48
SEGA49
SEGB49
SEGC49
SEGA50
SEGB50
SEGC50
SEGA51
SEGB51
SEGC51
SEGA52
SEGB52
SEGC52
X(µm)
3465
3423
3381
3339
3297
3255
3213
3171
3129
3087
3045
3003
2961
2919
2877
2835
2793
2751
2709
2667
2625
2583
2541
2499
2457
2415
2373
2331
2289
2247
2205
2163
2121
2079
2037
1995
1953
1911
1869
1827
1785
1743
1701
1659
1617
1575
1533
1491
1449
1407
Y(µm)
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
PAD
No.
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
Terminal
SEGA53
SEGB53
SEGC53
SEGA54
SEGB54
SEGC54
SEGA55
SEGB55
SEGC55
SEGA56
SEGB56
SEGC56
SEGA57
SEGB57
SEGC57
SEGA58
SEGB58
SEGC58
SEGA59
SEGB59
SEGC59
SEGA60
SEGB60
SEGC60
SEGA61
SEGB61
SEGC61
SEGA62
SEGB62
SEGC62
SEGA63
SEGB63
SEGC63
SEGA64
SEGB64
SEGC64
SEGA65
SEGB65
SEGC65
SEGA66
SEGB66
SEGC66
SEGA67
SEGB67
SEGC67
SEGA68
SEGB68
SEGC68
SEGA69
SEGB69
X(µm)
1365
1323
1281
1239
1197
1155
1113
1071
1029
987
945
903
861
819
777
735
693
651
609
567
525
483
441
399
357
315
273
231
189
147
105
63
21
-21
-63
-105
-147
-189
-231
-273
-315
-357
-399
-441
-483
-525
-567
-609
-651
-693
Y(µm)
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
NJU6820
■ PAD COORDINATES 5
Chip Size 18860µm x 2390µm (Chip Center 0µm x 0µm )
PAD
No.
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
Terminal
SEGC69
SEGA70
SEGB70
SEGC70
SEGA71
SEGB71
SEGC71
SEGA72
SEGB72
SEGC72
SEGA73
SEGB73
SEGC73
SEGA74
SEGB74
SEGC74
SEGA75
SEGB75
SEGC75
SEGA76
SEGB76
SEGC76
SEGA77
SEGB77
SEGC77
SEGA78
SEGB78
SEGC78
SEGA79
SEGB79
SEGC79
SEGA80
SEGB80
SEGC80
SEGA81
SEGB81
SEGC81
SEGA82
SEGB82
SEGC82
SEGA83
SEGB83
SEGC83
SEGA84
SEGB84
SEGC84
SEGA85
SEGB85
SEGC85
SEGA86
X(µm)
Y(µm)
-735
-777
-819
-861
-903
-945
-987
-1029
-1071
-1113
-1155
-1197
-1239
-1281
-1323
-1365
-1407
-1449
-1491
-1533
-1575
-1617
-1659
-1701
-1743
-1785
-1827
-1869
-1911
-1953
-1995
-2037
-2079
-2121
-2163
-2205
-2247
-2289
-2331
-2373
-2415
-2457
-2499
-2541
-2583
-2625
-2667
-2709
-2751
-2793
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
PAD
No.
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
Terminal
SEGB86
SEGC86
SEGA87
SEGB87
SEGC87
SEGA88
SEGB88
SEGC88
SEGA89
SEGB89
SEGC89
SEGA90
SEGB90
SEGC90
SEGA91
SEGB91
SEGC91
SEGA92
SEGB92
SEGC92
SEGA93
SEGB93
SEGC93
SEGA94
SEGB94
SEGC94
SEGA95
SEGB95
SEGC95
SEGA96
SEGB96
SEGC96
SEGA97
SEGB97
SEGC97
SEGA98
SEGB98
SEGC98
SEGA99
SEGB99
SEGC99
SEGA100
SEGB100
SEGC100
SEGA101
SEGB101
SEGC101
SEGA102
SEGB102
SEGC102
X(µm)
-2835
-2877
-2919
-2961
-3003
-3045
-3087
-3129
-3171
-3213
-3255
-3297
-3339
-3381
-3423
-3465
-3507
-3549
-3591
-3633
-3675
-3717
-3759
-3801
-3843
-3885
-3927
-3969
-4011
-4053
-4095
-4137
-4179
-4221
-4263
-4305
-4347
-4389
-4431
-4473
-4515
-4557
-4599
-4641
-4683
-4725
-4767
-4809
-4851
-4893
Y(µm)
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
PAD
No.
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
Terminal
SEGA103
SEGB103
SEGC103
SEGA104
SEGB104
SEGC104
SEGA105
SEGB105
SEGC105
SEGA106
SEGB106
SEGC106
SEGA107
SEGB107
SEGC107
SEGA108
SEGB108
SEGC108
SEGA109
SEGB109
SEGC109
SEGA110
SEGB110
SEGC110
SEGA111
SEGB111
SEGC111
SEGA112
SEGB112
SEGC112
SEGA113
SEGB113
SEGC113
SEGA114
SEGB114
SEGC114
SEGA115
SEGB115
SEGC115
SEGA116
SEGB116
SEGC116
SEGA117
SEGB117
SEGC117
SEGA118
SEGB118
SEGC118
SEGA119
SEGB119
X(µm)
-4935
-4977
-5019
-5061
-5103
-5145
-5187
-5229
-5271
-5313
-5355
-5397
-5439
-5481
-5523
-5565
-5607
-5649
-5691
-5733
-5775
-5817
-5859
-5901
-5943
-5985
-6027
-6069
-6111
-6153
-6195
-6237
-6279
-6321
-6363
-6405
-6447
-6489
-6531
-6573
-6615
-6657
-6699
-6741
-6783
-6825
-6867
-6909
-6951
-6993
Y(µm)
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
-7-
NJU6820
■ PAD COORDINATES 6
Chip Size 18860µm x 2390µm (Chip Center 0µm x 0µm )
PAD
No.
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
-8-
Terminal
SEGC119
SEGA120
SEGB120
SEGC120
SEGA121
SEGB121
SEGC121
SEGA122
SEGB122
SEGC122
SEGA123
SEGB123
SEGC123
SEGA124
SEGB124
SEGC124
SEGA125
SEGB125
SEGC125
SEGA126
SEGB126
SEGC126
SEGA127
SEGB127
SEGC127
DMY94
DMY95
DMY96
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
DMY97
DMY98
X(µm)
-7035
-7077
-7119
-7161
-7203
-7245
-7287
-7329
-7371
-7413
-7455
-7497
-7539
-7581
-7623
-7665
-7707
-7749
-7791
-7833
-7875
-7917
-7959
-8001
-8043
-8085
-8127
-8169
-8211
-8253
-8295
-8337
-8379
-8421
-8463
-8505
-8547
-8589
-8631
-8673
-8715
-8757
-8799
-8841
-8883
-8925
-8967
-9009
-9051
-9093
Y(µm)
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
990
PAD
No.
801
802
803
804
805
806
801
802
803
804
805
806
801
802
Terminal
DMY99
DMY100
DMY101
DMY101
DMY101
DMY102
DMY99
DMY100
DMY101
DMY101
DMY101
DMY102
DMY99
DMY100
X(µm)
-9135
-9225
-9225
-9225
-9225
-9225
-9135
-9225
-9225
-9225
-9225
-9225
-9135
-9225
Y(µm)
990
-742
-784
-826
-868
-910
990
-742
-784
-826
-868
-910
990
-742
PAD
No.
Terminal
X(µm)
Y(µm)
NJU6820
COM39
COM0
VSS
SEGA126
SEGB126
SEGC126
SEGA127
SEGB127
SEGC127
VSSH
SEGA1
SEGB1
SEGC1
SEGA0
SEGB0
SEGC0
■ BLOCK DIAGRAM
VSSA
VDDA
VDD
Common Driver
Gradation Circuit
Shift Register
Data Latch Circuit
VBA
VREG
Display Data RAM
(DD RAM)
128x40x(4+4+4)bit
D15
Initial Display Line Register
VREF
Line Address Decoder
Voltage
regulator
Row Address Decoder
VEE
Row Address Counter
C4+
C4VOUT
Voltage
booster
Row Address Register
C1+
C1C2+
C2C3+
C3-
Line Counter
VLCD, V1 -V4
Segment Driver
5
Column Address Decoder
D14
RAM
Interface
D13
D12
Display
Timing
Generator
Column Address Counter
D11
FR
FLM
CL
D10
D8
D7
Column Address Register
I/O Buffer
D9
CLK
Oscillator
OSC2
OSC1
D6
D5
D4/SPOL
D3/SMODE
D2
Bus Holder
Pole Control
Instruction
Decoder
Register Read
Control
Internal Bus
D1/SDA
D0/SCL
RESET
MPU Interface
CSb
RS
RDb
WRb
P/S
SEL68
RESb
-9-
NJU6820
! POWER SUPPLY CIRCUITS BLOCK DIAGRAM
VBA
Reference
Voltage
Generator
-
Voltage regulator
VREG
VREF
+
+
Gain
Control
(1x-5x)
E.V.R
1/2VREG
EVR register
Boost level register
C1+
C1C2+
C2C3+
Voltage
Booster
C3C4+
C4VEE
- 10 -
VOUT
+
-
VLCD
+
-
V1
+
-
V2
+
-
V3
+
-
V4
NJU6820
■ TERMINAL DESCRIPTION 1
No.
111-121
146-156
239-248
10,11,
42,43,
Symbol
VDD
VSS
VSSH
VDDA
I/O
Power
Power
Power
Power
4,5,
16,17,
76,77,
VSSA
Power
158-166
168-176
177-185
187-195
196-204
VLCD
V1
V2
V3
V4
Power/O
271-280
282-291
293-302
304-313
315-324
326-335
337-346
348-357
228-237
217-226
260-269
C1+
C1C2+
C2C3+
C3C4+
C4VBA
VREF
VEE
O
Function
Power supply for logic circuits
GND for logic circuits
GND for high voltage circuits
This terminal is internally connected to the VDD level.
•This terminal is used to fix the selection terminals to the VDD
level.
Note) Do not use this terminal for a main power supply.
This terminal is internally connected to the VSS level.
•This terminal is used to fix the selection terminals to the VSS
level.
Note) Do not use this terminal for a main GND.
LCD driving voltages
•When the internal voltage booster is not used, external LCD
driving voltages (V1 to V4 and VLCD) must be supplied on these
terminals. The external voltages must be maintained with the
following relation.
VSS<V4<V3<V2<V1<VLCD
• When the internal voltage booster is used, the LCD driving
voltages (V1 to V4 and VLCD) are enabled by the “Power control”
instruction. The capacitors between the VSS and these terminals
are necessary.
Capacitor connection terminals for the voltage booster
O
Capacitor connection terminals for the voltage booster
O
Capacitor connection terminals for the voltage booster
O
Capacitor connection terminals for the voltage booster
O
I
Power
249-258
VOUT
Power/O
206-215
19,20
VREG
RESb
O
I
7,8
SEL68
I
Output of the reference-voltage generator
Input of the voltage regulator
Input of the voltage booster
•This terminal is normally connected to the VDD level.
Output of the voltage booster
Input for high voltage circuits in using external power supply
Output of the voltage regulator
Reset
Active “0”
MPU interface type select
SEL68
H
L
Status
68 series
80 series
- 11 -
NJU6820
■ TERMINAL DESCRIPTION 2
No.
45,46
Symbol
D0/SCL
I/O
I/O
49,50
D1/SDA
I/O
57,58
D3/SMODE
I/O
61,62
D4/SPOL
I/O
53,54
65,66
69,70
73,74
D2
D5
D6
D7
I/O
79,80
83,84
87,88
91,92
95,96
99,100
103,104
107,108
24,25
D8
D9
D10
D11
D12
D13
D14
D15
I/O
29,30
CSb
RS
I
I
Function
Parallel interface:
D7 to D0 : 8-bit bi-directional bus
•In the parallel interface mode (P/S=“1”), these terminals connect
to 8-bit bi-directional MPU bus.
Serial interface:
SDA : serial data
SCL : serial clock
SMODE : 3-/4-line serial interface mode selection
SPOL : RS polarity selection (in the 3-line serial interface mode)
•In the 3-/4-line serial interface mode (P/S=“0”), the D0 terminal is
assigned to the SCL and the D1 terminal to the SDA.
•In the 3-line serial interface mode, the D4 terminal is assigned to
the SPOL.
•Serial data on the SDA is fetched at the rising edge of the SCL
signal in the order of the D7, D6…D0, and the fetched data is
converted into 8-bit parallel data at the falling edge of the 8th
SCL signal.
•The SCL signal must be set to “0” after data transmissions or
during non-access.
8-bit bi-directional bus
•In the 16-bit data bus mode, these terminals are assigned to the
upper 8-bit data bus.
•In the serial interface mode or 8-bit data bus mode of the parallel
interface, these terminals must be fixed to “1” or “0”.
Chip select
Active “0”
Resister select
•This signal distinguishes transferred data as an instruction or
display data as follows.
RS
Distinct.
39,40
34,35
RDb (E)
WRb (R/W)
I
I
H
Instruction
L
Display data
80 series MPU interface (P/S=“1”, SEL68=“0”)
RDb signal. Active “L”.
68 series MPU interface (P/S=“1”, SEL68=“1”)
Enable signal. Active “H”.
80 series MPU interface (P/S=“1”, SEL68=“0”)
WRb signal. Active “L”.
68 series MPU interface (P/S=“1”, SEL68=“1”)
R/W signal.
R/W
H
L
Status
Read
Write
- 12 -
NJU6820
■ TERMINAL DESCRIPTION 3
No.
13,14
Symbol
P/S
I/O
I
Function
Parallel / serial interface mode selection
Chip
Data/
Data
P/S
Instruction
Select
H
CSb
RS
D0 ~ D7
Read/Write
Serial clock
RDb, WRb
-
L
124,125
CL
O
128,129
132,133
136,137
140,141
143,144
FLM
FR
CLK
OSC1
OSC2
O
O
O
I
O
RS
SDA (D1)
Write only
SCL (D0)
CSb
•Since the D15 to D5 and D2 terminals are in the high impedance in the
serial inter face mode (P/S=”0”), they must be fixed to “1” or “0”. The
RDb and WRb terminals also must be “1” or “0”.
This terminal must be opened.
This terminal must be opened.
This terminal must be opened.
This terminal must be opened.
OSC
•When the internal oscillator clock is used, OSC1 terminal must be
fixed to “1” or “0”, and the OSC2 terminal must be opened. When the
oscillation frequency from the internal oscillator is adjusted by an
external resistor between OSC1 terminal and OSC2.
•When an external oscillator is used, external clock is input to the
OSC1 terminal or an external resistor is connected between the OSC1
and OSC2 terminals.
- 13 -
NJU6820
■ TERMINAL DESCRIPTION 4
No.
392-775
Symbol
SEGA0 - SEGA127,
SEGB0 - SEGB127,
SEGC0 - SEGC127
I/O
O
Function
Segment output
REV Mode
Normal
Reverse
Turn-off
0
1
Turn-on
1
0
•These terminals output LCD driving waveforms in accordance
with the combination of the FR signal and display data.
In the B/W mode
FR signal
Display data
Normal display mode
Reverse
mode
369-388,
779-798,
COM0 -COM39
O
display
V2
VLCD
V3
VSS
VLCD
V2
VSS
V3
Common output
# These terminals output LCD driving waveforms in accordance
with the combination of the FR signal and scanning data.
Data
H
L
H
L
FR
H
H
L
L
Output level
VSS
V1
VLCD
V4
Terminal No.
1-3, 12, 18, 21-23, 26-28, 31-33, 36-38, 41, 47, 48, 51, 52, 55, 56, 59, 60, 63, 64, 67, 68, 71, 72, 75, 81,
82, 85, 86, 89, 90, 93, 94, 97, 98, 101, 102, 105, 106, 109, 110, 122, 123, 126, 127, 130, 131, 134, 135,
138, 139, 142, 145, 157, 167, 186, 205, 216, 227, 238, 259, 270, 281, 292, 314, 325, 336, 347, 358-368,
389-391, 776-778, 799-806 are dummy.)
- 14 -
NJU6820
■
Functional Description
(1) MPU Interface
(1-1) Selection of Parallel / serial interface mode select
The P/S terminal is used to select parallel or serial interface mode as shown in the following table.
In the serial interface mode, it is possible to read out display data from the DDRAM and status from
the internal registers.
Table1
P/S
P/S mode
CSb
RS
H
Parallel I/F
CSb
RS
L
Serial I/F
CSb
RS
Note 1) “ -” : Fix to “1” or “0”.
RDb
RDb
-
WRb
WRb
-
SEL68
SEL68
-
SDA
SCL
SDA
SCL
Data
D7-D0 (D15-D0)
-
(1-2) Selection of MPU interface type
In the parallel interface mode, the SEL68 terminal is used to select 68- or 80-series MPU interface
type as shown in the following table.
Table2
SEL68
MPU type
H
68 series MPU
L
80 series MPU
CSb
CSb
CSb
RS
RS
RS
RDb
E
RDb
WRb
R/W
WRb
Data
D7-D0 (D15-D0)
D7-D0 (D15-D0)
(1-3) Data distinction
In the parallel interface mode, the combination of RS, RDb, and WRb (R/W) signals distinguishes
transferred data between the LSI and MPU as instruction or display data, as shown in the following
table.
Table3
RS
H
H
L
L
68 series
R/W
H
L
H
L
80 series
RDb
WRb
L
H
H
L
L
H
H
L
Function
Read out instruction data
Write instruction data
Read out display data
Write display data
(1-4) Selection of serial interface mode
In the serial interface mode, the SMODE terminal is used to select the 3- or 4-line serial interface
mode as shown in the following table.
Table4
SMODE
H
L
Serial interface mode
3-line
4-line
- 15 -
NJU6820
(1-5) 4-line serial interface mode
In the 4-line serial interface mode, when during the chip select is active (CSb=“0”), the SDA and the
SCL are enabled. When During the chip select is not active (CSb=“1”), the SDA and the SCL are
disabled and the internal shift register and the counter are being initialized. The 8-bit serial data on
the SDA is fetched at the rising edge of the SCL signal (serial clock) in order of the D7, D6…D0, and
the fetched data is converted into the 8-bit parallel data at the rising edge of the 8th SCL signal.
In the 4-line serial interface mode, the transferred data on the SDA is distinguished as display data
or instruction data in accordance with the condition of the RS signal.
RS
H
L
Table5
Data distinction
Instruction data
Display data
Since the serial interface operation is sensitive to external noises, the SCL should be set to “0” after
data transmissions or during non-access. To release a mal-function caused by the external noises,
the chip-selected status should be released (CSb=“1”) after each of the 8-bit data transmissions. The
following figure illustrates the interface timing for the 4-line serial interface operation.
CSb
RS
SDA
VALID
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
SCL
Fig1
- 16 -
4-line serial interface timing
NJU6820
(1-6) 3-line serial interface mode
In the 3-line serial interface mode, when the chip select is active (CSb=“0”), the SDA and SCL are
enabled. When the chip select is not active (CSb=“1”), the SDA and SCL are disabled and the
internal shift register and counter are being initialized. 9-bit serial data on the SDA is fetched at the
rising edge of the SCL signal in order of the RS, D7, D6…D0, and the fetched data is converted into
the 9-bit parallel data at the rising edge of the 9th SCL signal.
In the 3-line serial interface mode, data on the SDA is distinguished as display data or instruction
data in accordance with the condition of the RS bit of SDA data and the status of the SPOL, as
follows.
Table6
RS
L
H
SPOL=L
Data distinction
Display data
Instruction data
SPOL=H
Data distinction
Instruction data
Display data
RS
L
H
Since the serial interface operation is sensitive to external noises, the SCL must be set to “0” after
data transmissions or during non-access. To release a mal-function caused by the external noises,
the chip-selected status should be released (CSb=“1”) after each of 9-bit data transmissions. The
following figure illustrates the interface timing of the 3-line serial interface operation.
CSb
SDA
RS
D7
D6
D5
D4
1
2
3
4
5
D3
D2
D1
D0
SCL
Fig2
6
7
8
9
3-line serial interface timing
- 17 -
NJU6820
(2) Access to the DDRAM
When the CSb signal is ”0”, the transferred data from MPU is written into the DDRAM or instruction
register in accordance with the condition of the RS signal.
When the RS signal is “1”, the transferred data is distinguished as display data. After the “column
address” and “row address” instructions are executed, the display data can be written into the DDRAM by
the “display data write” instruction. The display data is written at the rising edge of the WRb signal in the
80 series MPU mode, or at the falling edge of the E signal in the 68 series MPU mode.
Table6
RS
Data
L
Display RAM Data
H
Internal Command Register
In the sequence of the “display data read” operation, the transferred data from MPU is temporarily held
in the internal bus-holder and then transferred to the internal data-bus. When the “display data read”
operation is executed just after the “column address” and “row address” instructions or “display data write”
instruction, unexpected data on the bus-holder is read out at the 1st execution, then the data of
designated DDRAM address is read out from the 2nd execution. For this reason, a dummy read cycle
must be executed to avoid the unexpected 1st data read.
Display data write operation
D0 to D15
n
n+1
n+2
n+3
n+4
Internal
WRb
n
Bus Holder
n+1
n+2
n+3
n+4
WRb
Display data read operation
WRb
D0 to D7(D0 to D15)
n
Address Set
n
n
Dummy
Read
Data Read
n Address
n+1
Data Read
n+1 Address
n+2
Data Read
n+2 Address
RDb
Fig3
Note) In the16-bit data bus mode, instruction data must be 16-bit as well as the display data.
- 18 -
NJU6820
(3) Access to the instruction register
Each instruction resisters is assigned to each address between 0H and FH, and the content of the
instruction register can be read out by the combination of the “Instruction resister address” and ”Instruction
resister read”.
WRb
D0 to D7
M
m
N
n
Instruction resister
address set
Instruction resister
contents read
Instruction resister
address set
Instruction resister
contents read
RDb
Fig4
(4) 8-/16-bit data bus length for display data (in the parallel interface mode)
The 8- or 16-bit data bus length for display data is determined by the “WLS” of the “Data bus length”
instruction.
In the 16-bit data bus mode, not only the display data but also the instruction data is required to be
transferred by 16-bit data (D15 to D0). However, for the access to the instruction register, the only lower 8bit data (D7 to D0) of the 16-bit data is valid. For the access to the DDRAM, all of the 16-bit data (D15 to D0)
is valid.
Table8
WLS
0
1
Data bus length mode
8-bit
16-bit
(5) Initial display line register
The initial display line resister specifies the line address, corresponding to the initial COM line, by the
“Initial display line” instruction. The initial COM line signifies the common driver, starting scanning the
display data in the DDRAM, and specified by the “Initial COM line” instruction.
The line address, established in the initial display line resister, is preset into the line counter whenever
the FLM signal becomes “1”. At the rising edge of the CL signal, the line counter is counted-up and
addressed 384-bit display data corresponding to the counted-up line address, is latched into the data latch
circuit. At the falling edge of the CL signal, the latched data outputs to the segment drivers.
- 19 -
NJU6820
(6) DDRAM mapping
The DDRAM is capable of 1,536-bit (12-bit x 128-segment) for the column address and 40-bit for the
row address.
In the gradation mode, each pixel for RGB corresponds to successive 3-segment drivers, and each
segment driver has 16-gradation. Therefore, the LSI can drive up to 128x40 pixels in 4096-color display
(16-gradation x 16-gradation x 16-gradation).
# In the 8-bit data bus length mode
column-address
0H
0H
7bit
1H
5bit
FEH
7bit
FFH
5bit
27H
7bit
5bit
7bit
5bit
row-address
column-address
0H
0H
4bit
1H
8bit
FEH
4bit
FFH
8bit
27H
4bit
8bit
4bit
8bit
0H
0H
8bit
1H
8bit
BEH
8bit
BFH
8bit
27H
8bit
8bit
8bit
8bit
0H
0H
8bit
1H
8bit
7EH
8bit
7FH
8bit
27H
8bit
8bit
8bit
8bit
ABS=’1’
row-address
column-address
HSW=’1’
row-address
column-address
C256=’1’
row-address
- 20 -
NJU6820
# In the 16-bit data bus length mode
column-address
0H
0H
12bit
27H
12bit
7FH
12bit
row-address
12bit
Fig6
In the B&W mode, only MSB data from each 4-bit display data group in the DDRAM is used. Therefore,
384 x 40 pixels in the B&W and 128 x 40 pixels in the 8-gradation are available.
The range of the column address varies depending on data bus length. The range between 00H and FFH
is used in the 8-bit data bus length and the range between 00H and 7FH is in the 16-bit data bus length.
The increments for the column address and row address are set to the auto-increment mode by
programming the “AXI” and “AYI” registers of the “Increment control” instruction. In this mode, the
contents of the column address and row address counters automatically increment whenever the DDRAM
is accessed.
The column address and row address counters, independent of the line counter. They are used to
designate the column and row addresses for the display data transferred from MPU. On the other hand,
the line counter is used to generate the line address, and output display data to the segment drivers, being
synchronized with the display control timing of the FLM and CL signals.
- 21 -
NJU6820
0
0
1
1
1
1
1
0
0
1
1
0
0
X
0
X
X
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
X
0
X
1
0
0
0
0
0
0
0
0
0
0
SEG0
Palette B
X=7FH
X=00H
Palette C
Palette A
SEG1
Palette B
X=01H
X=7EH
X=01H
Palette C
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
X=7FH
X=7EH
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X=00H
X=01H
X=02H
X=03H
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X=FEH
X=FFH
X=FCH
X=FDH
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
X=00H
X=01H
X=02H
X=03H
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
X=FEH
X=FFH
X=FCH
X=FDH
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=00H
X=01H
X=02H
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=BFH
X=BDH
X=BEH(H)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=BEH(L)
Palette B
SEG0
Palette C
SEG1
Palette B
Palette C
- D7 D6 D5 D4 D3 D2 D1 D0
- D7 D6 D5 D4 D3 D2 D1 D0
X=7EH
X=01H
-
-
-
Palette A
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
Palette A
- D7 D6 D5 D4 D3 D2 D1 D0
-
Palette A
A0
SEG126
Palette B
X=7EH
Palette C
Palette A
A0
SEG126
Palette B
X=FDH
X=03H
X=FDH
X=03H
X=02H
Palette C
X=BEH
- D7 D6 D5 D4 D3 D2 D1 D0
X=01H
X=7EH
- D7 D6 D5 D4 D3 D2 D1 D0
-
-
-
-
Palette A
X=FEH
X=00H
X=FEH
X=00H
X=00H
SEG127
Palette B
X=7FH
X=00H
X=7FH
X=00H
SEG127
Palette B
Palette C
X=FFH
X=01H
X=FFH
X=01H
X=BFH
X=01H(H)
Palette C
- D7 D6 D5 D4 D3 D2 D1 D0
X=00H
X=7FH
- D7 D6 D5 D4 D3 D2 D1 D0
-
-
-
-
-
-
Palette A
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
X=01H(L)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=BDH
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=02H
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=FCH
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
X=02H
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
X=FCH
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X=01H
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X=7EH
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
X=01H
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
A1
Note1) In the 256-color mode, the vacant LSB bit is filled with "1".
Note2) The function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode).
Note3) The written data in the DD RAM in "C256"=0 in not compatible with the data in "C256"=1.
Note4) In the 256-color mode, only 8-bit length mode is available, but 16-bit is not.
- D7 D6 D5 D4 D3 D2 D1 D0
X=7FH
X=00H
-
-
A2
Palette A
X=00H
A0
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
A0
RAM Map 1
Mode
16bit
8bit
0
X
1
A1
-
Palette C
SEGCx
SEGAx
C0
C0
0
0
1
X
1
X
X
0
X
Palette B
SEGBx
SEGBx
C1
C1
RAM Map 2 (256 Color Mode)
Mode
8bit
0
Palette A
SEGAx
SEGCx
C2
C2
C0
C0
C3
C3
C1
C1
B0
B0
C2
C2
B1
B1
C3
C3
B2
B2
B0
B0
B3
B3
A0
B1
B1
A1
A1
B2
B2
A2
A2
B3
B3
A0
A3
A3
A1
A1
C0
C0
A2
A2
C1
C1
A3
A3
C2
C2
C0
C0
C3
C3
C1
C1
B0
B0
C2
C2
B1
B1
C3
C3
B2
B2
B0
B0
B3
B3
B3
B3
A3
A0
B1
B1
C0
A1
B2
B2
C1
A2
A2
A0
C2
256
256
B3
A3
A3
B2
REF
A0
A1
C3
REF
HSW
A1
A2
B0
ABS
HSW
ABS
A3
A3
B1
WLS
WLS
A2
SWAP
0
0
1
1
0
1
0
1
- 22 -
REF
SWAP
NJU6820
(7) Window addressing mode
In addition to the above usual DDRAM addressing, it is possible to access some part of DDRAM in
using the window addressing mode, in which the start and end points are designated. The start point is
determined by the “column address” and “row address” instructions, and the end point is determined by
the “Window end column address” and “Window end row address” instructions, The setting example of
the window addressing is listed, as follows.
1. Set WIN=1, AXI=1 and AYI=1 by the “Increment control” instruction
2. Set the start point by the “column address” and “row address” instructions
3. Set the end point by the “Window end column address” and “Window end row address”
instructions
4. Enable to access to the DDRAM in the window addressing mode
In the window addressing mode (WIN=1, AXI=1, AYI=1), the read-modify-write operation is available by
setting “0” to the “AIM” register of the ”Increment control” instruction.
And in the window addressing mode, the following start and end point must be maintained to abide a
malfunction.
AX (column address of start point)< EX (column address of end point)< Maximum of column address
AY (row address of start point)< EY (row address of end point)< Maximum of row address
column address
row address
(X, Y)
Start point
Window display area
End point
(X, Y)
Whole DDRAM area
Fig7
(8) Reverse display ON/OFF
The “Reverse display ON/OFF” function is used to reverse the display data without changing the
contents of the DDRAM.
Table9
REV
Display
0
Normal
1
Reverse
DDRAM data → Display data
0
0
1
1
0
1
1
0
(9) Segment direction
The “Segment direction” function is used to reverse the assignment for the segment drivers and column
address, and it is possible to reduce the restrictions for the placement of the LSI on the LCD modules.
- 23 -
- 24 -
palette
C
SEGA127
$%
palette
B
$%
Column address / bit / segment assign
$%
$%
D0
D1
D0
D1
D2
palette
C
D2
SEGC127
D3
D3
D5
D4
X=7FH
X=00H
D4
palette
B
Column address / bit / segment assign
$%
$%
D5
SEGB127
SEGA127
SEGB127
palette
C
palette
B
palette
A
SEGC127
D1
D2
D3
D4
D7
D8
D9
D10
D12
D13
D14
D15
Column address / bit / segment assign
$%
$%
D6
D7
D8
D9
D10
D1
D2
D3
SEGC127
SEGB127
palette
C
palette
B
palette
A
palette
C
SEGC0
SEGA127
palette
B
SEGB0
D1
D2
D3
D4
D7
D8
D9
D10
D12
D13
D14
D1
D2
D3
D4
D7
D8
D9
D10
D12
D13
D14
D15
Column address / bit / segment assign
$%
$%
D6
D7
D8
palette
A
SEGA127
$%
D9
$%
D11
palette
C
SEGA0
$%
D10
D0
D1
D2
$%
D11
palette
C
SEGC0
D4
D7
D8
D9
$%
SEGB127
D0
D1
X=00H
X=7FH
D2
X=00H
X=7FH
$%
palette
A
palette
C
SEGA0
palette
B
SEGB0
X=00H
X=7FH
D3
D4
D5
D6
D10
D12
D13
palette
A
$%
SEGA0
D15
X=00H
X=7FH
D3
ABS REF SWAP
1
0
1
1
1
0
D4
palette
B
SEGB0
ABS REF SWAP
1
0
0
1
1
1
D5
D7
D8
D9
palette
A
$%
SEGC0
ABS REF SWAP
0
0
1
0
1
0
D6
palette
A
$%
SEGA0
D14
D15
ABS REF SWAP
0
0
0
0
1
1
SEGC127
palette
B
$%
SEGB0
D7
D8
D9
HSW
*
*
palette
A
D11
HSW
*
*
D10
HSW
*
*
SEGC0
D11
HSW
*
*
D10
NJU6820
(10) The relationship among the DDRAM column address, display data and segment drivers
In the color mode, and 16-bit data bus mode
X=7FH
X=00H
X=7FH
X=00H
X=7FH
X=00H
palette
C
SEGA127
$%
palette
B
$%
D0
D1
SEGC127
palette
C
D0
D1
D2
D3
SEGA127
palette
C
palette
B
SEGB127
D1
D2
D3
D4
D7
D0
D1
D2
D4
D5
D6
D7
Column address / bit / segment assign
$%
X=01H
X=FEH
$%
X=FFH
X=00H
D2
Column address / bit / segment assign
$%
X=01H
X=FEH
$%
X=FFH
X=00H
D4
D5
palette
A
SEGC127
D1
D2
D3
palette
C
palette
B
SEGB127
SEGC127
palette
A
palette
C
SEGC0
SEGA127
palette
B
SEGB0
D1
D2
D3
D4
D7
D0
D1
D1
D2
D3
D4
D7
D0
D1
D2
D4
D5
D6
D7
Column address / bit / segment assign
$%
X=01H
X=FEH
$%
X=FFH
X=00H
D3
palette
B
SEGB127
D6
D7
D0
D1
D2
Column address / bit / segment assign
$%
X=01H
X=FEH
$%
X=FFH
X=00H
D4
D5
D6
D7
D0
palette
A
SEGA127
$%
D1
$%
D3
palette
C
SEGA0
$%
D2
D0
D1
D2
$%
D3
palette
C
SEGC0
D4
D7
D0
D1
$%
SEGB127
D0
D1
D2
D3
palette
B
SEGB0
D2
D4
D5
D6
$%
palette
A
palette
C
SEGA0
X=00H
X=FEH
D4
D5
D6
X=00H
X=FEH
D3
palette
B
SEGB0
X=00H
X=FEH
D4
D5
D6
D2
D4
D5
palette
A
$%
SEGA0
D7
X=00H
X=FEH
SEGC127
palette
B
$%
SEGB0
D7
D0
D1
palette
A
$%
SEGC0
ABS REF SWAP
0
0
1
0
1
0
D7
palette
A
$%
SEGA0
D6
D7
ABS REF SWAP
0
0
0
0
1
1
D0
D1
ABS REF SWAP
1
0
1
1
1
0
palette
A
HSW
0
0
ABS REF SWAP
1
0
0
1
1
1
SEGC0
HSW
0
0
D2
D3
HSW
0
0
D2
HSW
0
0
D3
NJU6820
In the color mode, and 8-bit data bus mode
X=FFH
X=01H
X=FFH
X=01H
X=FFH
X=01H
X=FFH
X=01H
- 25 -
NJU6820
Palette B
D2
SEGA
126
D1
Palette C
D2
D3
SEGB
127
D1
Palette B
D2
D2
D3
Palette C
D5
D4
X=01H
X=01H
SEGA
127
SEGA
127
Palette C
D2
D1
D0
D2
D1
Palette B
D6
D5
D4
D3
SEGC
127
Palette C
D2
D1
D0
X=BFH
D7
D5
Palette A
X=BFH
D7
D5
D7
SEGB
127
D5
D4
D6
D0
D6
D0
D6
D1
D3
D7
Palette B
D2
D4
SEGA
127
D1
D0
D6
Palette C
D0
SEGB
127
D1
Palette B
X=BEH
D4
Palette A
X=00H
D2
D5
D3
X=BEH
D3
Palette A
D4
SEGC
126
D5
D7
D5
D5
D7
D6
D7
SEGC
127
D6
D0
D4
D6
Palette A
D7
D0
SEGC
127
D7
SEGA
126
D0
D0
D6
D1
D0
SEGB
126
D1
D2
X=BDH
D5
D3
Palette C
SEGB
126
Palette C
Column-address / bit / segment assign
D6
D4
SEGA
126
D1
D3
D5
X=02H
D4
X=02H
D2
D4
- 26 -
Palette B
D5
D6
D3
SEGC
1
X=01H
D5
X=00H
Palette C
SEGB
126
X=02H
SEGC
127
Palette A
D6
X=BDH
D0
D7
D7
D6
D3
Palette B
D1
D1
D0
SEGC
126
X=00H
Palette A
D2
D2
Palette B
D4
Column-address / bit / segment assign
D3
SEGC
126
Palette C
SEGB
1
D5
X=02H
D4
X=01H
D1
D5
X=BEH
D2
Palette C
Column-address / bit / segment assign
D5
SEGA
1
D1
D7
D6
D3
D6
D2
D0
D7
SEGA
1
Palette A
D7
D7
D4
SEGB
127
Palette B
D5
D0
D4
X=01H
Palette A
SEGB
1
D1
D6
D3
SEGA
1
D1
D0
X=BEH
SEGA
127
D2
D1
D4
D2
D0
D6
0
Palette B
Palette A
X=BDH
SEGB
1
D1
SEGC
1
D5
D3
D2
D3
Palette C
D6
D4
0
Palette A
*
D5
1
D3
Palette C
X=01H
D7
D2
D7
SEGC
0
D5
D7
D4
SEGC
126
Palette C
D4
SEGC
1
Palette B
D0
D6
D0
D6
SEGB
0
D1
D0
D7
Palette B
D1
D5
D3
D2
D7
SEGA
0
D6
D4
D0
D2
HSW ABS REF SWAP
Palette C
Palette B
X=BFH
D1
D0
SEGB
126
D5
D3
SEGA
0
SEGB
0
Palette A
X=00H
Palette B
D6
D4
D2
D3
Palette A
1
D5
D4
SEGA
126
X=BEH
SEGB
0
Column-address / bit / segment assign
Palette C
0
0
D6
SEGA
0
D5
D3
X=BDH
SEGC
1
Palette A
D7
D3
Palette B
SEGC
0
D7
D4
SEGB
1
D1
D7
D6
D4
X=BFH
Palette A
X=BEH
SEGA
1
Palette A
D7
D0
D3
Palette C
SEGC
0
D2
D0
D4
SEGC
0
*
1
1
Palette B
D1
1
*
1
SEGB
0
Palette A
D3
HSW ABS REF SWAP
1
*
SEGA
0
D2
HSW ABS REF SWAP
1
HSW ABS REF SWAP
D3
NJU6820
In the color mode, 8-bit data bus mode, and C256 mode (C256=1)
D0
D1
D1
SEGB127
SEGC127
palette
C
D2
D2
D3
palette
B
D4
D0
palette
C
SEGA127
D3
palette
B
SEGB127
D4
D6
palette
A
D5
D5
X=7FH
X=00H
palette
A
D6
X=7FH
X=00H
SEGC127
$%
D7
D0
D1
palette
C
SEGA0
D2
D3
palette
B
$%
SEGB0
D4
$%
palette
A
D5
Column address / bit / segment assign
$%
$%
SEGC0
D6
X=00H
X=7FH
SEGA127
$%
D7
D0
D1
palette
C
SEGC0
D3
palette
B
SEGB0
D4
palette
A
$%
SEGA0
D5
Column address / bit / segment assign
$%
$%
$%
ABS REF SWAP
*
0
1
*
1
0
D7
HSW
*
*
D6
X=00H
X=7FH
D2
ABS REF SWAP
*
0
0
*
1
1
D7
HSW
*
*
- 27 -
- 28 $%
$%
$%
Column address / bit / segment assign
$%
$%
SEGC127
Column address / bit / segment assign
$%
$%
SEGB127
SEGA127
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SEGC127
SEGA127
SEGB127
Column address / bit / segment assign
$%
$%
SEGA127
X=00H
X=7FH
$%
SEGC127
SEGB127
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
$%
SEGA127
SEGC0
SEGB0
SEGA0
Column address / bit / segment assign
$%
$%
SEGB127
ABS REF SWAP
1
0
1
1
1
0
$%
SEGC127
X=00H
X=7FH
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ABS REF SWAP
1
0
0
1
1
1
SEGA0
X=00H
X=7FH
SEGC0
$%
SEGB0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ABS REF SWAP
0
0
1
0
1
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HSW
*
*
X=00H
X=7FH
SEGA0
HSW
*
*
$%
SEGC0
HSW
*
*
ABS REF SWAP
0
0
0
0
1
1
SEGB0
SEGA0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HSW
*
*
SEGB0
SEGC0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NJU6820
In the B&W mode, and 16-bit data bus mode
X=7FH
X=00H
X=7FH
X=00H
X=7FH
X=00H
X=7FH
X=00H
NJU6820
In the B&W mode, and 8-bit data bus mode
D2
D1
D1
D3
D2
D3
D4
SEGA127
D2
D1
D0
D2
D1
D0
D3
SEGC127
D3
SEGA127
D4
D5
D6
D7
X=FFH
X=01H
SEGB127
D0
D1
D2
D3
$%
SEGC127
D0
D1
D2
D3
D4
D5
$%
D4
D5
D6
D7
X=FFH
X=01H
SEGB127
D0
D1
D2
D3
$%
SEGA127
D0
D1
D2
D3
SEGC0
D4
$%
D7
D0
D1
D2
SEGB127
D4
D5
D6
D7
SEGC127
D1
D2
$%
D4
SEGC127
D7
D0
D1
D2
SEGB127
D4
D5
D6
D7
SEGA127
D1
D2
D3
D3
D4
SEGA0
D7
D0
D5
D6
D6
D7
SEGB0
D0
D1
D2
$%
X=FFH
X=01H
Column address / bit / segment assign
$%
X=01H
X=FEH
$%
X=FFH
X=00H
X=00H
X=FEH
D3
D4
SEGC0
D7
D0
D1
D1
SEGB0
D7
SEGB0
D0
D1
D2
SEGA0
ABS REF SWAP
1
0
1
1
1
0
$%
Column address / bit / segment assign
$%
X=01H
X=FEH
$%
X=FFH
X=00H
X=00H
X=FEH
SEGC0
HSW
0
0
D2
D4
D5
D6
SEGC0
ABS REF SWAP
1
0
0
1
1
1
$%
X=FFH
X=01H
Column address / bit / segment assign
$%
X=01H
X=FEH
$%
X=FFH
X=00H
X=00H
X=FEH
D3
HSW
0
0
D2
SEGB0
D4
D5
D6
SEGA0
ABS REF SWAP
0
0
1
0
1
0
D7
HSW
0
0
Column address / bit / segment assign
$%
X=01H
X=FEH
$%
X=FFH
X=00H
X=00H
X=FEH
SEGA0
ABS REF SWAP
0
0
0
0
1
1
D7
HSW
0
0
- 29 -
NJU6820
1
*
0
0
1
D4
SEGB 0
D3
D2
D5
D5
D1
D1
SEGA 0
D3
X=BFH
D3
D4
D0
SEGA 0
D0
SEGC 0
D7
D7
D6
D6
D1
D1
D5
D5
D0
D0
D4
SEGC 1
SEGC 1
D7
D3
D4
SEGA 1
D3
D6
D6
D2
D2
D5
D5
D1
D1
SEGB 1
D3
X=BDH
D3
D4
D0
SEGB 1
D0
SEGB 1
D7
D7
D6
D6
D1
D1
D5
D5
D0
D0
D4
SEGA 1
D2
D1
D1
D0
SEGC 126 D7
D6
D5
D3
D2
D1
D0
SEGA 126 D7
D6
D5
D4
SEGB 126 D3
SEGB 126 D7
SEGB 126 D7
SEGB 126 D3
D6
D6
D2
D2
D5
D5
D1
D1
D4
SEGA 126 D3
X=02H
SEGC 126 D3
X=02H
D4
D0
D0
SEGA 126 D7
SEGC 126 D7
D6
D6
D1
D5
D5
D0
D0
D4
SEGA 127 D7
SEGC 127 D7
SEGC 127 D3
D6
D6
D2
D2
D5
D5
D1
D1
D4
SEGB 127 D3
X=00H
SEGB 127 D3
X=00H
D4
D4
SEGA 127 D3
D0
D0
SEGB 127 D7
SEGB 127 D7
D6
D6
D1
D5
D5
D0
D0
D4
SEGC 127 D7
SEGA 127 D7
SEGA 127 D3
D4
D6
D5
D4
X=01H
D5
X=01H
D6
D4
SEGC 127 D3
D2
D2
D1
D1
D0
D0
X=BFH
D2
D1
X=BFH
D2
X=BEH
D2
D1
X=BEH
D2
X=BDH
D4
X=BDH
D0
D2
D4
SEGC 1
Column-address / bit / segment assign
SEGC 126 D3
D3
Column-address / bit / segment assign
D0
D4
X=01H
D1
X=01H
D2
D5
X=BEH
SEGA 126 D3
D6
Column-address / bit / segment assign
X=BEH
D4
Column-address / bit / segment assign
D5
SEGA 1
D7
X=02H
D2
X=02H
D2
D7
X=01H
D2
X=01H
D2
D7
X=00H
X=00H
D3
HSW ABS REF SWAP
0
D5
D2
D6
- 30 -
D6
D5
D6
X=BDH
SEGC 1
SEGB 0
D7
D6
D4
D7
SEGA 0
D7
D6
D4
SEGB 1
SEGB 0
X=BFH
SEGA 1
D0
D7
D4
SEGC 0
*
SEGB 0
X=BEH
D1
1
0
X=BEH
D2
D0
SEGC 0
D3
HSW ABS REF SWAP
1
1
D1
*
1
D2
1
*
SEGC 0
D3
HSW ABS REF SWAP
1
HSW ABS REF SWAP
SEGA 0
NJU6820
Bit assignments between write and read data (in the 16-bit data bus mode)
ABS=0
Write data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read data
D15
D14
D13
D12
*
D10
D9
D8
D7
*
*
D4
D3
D2
D1
*
Write data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read data
*
*
*
*
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ABS=1
Examples of write and read data (In the 8 bit bus mode)
ABS=0, HSW=0, C256=0
(Address; 00, 02……FC,FEH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
Read data
D7
D6
D5
D4
1
D2
D1
D0
ABS=0, HSW=0, C256=0
(Address; 01,03……FD,FFH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
Read data
D7
1
1
D4
D3
D2
D1
1
ABS=1, HSW=0, C256=0
(Address; 00, 02……FC,FEH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
Read data
1
1
1
1
D3
D2
D1
D0
ABS=1, HSW=0, C256=0
(Address; 01,03……FD,FFH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
Read data
D7
D6
D5
D4
D3
D2
D1
D0
ABS=0, HSW=1, C256=0
(Address; 00, 01……BE,BFH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
Read data
D7
D6
D5
D4
D3
D2
D1
D0
ABS=0, HSW=0, C256=1
(Address; 00, 01…… 7E ,7FH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
Read data
D7
D6
D5
D4
D3
D2
D1
D0
* : Invalid data
- 31 -
NJU6820
(11) Gradation palette
In the gradation mode, either variable or fixed gradation mode is selected by programming the “PWM”
register of the “Gradation control” instruction.
PWM=0:
Variable gradation mode
(Select 16 gradation levels out of 32-gradation level of the gradation palette)
PWM=1:
Fixed gradation mode
(Fixed 8-gradation levels)
In these mode, each of the gradation palettes Aj, Bj and Cj can select 16-gradation level out of 32gradation level by setting 5-bit data to the “PA” registers in the “Gradation palette j” instructions (j=0 to Fh).
For instance, the gradation palettes Aj correspond to the SEGAi, the Bj to SEGBi and the Cj to SEGCi
(j=0 to 15, i=0 to 127).
Correspondence between display data and gradation palettes
Table 10 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(MSB) Display data (LSB)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Gradation palette
Palette 0
Palette 1
Palette 2
Palette 3
Palette 4
Palette 5
Palette 6
Palette 7
Palette 8
Palette 9
Palette10
Palette11
Palette12
Palette13
Palette14
Palette15
Default palette value
00000
00011
00101
00111
01001
01011
01101
01111
10001
10011
10101
10111
11001
11011
11101
11111
Gradation palette table (Variable gradation mode, PWM=”0”, MON=”0”)
Table 11 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
- 32 -
Palette value
Gradation level
Gradation palette
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
0
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Palette 0(default)
Palette 1(default)
Palette 2(default)
Palette 3(default)
Palette 4(default)
Palette 5(default)
Palette 6(default)
Palette 7(default)
Palette
value
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Gradation
level
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
Gradation palette
Palette 0(default)8
Palette 9(default)
Palette 10(default)
Palette 11(default)
Palette 12(default)
Palette 13(default)
Palette 14(default)
Palette 15(default)
NJU6820
Gradation palette table (Fixed gradation mode, PWM=”1”, MON=”0”)
Table 12 8-gradation segment drivers
(MSB) Display data (LSB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
*
*
*
*
*
*
*
*
Gradation
level
0/7
(MSB) Display data (LSB)
Gradation level
0
0
*
*
1/7
2/7
3/7
4/7
5/7
6/7
7/7
0
0
0
1
1
1
1
0
1
1
0
0
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0/7
3/7
5/7
7/7
Correspondence between display data and gradation level (B&W mode, MON=”1”)
Table 13
(MSB) Display data (LSB)
0
1
*
*
*
*
*
*
Gradation
level
0
1
*:Don’t care
(12) Gradation control and display data
(12-1) Gradation mode
In the graduation mode, each pixel for RGB corresponds to successive 3 segment drivers, and
each segment driver provides 16-gradation PWM output by controlling 4 bit display data of the
DDRAM. Accordingly, the LSI can drive up to 128x40 pixels in 4096-color (16-gradation x 16gradation x 16-gradation = 4-bit x 4-bit x 4-bit).
In addition, the LSI can transfer the display data for the RGB by 16-bit at once or 8-bit two-times.
The data assignment between gradation palettes and segment drivers varies in accordance with
setting for the “SWAP” and “REF” registers of the "Display control (2)" instruction.
(REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
Paltte Aj
Palette Bj
(i=0 to 127)
SEGCi
Gradation palette
j=0 to 15
Palette Cj
Gradation control circuit
0
MSB
0
0
0
0
LSB MSB
0
0
0
D7
0
D6
0
D5
0
D4
ABS=1
(D3
D2
D1
HSW=1
(D7
D6
C256=1
(D7
D6
1
1
LSB MSB
1
1
0
D2
0
D1
0
D0
1
D7
D0
D7
D6
D5
D5
D4
D3
D2
D5
*
D4
D3
1
D4
1
D3
1
D2
1
D1
D4
D3
D2
D1
D0 )
D1
D0
D7
D6
D5
D4 )
D2
*
D1
D0
*
*)
:2nH ,2nH+1H
:FEH -2nH , FFH-(2nH+1H)
HSW=1; 00H to BFH, C256=1; 00H to 7FH
Note) DDRAM column address
1
LSB
Display data in DDRAM
Display data from MPU
Column address:2nH:2n+1H
(REF=”0”)
(REF=”1”)
- 33 -
NJU6820
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi
SEGBi
SEGCi
Palette Aj
Palette Bj
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Cj
Gradation control circuit
1
LSB
1
1
1
1
MSB LSB
0
D7
ABS=1 (D3
HSW=1 (D7
C256=1 (D7
0
D6
D2
D6
D6
0
D5
D1
D5
D5
0
D4
D0
D4
*
0
D2
D7
D3
D4
0
0
0
0
MSB LSB
0
D1
D6
D2
D3
0
D0
D5
D1
D2
1
D7
D4
D0
*
: 2nH ,2nH+1H
: FEH -2nH , FFH-(2nH+1H)
HSW=1; 00H to BFH, C256=; 00H to 7FH
Note) DDRAM column address
1
D4
D3
D7
D1
Display data in DDRAM
0
MSB
0
0
1
D3
D2
D6
D0
1
D2
D1
D5
*
1
D1
D0 )
D4 )
*)
Display data from MPU
Column address:2nH:2n+1H
(REF=”0”)
(REF=”1”)
In the 16-bit data bus mode, the data assignments between the gradation palettes and the segment
drivers vary in accordance with setting for the “SWAP” and “REF” bit of the "Display control (2)"
instruction as well as the assignment in the 8-bit data bus mode.
(REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
Palette Aj
SEGCi
Palette Bj
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Cj
Gradation control circuit
ABS=1
0
MSB
0
0
0
D15
0
D14
0
D13
0
D12
D9
D8
(D11 D10
0
0
LSB MSB
Note) DDRAM column address
- 34 -
0
0
1
1
LSB MSB
0
D10
0
D9
0
D8
1
D7
D7
D6
D5
D4
(REF=”0”)
:nH
:7FH - nH (REF=”1”)
1
1
1
LSB
1
D4
1
D3
1
D2
1
D1
D3
D2
D1
D0 )
Display data in DDRAM
Display data from MPU
Column address;
nH
NJU6820
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi
SEGBi
Palette Aj
Palette Bj
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Cj
Gradation control circuit
ABS=1
1
LSB
1
1
0
0
0
0
D13
D9
D12
D8
D15 D14
(D11 D10
1
1
MSB LSB
Note) DDRAM column address
0
0
0
0
MSB LSB
0
0
0
1
D10
D7
D9
D6
D8
D5
D7
D4
Display data in DDRAM
0
MSB
0
0
1
1
1
1
D4
D3
D3
D2
D2
D1
D1
D0 )
Display data from MPU
Column address
; nH
(REF=”0”)
:nH
:7FH -nH (REF=”1”)
- 35 -
NJU6820
(12-2) B&W mode (MON=”1”)
In the B&W mode, 3 bits of the MSB data are used in both of the 16-bit and 8-bit data bus modes.
In the 16-bit data bus mode (Similarly 8-bit data bus access)
(REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
Palette Aj
Palette Bj
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Cj
Gradation control circuit
ABS=1
0
MSB
0
0
0
0
0
0
D15
D14
D13
D9
(D11 D10
0
0
LSB MSB
0
0
0
0
0
1
D12
D10
D9
D8
D8
D7
D6
D5
Note) DDRAM column address
1
1
LSB MSB
1
1
1
1
1
1
D7
D4
D3
D2
D1
D4
D3
D2
D1
D0 )
SEGBi
Palette Aj
Display data in DDRAM
Display data in DDRAM
Column address; nH
(REF=”0”)
(REF=”1”)
: nH
: 7FH-nH
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi
1
LSB
SEGCi
Palette Bj
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Cj
Gradation control circuit
ABS=1
1
LSB
1
1
0
0
0
0
D15
D14
D13
D9
(D11 D10
1
1
MSB LSB
0
0
0
0
0
1
D12
D10
D9
D8
D8
D7
D6
D5
Note ) DDRAM column address
- 36 -
: nH
: 7FH-nH
0
0
MSB LSB
Display data in DDRAM
0
MSB
0
0
1
1
1
1
D7
D4
D3
D2
D1
D4
D3
D2
D1
D0 )
(REF=”0”)
(REF=”1”)
Display data in DDRAM
Column address;
nH
NJU6820
(13) Display timing generator
The display-timing generator creates the timing pulses such as the CL, the FLM, the FR and the CLK by
dividing the oscillation frequency oscillate an external or internal resister mode. The each of timing pulses
is outputted through the each output terminals by “SON” = 1.
(14) LCD line clock (CL)
The LCD line clock (CL) is used as a count-up signal for the line counter and a latch signal for the data
latch circuit. At the rising edge of the CL signal, the line counter is counted-up and the 384-bit display data,
corresponding to this line address, is latched into the data latch circuit. And at the falling edge of the CL
signal, this latched data output on the segment drivers. Read out timing of the display data, from DDRAM
to the latch circuits is completely independent of the access timing to the MPU. For this reason, the MPU
can access to the LSI regardless of an internal operation.
(15) LCD alternate signal (FR) and LCD synchronous signal (FLM)
The FR and FLM signals are created from the CL signal. The FR signal is used to alternate the crystal
polarization on a LCD panel. It is programmed that the FR signal is toggle on every frame in the default
setting or once every N lines in the N-line inversion mode. The FLM signal is used to indicate a start line of
a new display frame. It presets an initial display line address of the line counter when the FLM signal
becomes ”1”.
(16) Data latch circuit
The data latch circuit is used temporarily store the display data that will output to the segment drivers.
The display data in this circuit is updated in synchronization of the CL signal.
The “All pixels ON/OFF”, “Display ON/OFF” and “Reverse display ON/OFF” instructions change the
display data in this circuit but do not change the display data of the DDRAM.
(17) Common and segment drivers
The LSI includes 384-segment drivers and 40-common drivers. The common drivers generate the LCD
driving waveforms composed of the VLCD, V1, V4 and VSS in accordance with the FR signal and scanning
data. The segment drivers generate waveforms composed of the VLCD, V2, V3 and VSS in accordance with
the FR signal and display data.
- 37 -
NJU6820
LCD Driving waveforms (In the B&W mode, Reverse display OFF, 1/41 duty)
COM0
41
1
2 3 4 5
41
1
2 3 4 5
41 1
COM1
SEG2
SEG1
SEG0
CL
FLM
FR
COM0
VLCD
V1
V2
V3
V4
VSS
COM1
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
SEG0
VLCD
V1
V2
V3
V4
VSS
SEG1
Fig 8
- 38 -
NJU6820
(18) Oscillator
The oscillator generates internal clocks for the display timing and the voltage booster. Since the LSI has
internal capacitor (C) and resistor (R) for the oscillation, external capacitor and resistor are not usually
required. However, in case that an external resistor is used, the resister is connected between the OSC1
and OSC2 terminals. The external resistor becomes enabled by setting “1” to the “CKS” register of “Data
bus length” instruction. When the internal oscillator is not used, the external clocks with 50% duty cycle
ratio must be input to the OSC1 terminal.
In addition, the feed back resister for the oscillation is varied by programming the “Rf” register of the
“Frequency control” instruction, so that it is possible to optimize the frame frequency for a LCD panel.
Setting examples of the MON (B&W /Gradation) and the PWM (Variable gradation /Fixed gradation) are
described, as follows.
(18-1) Internal oscillation mode (CKS=0)
Symbol
f1
f2
f3
MON
0
0
1
PWM
0
1
*
Display mode
Variable gradation mode
Fixed gradation mode
B&W mode
*: Don’t care
(18-2) External resistor oscillation mode(CKS=1)
The internal clocks must be adjusted to the same frequency as the one in using the internal
oscillation mode, and the “MON” and “PWM” registers must be set as well.
(18-3) External clock input mode (CKS=1)
The external clocks must be adjusted to the same frequency as the one in using the internal
oscillation mode, and the “MON” and “PWM” registers must be set as well.
(19) Power supply circuits
The internal power supply circuits are composed of the voltage booster, the electrical variable resister
(EVR), the voltage regulator, reference voltage generator and the voltage followers.
The condition of the power supply circuits is arranged by programming the “DCON” and “AMPON”
registers on the “Power control” instruction. For this arrangement, same parts of the internal power supply
circuits are activated in using an external power supply, as shown in the following table.
Table 14
DCON
AMPON
Voltage booster
0
0
1
0
1
1
Disable
Disable
Enable
Voltage followers
Voltage regulator
EVR
Disable
Enable
Enable
External voltage
Note
VOUT, VLCD, V1, V2, V3, V4
VOUT
−
1, 3
2, 3
−
Note1) The internal power circuits are not used. The external VOUT is required and the C1+, C1-, C2+, C2-,
C3+, C3-, C4+, C4-, VOUT, VREF, VREG and VEE terminals must be open.
Note2) The internal power circuits except the voltage booster are used. The external VOUT is required and
the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4- and VEE terminals must be open. The reference voltage
is required to VREF terminal.
Note3) The relation among the voltages should be maintained as follows.
VOUT ≥ VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
- 39 -
NJU6820
(20) Voltage booster
The voltage booster generates maximum 5x voltage of the VEE level. It is programmed so that the boost
level is selected out of 1x, 2x, 3x, 4x, and 5x by the “Boost level select” instruction. The boosted voltage
VOUT must not exceed beyond the value of 18.0V, otherwise the voltage stress may cause a permanent
damage to the LSI.
Boosted voltages
VOUT=15V
VOUT=9V
VEE=3V
VEE=3V
VSS=0V
VSS=0V
5-time boost
3-time boost
Capacitor connections for the voltage Booster
5-time boost
C1+
C1C2+
C2C3+
C3C4+
C4VOUT
VSS
4-time boost
C1+
C1C2+
C2C3+
C3C4+
C4-
+
+
+
+
VOUT
VSS
+
3-time boost
C1+
C1C2+
C2C3+
C3C4+
C4VOUT
VSS
+
+
+
2-time boost
C1+
C1C2+
C2C3+
C3C4+
C4-
+
+
VOUT
VSS
+
Fig 9
- 40 -
+
+
+
NJU6820
(21) Reference voltage generator
The reference voltage generator is used to produce the reference voltage (VBA), which is output from the
VBA terminal and should be input to the VREF terminal.
VBA = VEE x 0.9
(22) Voltage regulator
The voltage regulator, composed of the gain control circuit and an operational amplifier, and is used to
gain the reference voltage (VREF) and to create the regulated voltage (VREG). The VREG is used as an input
voltage to the EVR circuits, which is programmed by the “VU” register of the “Boost level” instruction.
VREG = VREF x N
(N: register value for the boost level)
(23) Electrical variable resister (EVR)
The EVR, variable within 128-step, and is used to fine-tune the LCD driving voltage (VLCD) by
programming the “DV” register in the “EVR control” instruction, so that it is possible to optimize the
contrast level for a LCD panels.
VLCD = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127 (M: register value for the EVR)
(24) LCD driving voltage generation circuit
LCD driving voltage generation circuit generates the VLCD voltage levels as VLCD, V1, V2, V3 and V4 with
internal E.V.R and the Bleeder resistors. The bias ratio of LCD driving voltage can be selected out of 1/4,
1/5, 1/6, 1/7 and 1/8.
In using the internal power supply, the capacitors CA2 must be connected to the VLCD, V1, V2, V3 and V4
terminals, and the CA2 value must be determined by the evaluation with actual LCD modules.
In using the external power supply, the external LCD driving voltages such as the VLCD, V1, V2, V3 and
V4 are supplied and the internal power supply circuits must be set to “OFF” by DCON = AMPON = "0". In
this mode, voltage booster terminals such as C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, VEE, VREF and VREG
must be opened.
In case that the voltage booster is not used but only some parts of internal power supply circuits
(Voltage followers, Voltage regulator and EVR) are used, the C1+, C1-, C2+, C2-, C3+, C3-, C4+ and C4terminals must be opened. And, the external power supply is input to the VOUT terminal, and the reference
voltage to the VREF terminal. The capacitor CA3 must connect to the VREG terminal for voltage stabilization.
- 41 -
NJU6820
Connections of the capacitor for the voltage booster
Using all of the internal power supply circuits
(5-time boost)
VDD
VDD
VDD
CA1
VEE
CA1
CA3
VSS
Using only external power supply circuits
CA3
VSS
VBA
VBA
VREF
VREF
VREG
VREG
C1-
C1-
CA1
C1+
C1+
C2-
C2-
CA1
C2+
C2+
C3-
C3-
CA1
C3+
C3+
C4-
CA1
C4+
C4C4+
NJU6820
NJU6820
VOUT
CA1
VSS
CA1
CA2
CA2
CA2
CA2
VSS
VDD
VEE
CA2
VLCD
VLCD
VOUT
VLCD
V1
V3
V1
External
Power V2
circuit
V3
V4
V4
V4
V1
V2
Fig 10
Reference values
1.0 to 4.7uF
CA1
CA2
1.0 to 2.2uF
CA3
0.1uF
V2
V3
CA2
CA2
CA2
Fig11
CA2
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s
operation and display quality. To minimize this impact, use the shortest possible wires and place
the capacitors to be as close as possible to the LSI.
- 42 -
NJU6820
Using internal power supply circuit
Without the reference voltage generator(2)
(5-time boost)
Using internal power supply circuits
Without the reference voltage generator(1)
(5-time boost)
VDD
VEE
CA1
VBA
VREF
VREF
Thermistor
VBA
C1-
CA1
CA3
VSS
CA1
C1+
C2-
CA1
CA1
C2+
C3-
CA1
CA1
C3+
C4-
CA1
C4+
CA2
CA2
CA2
CA2
CA2
CA1
NJU6820
VOUT
CA1
VSS
VDD
VEE
CA1
VREG
CA3
VSS
VSS
VDD
VDD
CA1
VSS
VREG
C1C1+
C2C2+
C3C3+
C4-
VOUT
VLCD
CA2 VLCD
V1
CA2 V1
V2
CA2 V2
V3
CA2 V3
V4
VSS
Fig 12
NJU6820
C4+
CA2 V4
Fig 13
Reference value
CA1
1.0 to 4.7µF
CA2
1.0 to 2.2µF
CA3
0.1µF
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s
operation and display quality. To minimize this impact, use the shortest possible wires and place
the capacitors to be as close as possible to the LSI.
- 43 -
NJU6820
Using internal power supply circuits
Without the voltage booster
VDD
VDD
VEE
CA1
VBA
CA3
VSS
VREF
CA3
VREG
VSS
C1C1+
C2C2+
C3C3+
C4C4+
External
power
circuit
CA1
CA2
CA2
CA2
NJU6820
VOUT
VLCD
V1
V2
CA2 V3
VSS
CA2 V4
Fig 14
Reference value
CA1
1.0 to 4.7µF
CA2
1.0 to 2.2µF
CA3
0.1µF
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s
operation and display quality. To minimize this impact, use the shortest possible wires and place
the capacitors to be as close as possible to the LSI.
- 44 -
NJU6820
(25) Partial display function
The partial display function is used to partially specify some parts of display area on LCD panels. By
using this function, LCD modules can work in lower duty cycle ratio, lower LCD bias ratio, lower boost
level and lower LCD driving voltage. It is usually used to display a time and calendar, and is also used to
optimize the LSI condition in accordance with the display size. It can be programmed to select the duty
cycle ratio (1/5, 1/9, 1/13, 1/17, 1/21, 1/25, 1/29, 1/33, 1/37, 1/41 in case “DSE” is “0”), the LCD bias ratio,
the boost level and the EVR value by the instructions.
Partial display image
NJRC
LCD DRIVER
Low Power and
Low Voltage
LCD DRIVER
Normal display
Partial display
Partial display sequence
Optional status
Display OFF (ON/OFF=”0”)
Internal Power supply OFF (DCON=”0”, AMPON=”0”)
WAIT
Setting for LCD driving voltage-related functions
- Boost level
- EVR value
- LCD bias ratio
Internal Power supply ON (DCON=”1”, AMPON=”1”)
WAIT
Setting for display-related functions
- Duty cycle ratio
- Initial display line
- Initial COM line
- Other instructions
Display ON (ON/OFF =”1”)
Partial display Status
- 45 -
NJU6820
(26) Discharge circuit
Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and VLCD
terminals. This circuit is activated by setting “0” to the “DIS” register of the “Discharge” instruction or by
setting “RESb” terminal to ”0” level. The “Discharge ON/OFF” instruction is usually required just after the
internal power supply is turned off by setting “0” into the “DCON” and “AMPON” registers, or just after the
external power supply is turned off. During the discharge operation, the internal or external power supply
must not be turned on.
(27) Reset circuit
The reset circuit initializes the LSI into the following default status. It is activated by setting the RESb
terminal to “0”. The RESB terminal is usually required to connect to MPU reset terminal in order that the
LSI can be initialized at the same timing of the MPU.
●
Default status
1. DDRAM display data
2. column address
3. row address
4. Initial display line
5. Display ON/OFF
6. Reverse display ON/OFF
7. Duty cycle ratio
8. N-line Inversion ON/OFF
9. COM scan direction
10. Increment mode
11. Reverse SEG direction
12. SWAP mode
13. EVR value
14. Internal power supply
15. Display mode
16. LCD bias ratio
17. Gradation Palette 0
18. Gradation Palette 1
19. Gradation Palette 2
20. Gradation Palette 3
21. Gradation Palette 4
22. Gradation Palette 5
23. Gradation Palette 6
24. Gradation Palette 7
25. Gradation Palette 8
26. Gradation Palette 9
27. Gradation Palette 10
28. Gradation Palette 11
29. Gradation Palette 12
30. Gradation Palette 13
31. Gradation Palette 14
32. Gradation Palette 15
33. Gradation mode control
34. Data bus length
35. Discharge circuit
- 46 -
:Undefined
:(00)H
:(00)H
:(0)H (1st line)
:OFF
:OFF (normal)
:1/41 duty(DSE=0)
:OFF
:COM0 → COM39
:OFF
:OFF (normal)
:OFF (normal)
:(0, 0, 0, 0, 0, 0, 0)
:OFF
:Gradation display mode
:1/8 bias
:(0, 0, 0, 0, 0)
:(0, 0, 0, 1, 1)
:(0, 0, 1, 0, 1)
:(0, 0, 1, 1, 1)
:(0, 1, 0, 0, 1)
:(0, 1, 0, 1, 1)
:(0, 1, 1, 0, 1)
:(0, 1, 1, 1, 1)
:(1, 0, 0, 0, 1)
:(1, 0, 0, 1, 1)
:(1, 0, 1, 0, 1)
:(1, 0, 1, 1, 1)
:(1, 1, 0, 0, 1)
:(1, 1, 0, 1, 1)
:(1, 1, 1, 0, 1)
:(1, 1, 1, 1, 1)
:Variable gradation mode
:8-bit data bus length
:(DIS/DIS2) : ”0”
NJU6820
(28) Power supply ON/OFF sequences
The following paragraphs describe power supply ON/OFF sequences, which are to protect the LSI from
over current.
(28-1) Using an external power supply
# Power supply ON sequence
Logic voltage (VDD) must be always input first, and next the LCD driving voltages (V1 to V4 and
VLCD) are turned on. In using the external VOUT, the VDD must be input first, next the reset
operation must be performed, and finally the VOUT can be input.
# Power supply OFF sequence
Either the reset operation, cutting off the V1 to V4 and VLCD from the LSI by the RESb terminal
or the “Power control” instruction must be performed first, and next the VDD is turned off. It is
recommended that a series-resister between 50 Ω and 100 Ω is added on the VLCD line (or VOUT
line in using only the external VOUT voltage) in order to protect the LSI from the over current.
(28-2) Using the internal power supply circuits
# Power supply ON sequence
The VDD must be input first, next the reset operation must be performed, and finally the V1 to
V4 and VLCD can be turned on by setting “1” to the “DCON” and “AMPON” registers of the “Power
control” instruction.
# Power supply OFF sequence
Either the reset operation by the RESb terminal or the “Power control” instruction must be
performed first, and next the input voltage for the voltage booster (VEE) and the VDD can be
turned off. If the VEE is supplied from different power sources for VDD, the VEE is turned off first,
and next the VDD is turned off.
- 47 -
NJU6820
(29) Referential instruction sequences
(29-1) Initialization in using the internal power supply circuits
VDD, VEE power ON
Wait for power-ON stabilization
RESET Input
WAIT
Setting for LCD driving voltage-related functions
- EVR value
- LCD bias ratio
- Power control (DCON=”1”, AMPON=”1”)
End of initialization
(29-2) Display data writing
End of Initialization
Setting for display-related functions
- Initial display line
- Increment mode
- column address
- row address
Display data write
Display ON (ON/OFF =”1”)
(29-3) Power OFF
Optional status
Power save or reset operation
Discharge ON
WAIT
VEE, VDD power OFF
- 48 -
- All COM/SEG output VSS level.
NJU6820
(30) Instruction table
Instruction Table (1)
Code (80 series MPU I/F)
Instructions
Code
CSb RS RDb WRb RE2 RE1 RE0 D7
D6
D5
D4
Functions
D3
D2
D1
D0
Display data write
0
0
1
0
0/1 0/1 0/1
Write Data
Write display data to DDRAM
Display data read
0
0
0
1
0/1 0/1 0/1
Read Data
Read display data from DDRAM
column address
(Lower) [0H]
0
1
1
0
0
0
0
0
0
0
0
AX3
AX2
AX1
AX0
DDRAM column address
column address
(Upper) [1H]
0
1
1
0
0
0
0
0
0
0
1
AX7
AX6
AX5
AX4
DDRAM column address
row address
(Lower) [2H]
0
1
1
0
0
0
0
0
0
1
0
AY3
AY2
AY1
AY0
DDRAM row address
row address
(Upper) [3H]
0
1
1
0
0
0
0
0
0
1
1
*
*
AY5
AY4
DDRAM row address
Initial display line
(Lower) [4H]
0
1
1
0
0
0
0
0
1
0
0
LA3
LA2
LA1
LA0
Row address for an initial COM line
(Scan start line)
Initial display line
(Upper) [5H]
0
1
1
0
0
0
0
0
1
0
1
*
*
LA5
LA4
Row address for an initial COM line
(Scan start line)
N-line inversion
(Lower) [6H]
0
1
1
0
0
0
0
0
1
1
0
N3
N2
N1
N0
The number of N-line inversion
N-line inversion
(Upper) [7H]
0
1
1
0
0
0
0
0
1
1
1
*
*
N5
N4
The number of N-line inversion
0
1
1
0
0
0
0
1
0
0
0
SHIFT: Common direction
Display control (1)
[8H]
Display control (2)
[9H]
Increment control
[AH]
Power control
[BH]
Duty cycle ratio
[CH]
Boost level
[DH]
LCD bias ratio
[EH]
RE register
[FH]
Note 1)
Note 2)
Note 3)
SHIFT MON
ALL
ON
ON/ MON: Gradation or B/W display mode
OFF ALLON: All pixels ON/OFF
ON/OFF: Display ON/OFF
REV: Reverse display ON/OFF
NLIN: N-line inversion ON/OFF,
NLIN SWAP REF
SWAP: SWAP mode ON/OFF
REF: Segment direction
WIN: Window addressing mode ON/OFF
AIM: Read-modify-write ON/OFF
AIM
AYI
AXI AYI: Row auto-increment mode ON/OFF
AXI: column auto-increment mode
ON/OFF
AMPON: Voltage followers ON/OFF
HALT: Power save ON/OFF
DC
HALT
ACL
ON
DCON: Voltage booster ON/OFF
ACL: Reset
0
1
1
0
0
0
0
1
0
0
1
REV
0
1
1
0
0
0
0
1
0
1
0
WIN
0
1
1
0
0
0
0
1
0
1
1
AMP
ON
0
1
1
0
0
0
0
1
1
0
0
DS3
DS2
DS1
DS0
Sets LCD duty cycle ratio
0
1
1
0
0
0
0
1
1
0
1
*
VU2
VU1
VU0
Sets boost level
0
1
1
0
0
0
0
1
1
1
0
*
B2
B1
B0
0
1
1
0
1
1
1
1
TST0
RE2
RE1
0/1 0/1 0/1
Sets LCD bias ratio
RE0 RE flag set
*
: Don’t care.
[ NH ] : Address of instruction register
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of
the upper and lower bytes are set.
- 49 -
NJU6820
Instruction Table (2)
Code (80 series MPU I/F)
Instructions
Code
CSb RS RDb WRb RE2 RE1 RE0
D7
D6
D5
D4
Gradation palette A0/A8
(Lower) [0H]
0
1
1
0
0
0
1
0
0
0
0
Gradation palette A0/A8
(Upper) [1H]
0
1
1
0
0
0
1
0
0
0
1
Gradation palette A1/A9
(Lower) [2H]
0
1
1
0
0
0
1
0
0
1
0
Gradation palette A1/A9
(Upper) [3H]
0
1
1
0
0
0
1
0
0
1
1
Gradation palette A2/A10
(Lower) [4H]
0
1
1
0
0
0
1
0
1
0
0
Gradation palette A2/A10
(Upper) [5H]
0
1
1
0
0
0
1
0
1
0
1
Gradation palette A3/A11
(Lower) [6H]
0
1
1
0
0
0
1
0
1
1
0
Gradation palette A3/A11
(Upper) [7H]
0
1
1
0
0
0
1
0
1
1
1
Gradation palette A4/A12
(Lower) [8H]
0
1
1
0
0
0
1
1
0
0
0
Gradation palette A4/A12
(Upper) [9H]
0
1
1
0
0
0
1
1
0
0
1
Gradation palette A5/A13
(Lower) [AH]
0
1
1
0
0
0
1
1
0
1
0
Gradation palette A5/A13
(Upper) [BH]
0
1
1
0
0
0
1
1
0
1
1
Gradation palette A6/A14
(Lower) [CH]
0
1
1
0
0
0
1
1
1
0
0
Gradation palette A6/A14
(Upper) [DH]
0
1
1
0
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
RE register
[FH]
Note 1)
Note 2)
Note 3)
- 50 -
0/1 0/1 0/1
D3
Functions
D2
D1
D0
PA03/ PA02/ PA01/ PA00/
PA83 PA82 PA81 PA80
Sets palette values to gradation
palette A0(PS=0)/A8(PS=1)
*
PA04/
PA84
Sets palette values to gradation
palette A0(PS=0)/A8(PS=1)
PA11/
PA91
PA10/
PA90
Sets palette values to gradation
palette A1(PS=0)/A9(PS=1)
*
PA14/
PA94
Sets palette values to gradation
palette A1(PS=0)/A9(PS=1)
PA23/ PA22/ PA21/ PA20/
PA103 PA102 PA101 PA100
Sets palette values to gradation
palette A2(PS=0)/A10(PS=1)
PA24/
PA104
Sets palette values to gradation
palette A2(PS=0)/A10(PS=1)
PA33/ PA32/ PA31/ PA30/
PA113 PA112 PA111 PA110
Sets palette values to gradation
palette A3(PS=0)/A11(PS=1)
PA34/
PA114
Sets palette values to gradation
palette A3(PS=0)/A11(PS=1)
PA43/ PA42/ PA41/ PA40/
PA123 PA122 PA121 PA120
Sets palette values to gradation
palette A4(PS=0)/A12(PS=1)
PA44/
PA124
Sets palette values to gradation
palette A4(PS=0)/A12(PS=1)
PA53/ PA52/ PA51/ PA50/
PA133 PA132 PA131 PA130
Sets palette values to gradation
palette A5(PS=0)/A13(PS=1)
PA54/
PA134
Sets palette values to gradation
palette A5(PS=0)/A13(PS=1)
PA63/ PA62/ PA61/ PA60/
PA143 PA142 PA141 PA140
Sets palette values to gradation
palette A6(PS=0)/A14(PS=1)
PA64/
PA144
Sets palette values to gradation
palette A6(PS=0)/A14(PS=1)
*
*
PA13/ PA12/
PA93 PA92
*
*
*
*
*
*
*
*
*
*
*
*
TST0 RE2
*
*
*
*
*
RE1
RE0 RE flag set
*
: Don’t care.
[ NH ] : Address of Instruction register
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of
the upper and lower bytes are set.
NJU6820
Instruction Table (3)
Code (80 series MPU I/F)
Instructions
Code
CSb RS RDb WRb RE2 RE1 RE0
D7
D6
D5
D4
Gradation palette A7/A15
(Lower) [0H]
0
1
1
0
0
1
0
0
0
0
0
Gradation palette A7/A15
(Upper) [1H]
0
1
1
0
0
1
0
0
0
0
1
Gradation palette B0/B8
(Lower) [2H]
0
1
1
0
0
1
0
0
0
1
0
Gradation palette B0/B8
(Upper) [3H]
0
1
1
0
0
1
0
0
0
1
1
Gradation palette B1/B9
(Lower) [4H]
0
1
1
0
0
1
0
0
1
0
0
Gradation palette B1/B9
(Upper) [5H]
0
1
1
0
0
1
0
0
1
0
1
Gradation palette B2/B10
(Lower) [6H]
0
1
1
0
0
1
0
0
1
1
0
Gradation palette B2/B10
(Upper) [7H]
0
1
1
0
0
1
0
0
1
1
1
Gradation palette B3/B11
(Lower) [8H]
0
1
1
0
0
1
0
1
0
0
0
Gradation palette B3/B11
(Upper) [9H]
0
1
1
0
0
1
0
1
0
0
1
Gradation palette B4/B12
(Lower) [AH]
0
1
1
0
0
1
0
1
0
1
0
Gradation palette B4/B12
(Upper) [BH]
0
1
1
0
0
1
0
1
0
1
1
Gradation palette B5/B13
(Lower) [CH]
0
1
1
0
0
1
0
1
1
0
0
Gradation palette B5/B13
(Upper) [DH]
0
1
1
0
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
RE register
[FH]
Note 1)
Note 2)
Note 3)
0/1 0/1 0/1
D3
Functions
D2
D1
D0
PA73/ PA72/ PA71/ PA70/
PA153 PA152 PA151 PA150
Sets palette values to gradation
palette A7(PS=0)/A15(PS=1)
PA74/
PA154
Sets palette values to gradation
palette A7(PS=0)/A15(PS=1)
PB03/ PB02/ PB01/ PB00/
PB83 PB82 PB81 PB80
Sets palette values to gradation
palette B0(PS=0)/B8(PS=1)
PB04/
PB84
Sets palette values to gradation
palette B0(PS=0)/B8(PS=1)
PB13/ PB12/ PB11/ PB10/
PB93 PB92 PB91 PB90
Sets palette values to gradation
palette B1(PS=0)/B9(PS=1)
PB14/
PB94
Sets palette values to gradation
palette B1(PS=0)/B9(PS=1)
PB23/ PB22/ PB21/ PB20/
PB103 PB102 PB101 PB100
Sets palette values to gradation
palette B2(PS=0)/B10(PS=1)
PB24/
PB104
Sets palette values to gradation
palette B2(PS=0)/B10(PS=1)
PB33/ PB32/ PB31/ PB30/
PB113 PB112 PB111 PB110
Sets palette values to gradation
palette B3(PS=0)/B11(PS=1)
PB34/
PB114
Sets palette values to gradation
palette B3(PS=0)/B11(PS=1)
PB43/ PB42/ PB41/ PB40/
PB123 PB122 PB121 PB120
Sets palette values to gradation
palette B4(PS=0)/B12(PS=1)
PB44/
PB124
Sets palette values to gradation
palette B4(PS=0)/B12(PS=1)
PB53/ PB52/ PB51/ PB50/
PB133 PB132 PB131 PB130
Sets palette values to gradation
palette B5(PS=0)/B13(PS=1)
PB54/
PB134
Sets palette values to gradation
palette B5(PS=0)/B13(PS=1)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
TST0 RE2
*
*
*
*
*
*
*
RE1
RE0 RE flag set
*
: Don’t care.
[ NH ] : Address of Instruction register
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of
the upper and lower bytes are set.
- 51 -
NJU6820
Instruction Table (4)
Code (80 series MPU I/F)
Instructions
Code
CSb RS RDb WRb RE2 RE1 RE0
D7
D6
D5
D4
D3
Functions
D2
Gradation palette B6/B14
(Lower) [0H]
0
1
1
0
0
1
1
0
0
0
0
Gradation palette B6/B14
(Upper) [1H]
0
1
1
0
0
1
1
0
0
0
1
Gradation palette B7/B15
(Lower) [2H]
0
1
1
0
0
1
1
0
0
1
0
Gradation palette B7/B15
(Upper) [3H]
0
1
1
0
0
1
1
0
0
1
1
*
*
Gradation palette C0/C8
(Lower) [4H]
0
1
1
0
0
1
1
0
1
0
0
PC03/
PC83
Gradation palette C0/C8
(Upper) [5H]
0
1
1
0
0
1
1
0
1
0
1
Gradation palette C1/C9
(Lower) [6H]
0
1
1
0
0
1
1
0
1
1
Gradation palette C1/C9
(Upper) [7H]
0
1
1
0
0
1
1
0
1
Gradation palette C2/C10
(Lower) [8H]
0
1
1
0
0
1
1
1
Gradation palette C2/C10
(Upper) [9H]
0
1
1
0
0
1
1
Gradation palette C3/C11
(Lower) [AH]
0
1
1
0
0
1
Gradation palette C3/C11
(Upper) [BH]
0
1
1
0
0
Gradation palette C4/C12
(Lower) [CH]
0
1
1
0
Gradation palette C4/C12
(Upper) [DH]
0
1
1
0
0
1
1
0
RE register
[FH]
Note 1)
Note 2)
Note 3)
- 52 -
D1
D0
PB63/ PB62/ PB61/ PB60/
PB143 PB142 PB141 PB140
Sets palette values to gradation
palette B6(PS=0)/B14(PS=1)
PB64/
PB144
Sets palette values to gradation
palette B6(PS=0)/B14(PS=1)
PB73/ PB72/ PB71/ PB70/
PB153 PB152 PB151 PB150
Sets palette values to gradation
palette B7(PS=0)/B15(PS=1)
*
PB74/
PB154
Sets palette values to gradation
palette B7(PS=0)/B15(PS=1)
PC02/
PC82
PC01/
PC81
PC00/
PC80
Sets palette values to gradation
palette C0(PS=0)/C8(PS=1)
*
*
*
PC04/
PC84
Sets palette values to gradation
palette C0(PS=0)/C8(PS=1)
0
PC13/
PC93
PC12/
PC92
PC11/
PC91
PC10/
PC90
Sets palette values to gradation
palette C1(PS=0)/C9(PS=1)
1
1
*
*
*
PC14/
PC94
Sets palette values to gradation
palette C1(PS=0)/C9(PS=1)
0
0
0
PC23/ PC22/ PC21/ PC20/
PC103 PC102 PC101 PC100
Sets palette values to gradation
palette C2(PS=0)/C10(PS=1)
1
0
0
1
PC24/
PC104
Sets palette values to gradation
palette C2(PS=0)/C10(PS=1)
1
1
0
1
0
PC33/ PC32/ PC31/ PC30/
PC113 PC112 PC111 PC110
Sets palette values to gradation
palette C3(PS=0)/C11(PS=1)
1
1
1
0
1
1
PC34/
PC114
Sets palette values to gradation
palette C3(PS=0)/C11(PS=1)
0
1
1
1
1
0
0
PC43/ PC42/ PC41/ PC40/
PC123 PC122 PC121 PC120
Sets palette values to gradation
palette C4(PS=0)/C12(PS=1)
0
1
1
1
1
0
1
PC44/
PC124
Sets palette values to gradation
palette C4(PS=0)/C12(PS=1)
1
1
1
1
0/1 0/1 0/1
*
*
*
*
*
*
*
*
TST0 RE2
*
*
*
*
RE1
RE0 RE flag set
*
: Don’t care.
[ NH ] : Address of Instruction register
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of
the upper and lower bytes are set.
NJU6820
Instruction Table (5)
Code (80 series MPU I/F)
Instructions
Code
CSb RS RDb WRb RE2 RE1 RE0
D7
D6
D5
D4
Functions
D3
D2
D1
D0
Gradation palette C5/C13
(Lower) [0H]
0
1
1
0
1
0
0
0
0
0
0
Gradation palette C5/C13
(Upper) [1H]
0
1
1
0
1
0
0
0
0
0
1
Gradation palette C6/C14
(Lower) [2H]
0
1
1
0
1
0
0
0
0
1
0
Gradation palette C6/C14
(Upper) [3H]
0
1
1
0
1
0
0
0
0
1
1
Gradation palette C7/C15
(Lower) [4H]
0
1
1
0
1
0
0
0
1
0
0
Gradation palette C7/C15
(Upper) [5H]
0
1
1
0
1
0
0
0
1
0
1
*
*
0
1
1
0
1
0
0
0
1
1
0
SC3
SC2
Display control Signal/
Duty Select
[7H]
0
1
1
0
1
0
0
0
1
1
1
*
*
Gradation mode control
[8H]
0
1
1
0
1
0
0
1
0
0
0
PWM C256
0
1
1
0
1
0
0
1
0
0
1
HSW
ABS CKS
WLS
HSW : High speed access ON/OFF
ABS : ABS mode ON/OFF
CKS : Internal/external oscilation
WLS : Display data Length
EVR control
(Lower) [AH]
0
1
1
0
1
0
0
1
0
1
0
DV3
DV2
DV1
DV0
Sets EVR level
(Lower bit)
EVR control
(Upper) [BH]
0
1
1
0
1
0
0
1
0
1
1
*
DV6
DV5
DV4
Sets EVR level
(Upper bit)
0
1
1
0
1
0
0
1
1
0
1
*
RF2
RF1
RF0
Oscillation frequency
0
1
1
0
1
0
0
1
1
1
0
*
*
0
1
1
0
1
1
1
1
0
1
1
0
1
1
0
0
Reading address
Sets instruction register address
0
1
0
1
*
*
*
*
Read Data
Read out instruction register data
Initial COM line
[6H]
Data bus length
[9H]
Frequency control
[DH]
Discharge ON/OFF
[EH]
RE register
[FH]
Instruction register address
[CH]
Instruction register read
0/1 0/1 0/1
1
0
0
0/1 0/1 0/1
PC53/ PC52/ PC51/ PC50/
PC133 PC132 PC131 PC130
Sets palette values to gradation
palette C5(PS=0)/C13(PS=1)
PC54/
PC134
Sets palette values to gradation
palette C5(PS=0)/C13(PS=1)
PC63/P PC62/ PC61/ PC60/
C143 PC142 PC141 PC140
Sets palette values to gradation
palette C6(PS=0)/C14(PS=1)
PC64/
PC144
Sets palette values to gradation
palette C6(PS=0)/C14(PS=1)
PC73/ PC72/ PC71/ PC70/
PC153 PC152 PC151 PC150
Sets palette values to gradation
palette C7(PS=0)/C15(PS=1)
*
PC74/
PC154
Sets palette values to gradation
palette C7(PS=0)/C15(PS=1)
SC1
SC0
*
*
*
*
TST0 RE2
*
*
DSE SON
*
*
DIS2 DIS
RE1
Sets scan-starting common driver
SON : Display clock ON/OFF
DSE : Duty-1 ON/OFF
PWM : Variable/Fixed gradation
mode
C256 : 256-Color Mode ON/OFF
Discharge the electric charge in
capacitors on V1 to V4 and VLCD
RE0 RE flag
Note 1)
Note 2)
Note 3)
*
: Don’t care.
[ NH ] : Address of Instruction register
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of
the upper and lower bytes are set.
Note 4)
CKS=0: Internal oscillation mode (default)
CKS=1: External oscillation mode
- 53 -
NJU6820
Instruction Table (6)
Code (80 series MPU I/F)
Instructions
Code
CSb RS RDb WRb RE2 RE1 RE0
Window end
column address
(Lower) [0H]
Window end
column address
(Upper) [1H]
Functions
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
1
0
0
0
0
EX3
EX2
EX1
EX0
Sets column address for end point
0
1
1
0
1
0
1
0
0
0
1
EX7
EX6
EX5
EX4
Sets column address for end point
Window end row address
(Lower) [2H]
0
1
1
0
1
0
1
0
0
1
0
EY3
EY2
EY1
EY0
Sets row address for end point
Window end row address
(Upper) [3H]
0
1
1
0
1
0
1
0
0
1
1
*
*
EY5
EY4
Sets row address for end point
Initial reverse line
(Lower) [4H]
0
1
1
0
1
0
1
0
1
0
0
LS3
LS2
LS1
LS0
Sets address for reverse line
Initial reverse line
(Upper) [5H]
0
1
1
0
1
0
1
0
1
0
1
*
*
LS5
LS4
Sets address for reverse line
Last reverse line
(Lower) [6H]
0
1
1
0
1
0
1
0
1
1
0
LE3
LE2
LE1
LE0
Sets address for reverse line
Last reverse line
(Upper) [7H]
0
1
1
0
1
0
1
0
1
1
1
*
*
LE5
LE4
Sets address for reverse line
0
1
1
0
1
0
1
1
0
0
0
*
*
BT
LREV
1
1
0
1
0
1
1
0
0
1
*
*
*
PS
0
1
1
0
1
0
1
1
0
1
0
PWM PWM PWM PWM
S
A
B
C
0
1
1
0
1
1
1
1
TST0 RE2
Reverse line display
ON/OFF
[8H]
Gradation palette setting
control / Icon SEG
address
set
[9H]
PWM control
[AH]
RE register
[FH]
Note 1)
Note 2)
Note 3)
- 54 -
0
0/1 0/1 0/1
RE1
BT : Blink type setting
LREV : Reverse line display ON/OFF
PS : gradation setting
Sets PWM mode
RE0 RE flag
*
: Don’t care.
[ NH ] : Address of Instruction register
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of
the upper and lower bytes are set.
NJU6820
(31) Instruction descriptions
This chapter provides detail descriptions and instruction registers. Nonexistent instruction codes must
not be set into the LSI.
(31-1) Display data write
The “Display data write” instruction is used to write 8-bit display data into the DDRAM.
CSB
RS
0
0
RDb WRb RE2
1
0
0/1
RE1
RE0
0/1
0/1
D7
D6
D5
D4
D3
D2
D1
D0
Display data
(31-2) Display data read
The “Display data read” instruction is used to read out 8-bit display data from the DDRAM, where
the column address and row address must be specified beforehand by the “column address” and
“row address” instructions. The dummy read is required just after the “column address” and “row
address” instructions.
CSB
RS
0
0
RDb WRb
0
1
RE2
RE1
RE0
0/1
0/1
0/1
D7
D6
D5
D4
D3
D2
D1
D0
Display data
(31-3) Column address
The “column address” instruction is used to specify the column address for the display data’s
reading and writing operations. It requires dual bytes for lower 4-bit and upper 4-bit data. The
instruction for the lower 4-bit data must be executed first, next the instruction for the upper 4-bit.
CSB
RS
RDb WRb
0
1
1
CSB
RS
RDb
0
1
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
AX3
AX2
AX1
AX0
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
AX7
AX6
AX5
AX4
WRb RE2
0
0
(31-4) Row address
The “row address” instruction is used to specify the row address for the display data read and write
operations. It requires dual bytes for lower 4-bit and upper 2-bit data. The instruction for the lower 4bit data must be executed first, next the instruction for upper 2-bit. The row address is specified in
between 00H and 27H. The setting for nonexistent row address between 28H and 3FH is prohibited.
CSb
RS
RDb WRb
0
1
1
CSb
RS
RDb
0
1
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
AY3
AY2
AY1
AY0
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
*
*
AY5
AY4
WRb RE2
0
0
- 55 -
NJU6820
(31-5) Initial display line
The “Initial display line” instruction is used to specify the line address corresponding to the initial
COM line. The initial COM line specified by the “Initial COM line” instruction and indicates the
common driver that starts scanning data.
CSb
RS
RDb WRb
0
1
1
CSb
RS
RDb
0
1
1
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
0
0
LA3
LA2
LA1
LA0
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
1
*
*
LA5
LA4
0
WRb RE2
0
0
LA5
LA4
LA3
LA2
LA1
LA0
Line Address
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
1
0
:
:
0
1
1
1
39
(31-6) N-line inversion
The “N-line inversion” instruction is used to control the alternate rates of the liquid crystal direction.
It is programmed to select the N value between 2 and 39, and the FR signal toggles once every N
lines by setting “1” into the “NLIN” register of the “Display control (2)” instruction. When the N-line
inversion is disabled by setting “0” into the “NLIN” register, the FR signal toggles by the frame.
CSb
RS
RDb
0
1
1
CSb
RS
0
1
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
0
N3
N2
N1
N0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
*
*
N5
N4
WRb RE2
0
RDb WRb
1
0
LA5
LA4
LA3
LA2
LA1
LA0
N value
0
0
0
0
0
0
Inhibited*
0
0
0
0
0
1
2
:
:
1
- 56 -
0
0
:
:
1
1
0
39
NJU6820
! N-line Inversion Timing (1/41 duty cycle ratio)
N-line inversion OFF
1st line
3rd line
40th line
2nd line
1st line
41th line
CL
FLM
FR
N-line inversion ON
N-line control
1st line
3rd line
N line
2nd line
2nd line
1st line
CL
FR
(31-7) Display control (1)
The “Display control (1)” instruction is used to control display conditions by setting the “Display
ON/OFF”, “All pixels ON/OFF”, Display mode” and “Common direction” registers.
CSb
RS
RDb
0
1
1
WRb RE2
0
0
RE1
RE0
D7
D6
D5
D4
D3
D2
0
0
1
0
0
0
SHIFT
MON
D1
D0
ALLON ON/OFF
! ON/OFF register
ON/OFF=0
ON/OFF=1
: Display OFF (All COM/SEG output Vss level.)
: Display ON
! All ON register
The “All pixels ON/OFF” register is used to turn on all pixels without changing display data of
the DDRAM. The setting for the “All pixels ON/OFF” register has a priority over the “Reverse
display ON/OFF” register.
ALLON=0
ALLON=1
: Normal
: All pixels turn on.
! MON register
MON=0
MON=1
: Gradation mode
: B&W mode
! SHIFT register
SHIFT=0
SHIFT=1
: COM0 → COM39
: COM39 → COM0
- 57 -
NJU6820
(31-8) Display control (2)
The “Display control (2)” instruction is used to control display conditions by setting “Segment
direction”, “SWAP mode ON/OFF”, “N-line inversion ON/OFF” and “Reverse display ON/OFF”
registers.
CSb
RS
RDb
WRb
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
0
1
0
0
1
REV
NLIN
SWAP
REF
# REF register
The “REF” register is used to reverse the assignment between segment drivers and column
address, and it is possible to reduce restrictions for placement of the LSI on the LCD modules.
For more information, see (10) “The relation among the DDRAM column address, display data
and segment drivers”.
# SWAP register
The “SWAP” register is used to reverse the arrangement of the display data in the DDRAM.
SWAP=0
SWAP=1
: SWAP mode OFF
: SWAP mode ON
(Normal)
SWAP=”0”
SWAP=”1”
Write data
D7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
D7 D6 D5 D4 D3 D2 D1 D0
RAM data
D7 d6 d5 d4 d3 d2 d1 d0
d0 d1 d2 d3 d4 d5 d6 d7
Read data
D 7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
# NLIN register
The “NLIN” is used to enable or disable the N-line inversion.
NLIN=0
NLIN=1
: N-line inversion OFF
: N-line inversion ON
(The FR signal toggles by the flame.)
(The FR signal toggles once every N frames.)
# REV register
The “REV” register is used to enable or disable the reverse display mode that reverses the
polarity of the display data without changing the display data of the DDRAM.
REV=0
REV=1
- 58 -
: Reverse display mode OFF
: Reverse display mode ON
REV
Display
0
Normal
1
Reverse
DDRAM data → Display data
0
0
1
1
0
1
1
0
NJU6820
(31-9) Increment control
The “Increment control” instruction is used for the increment mode. In using the auto-increment
mode, DDRAM address automatically increments (+1) whenever the DDRAM is accessed by the
“Display data write” or “Display data read” instruction. Therefore, once “Display data write” or “Display
data read” instruction is established, it is possible to continuously access to the DDRAM without the
“column address” and “row address” instructions. The settings for the “AIM”, “AXI” and “AYI” registers
are listed in the following tables.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
1
0
WIN
AIM
AYI
AXI
# AIM, AYI and AXI registers
AIM
0
1
Increment mode
Auto-increment for both of the display data read and write operations
Auto-increment for the display write operation (Read modify write)
Note
1
2
Note 1) It is effective for usual operations accessing successive addresses.
Note 2) It is effective for the read-modify-write operation.
AYI
0
0
1
AXI
0
1
0
1
1
Increment mode
No auto-increment
Auto-increment for the column address
Auto-increment for the row address
Auto-increment for the column address and row
address
Note
1
2
3
4
Note 1) Auto-increment is disabled regardless of the “AIM” register.
Note 2) Auto-increment is of the column address is enabled in accordance with the “AIM” register.
00H
MAXH
MAXH in the 8-bit data bus mode
MAXH in the 16-bit data bus mode
: FFH
: 7FH
Note 3) Auto-increment of the row address is enabled in accordance with the “AIM” register.
00H
27H
Note 4) Auto-increment of the column address and the row address are enabled. The row address
increments whenever the column address reaches to the MAXH.
00H
MaxH
column address
MAXH in the 8-bit data bus mode
MAXH in the 16-bit data bus mode
00H
7FH
row address
: FFH
: 7FH
- 59 -
NJU6820
# WIN register
The “WIN” register is used to access to the DDRAM for the window display area, where the
start point is determined by the “column address” and “row address” instructions, and the end
point by the “Window end column address “and ”Window end row address” instructions. The
setting sequence for the window display area is listed as follows. For more detail, see (7)
“Window addressing mode”.
WIN=0
WIN=1
:Window addressing mode OFF
:Window addressing mode ON
1. Set WIN=1, AXI=1, and AYI=1 by “Increment control” instruction.
2. Set the start point by the “column address” and “row address” instructions
3. Set the end point by the “Window end column address” and “Window end row address”
instructions
4. Enable to access to the DDRAM in the window addressing mode
START
Address
END
Address
column address
- 60 -
START
Address
END
Address
row address
NJU6820
(31-10) Power control
CSb
RS
0
1
RDb WRb RE2
1
0
0
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
1
AMPON
HALT
DCON
ACL
# ACL register
The “ACL” register is used to initialize the internal power supply circuits.
ACL=0
ACL=1
: Initialization OFF (Normal)
: Initialization ON
When the data of the “ACL register” is read out by the “Instruction register read” instruction,
the read-out data is “1” during the initialization and “0” after the initialization. This initialization is
performed by using the signal produced by 2 clocks on the OSC1. For this reason, the wait time
for 2 clocks of the OSC1 necessary until next instruction.
# DCON register
The “DCON” register is used to enable or disable the voltage booster.
DCON=0
DCON=1
: Voltage booster OFF
: Voltage booster ON
# HALT register
The “HALT” register is used to enable or disable the power save mode. It is possible reduce
operating current down to stand-by level. The internal status in the power save mode is listed
below.
HALT=0
HALT=1
: Power save OFF (Normal)
: Power save ON
Internal status in the power save mode
• The oscillation circuits and internal power supply circuits are halted.
• All segment and common drivers output VSS level.
• The clock input into the OSC1 is inhibited.
• The display data in the DDRAM is maintained.
• The operational modes before the power save mode are maintained.
• The V1 to V4 and VLCD are in the high impedance.
As a power save ON sequence, the “Display OFF” must be executed first, next the “Power
save ON” instruction, and then all common and segment drivers output the VSS level. And as
power save OFF sequence, the “Power save OFF” instruction is executed first, next the “Display
ON” instruction. If the “Power save OFF” instruction is executed in the display ON status,
unexpected pixels may instantly turn on.
# AMPON register
The “AMPON” register is used to enable or disable the voltage followers, voltage regulator and
EVR.
AMPON=0
AMPON=1
: The voltage followers, voltage regulator the EVR OFF
: The voltage followers, voltage regulator the EVR ON
- 61 -
NJU6820
(31-11) Duty cycle ratio
The “Duty cycle ratio” instruction is used to select LCD duty cycle ratio for the partial display
function. The partial display function specifies some parts of display area on a LCD panel in the
condition of lower duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving
voltage. Therefore, it is possible to optimize the LSI’s conditions with extremely low power
consumption.
CSb
RS
0
1
RDb WRb RE2
1
0
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
0
DS3
DS2
DS1
DS0
0
DS3
DS2
DS1
DS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Row way
displays
40 commons
37 commons
33 commons
29 commons
25 commons
21 commons
17 commons
13 commons
9 commons
5 commons
Duty cycle ratio
DSE=0
DSE=1
1/41
1/40
1/37
1/36
1/33
1/32
1/29
1/28
1/25
1/24
1/21
1/20
1/17
1/16
1/13
1/12
1/9
1/8
1/4
1/5
Inhibited
Inhibited
Inhibited
Inhibited
Inhibited
Inhibited
The duty cycle ratio is controlled by the “DS3 to DS0” registers of the “Duty cycle ratio” instruction and the
“DSE” register of the “Display Clock / Duty-1” instruction.
DSE=”0”
DSE=”1”
: The number of commons + 1
(Duty cycle ratio in the default setting)
: The number of commons (Duty-1)
When the “DSE” is “0”, all common drivers output non-selective levels in period of last common.
And the segment drivers output the same data for the last line as the data for previous line:
th
th
For instance they output the same data for the 40 and 41 lines when the duty cycle ratio is
set to 1/41. For the setting of the “DSE” register, see (31-17) “Display clock / Duty-1”.
(31-12) Boost level
The “Boost level” is used to select the multiple of the voltage booster for the partial display function.
CSB
RS
0
1
RDB WRB RE2
1
0
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
1
*
VU2
VU1
VU0
0
VU2
0
0
0
0
1
1
1
1
- 62 -
RE1
VU1
0
0
1
1
0
0
1
1
VU0
0
1
0
1
0
1
0
1
Boost level
1-time (No boost)
2-time
3-time
4-time
5-time
Inhibited
Inhibited
Inhibited
NJU6820
(31-13) LCD bias ratio
The “LCD bias ratio” is used to select the LCD bias ratio for the partial display function.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
1
0
*
B2
B1
B0
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
LCD bias ratio
1/8
1/7
1/6
1/5
1/4
Inhibited
Inhibited
Inhibited
(31-14) RE flag
The “RE flag” registers are used to determine the contents for the RE registers (RE2, RE1 and RE0)
and it is possible to access to the instruction registers.
The data in the “TST0” register must be “0”, and it is used maker tests only.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0/1
0/1
0/1
1
1
1
1
TST0
RE2
RE1
RE0
- 63 -
NJU6820
(31-15) Gradation palette A, B and C
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
- 64 -
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
0
PA03/
PA83
PA02/
PA82
PA01/
PA81
PA00/
PA80
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
1
*
*
*
PA04/
PA84
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
1
0
PA13/
PA93
PA12/
PA92
PA11/
PA91
PA10/
PA90
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
1
1
*
*
*
PA14/
PA94
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
0
PA23/
PA103
PA22/
PA102
PA21/
PA101
PA20/
PA100
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
1
*
*
*
PA24/
PA104
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
1
0
PA33/
PA113
PA32/
PA112
PA31/
PA111
PA30/
PA110
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
1
1
*
*
*
PA34/
PA114
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
0
0
PA43/
PA123
PA42/
PA122
PA41/
PA121
PA40/
PA120
NJU6820
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
0
1
*
*
*
PA44/
PA124
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
1
0
PA53/
PA133
PA52/
PA132
PA51/
PA131
PA50/
PA130
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
1
1
*
*
*
PA54/
PA134
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
1
0
0
PA63/
PA143
PA62/
PA142
PA61/
PA141
PA60/
PA140
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
1
0
1
*
*
*
PA64/
PA144
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
0
PA73/
PA153
PA72/
PA152
PA71/
PA151
PA70/
PA150
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
1
*
*
*
PA74/
PA154
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
PB03/
PB83
PB02/
PB82
PB01/
PB81
PB00/
PB80
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
*
*
*
PB04/
PB84
- 65 -
NJU6820
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
- 66 -
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
0
0
PB13/
PB93
PB12/
PB92
PB11/
PB91
PB10/
PB90
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
0
1
*
*
*
PB14/
PB94
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
0
PB23/
PB103
PB22/
PB102
PB21/
PB101
PB20/
PB100
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
1
*
*
*
PB24/
PB104
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
0
PB33/
PB113
PB32/
PB112
PB31/
PB111
PB30/
PB110
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
*
*
*
PB34/
PB114
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
PB43/
PB123
PB42/
PB122
PB41/
PB121
PB40/
PB120
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
1
*
*
*
PB44/
PB124
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
0
PB53/
PB133
PB52/
PB132
PB51/
PB131
PB50/
PB130
NJU6820
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
*
*
*
PB54/
PB134
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
0
PB63/
PB143
PB62/
PB142
PB61/
PB141
PB60/
PB140
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
1
*
*
*
PB64/
PB144
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
1
0
PB73/
PB153
PB72/
PB152
PB71/
PB151
PB70/
PB150
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
1
1
*
*
*
PB74/
PB154
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
0
PC03/
PC83
PC02/
PC82
PC01/
PC81
PC00/
PC80
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
1
*
*
*
PC04/
PC84
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
1
0
PC13/
PC93
PC12/
PC92
PC11/
PC91
PC10/
PC90
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
1
1
*
*
*
PC14/
PC94
- 67 -
NJU6820
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
- 68 -
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
0
PC23/
PC103
PC22/
PC102
PC21/
PC101
PC20/
PC100
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
*
*
*
PC24/
PC104
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
1
0
PC33/
PC113
PC32/
PC112
PC31/
PC111
PC30/
PC110
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
1
1
*
*
*
PC34/
PC114
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
1
0
0
PC43/
PC123
PC42/
PC122
PC41/
PC121
PC40/
PC120
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
1
0
1
*
*
*
PC44/
PC124
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
PC53/
PC133
PC52/
PC132
PC51/
PC131
PC50/
PC130
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
1
*
*
*
PC54/
PC134
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
0
PC63/
PC143
PC62/
PC142
PC61/
PC141
PC60/
PC140
NJU6820
CSb
RS
0
1
CSb
RS
0
1
CSb
RS
0
1
RDb WRb
1
0
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
1
*
*
*
PC64/
PC144
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
0
PC73/
PC153
PC72/
PC152
PC71/
PC151
PC70/
PC150
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
1
*
*
*
PC74/
PC154
Gradation Palette Table (Variable gradation mode, PWM=”0” and MON=”0”)
(Palette Aj, Palette Bj, Palette Cj, (j=0 to 15))
Palette Value
Gradation
Level
Note
0 0 0 0 0
0/31
Gradation Palette 0
Initial Value
0 0 0 0 1
Gradation
Level
Palette Value
1
0 0 0
0
16/31
1/31
1
0 0 0
1
17/31
0 0 0 1 0
2/31
1
0 0 1
0
18/31
0 0 0 1 1
3/31
1
0 0 1
1
19/31
0 0 1 0 0
4/31
1
0 1 0
0
20/31
0 0 1 0 1
5/31
1
0 1 0
1
21/31
0 0 1 1 0
6/31
1
0 1 1
0
22/31
0 0 1 1 1
7/31
1
0 1 1
1
23/31
0 1 0 0 0
8/31
1
1 0 0
0
24/31
0 1 0 0 1
9/31
1
1 0 0
1
25/31
0 1 0 1 0
10/31
1
1 0 1
0
26/31
0 1 0 1 1
11/31
1
1 0 1
1
27/31
0 1 1 0 0
12/31
1
1 1 0
0
28/31
0 1 1 0 1
13/31
1
1 1 0
1
29/31
0 1 1 1 0
14/31
1
1 1 1
0
30/31
0 1 1 1 1
15/31
1
1 1 1
1
31/31
Gradation Palette 1
Initial Value
Gradation Palette2
Initial Value
Gradation Palette 3
Initial Value
Gradation Palette 4
Initial Value
Gradation Palette 5
Initial Value
Gradation Palette 6
Initial Value
Gradation Palette 7
Initial Value
Note
Gradation Palette 8
Initial Value
Gradation Palette 9
Initial Value
Gradation Palette 10
Initial Value
Gradation Palette 11
Initial Value
Gradation Palette 12
Initial Value
Gradation Palette 13
Initial Value
Gradation Palette 14
Initial Value
Gradation Palette 15
Initial Value
- 69 -
NJU6820
(31-16) Initial COM line
The “Initial COM line” instruction is used to specify the common driver that starts scanning the
display data. The line address, corresponding to the initial COM line, is specified by the “Initial display
line” instruction.
CSb
RS
0
1
SC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
1
0
SC3
SC2
SC1
SC0
SC2 SC1 SC0
Initial COM line (SHIFT=0)
Initial COM line (SHIFT=1)
0
0
0
COM0
COM39
0
0
1
COM4
COM31
0
1
0
COM8
COM27
0
1
1
COM16
COM23
1
0
0
COM20
COM19
1
0
1
COM24
COM15
1
1
0
COM28
COM11
1
1
1
COM32
COM7
0
0
0
COM36
COM3
0
0
1
Inhibited
Inhibited
0
1
0
Inhibited
Inhibited
0
1
1
Inhibited
Inhibited
1
0
0
Inhibited
Inhibited
1
0
1
Inhibited
Inhibited
1
1
0
Inhibited
Inhibited
1
1
1
Inhibited
Inhibited
SHIFT=0: Positive scan direction
(for instance, COM0 → COM39)
SHIFT=1: Negative scan direction
(for instance, COM39 → COM0)
(31-17) Display clock / Duty-1
The “Display clock / Duty-1” instruction is used to enable or disable the display clocks (CL, FLM, FR, and
CLK), and to control ON/OFF of the “Duty-1”. For more detail about the “Duty-1”, see (31-11) “Duty cycle
ratio”.
CSb
RS
0
1
- 70 -
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
1
1
*
*
DSE
SON
SON=0:
SON=1:
CL, FLM, FR, and CLK outputs level “0”.
CL, FLM, FR, and CLK outputs are active.
DSE=0:
DSE=1:
Duty -1 OFF
Duty -1 ON
NJU6820
(31-18) Gradation mode control
The “Gradation mode control” is used select display mode as follows.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
1
0
0
1
0
0
0
D3
D2
PWM C256
D1
D0
*
*
# PWM register
PWM=0: Variable gradation mode
(Variable 16-gradation levels out of 32-gradation level of the gradation palette)
PWM=1: Fixed gradation mode
(Fixed 8-gradation levels)
# C256 register
C256=0 256-color mode OFF (4,096-color in the default setting)
C256=1 256-color mode ON
(31-19) Data bus length
The “Data bus length” instruction is used to select the 8- or 16- bit data bus length and determine
the internal or external oscillation. In the 16-bit data bus mode, instruction data must be 16-bit (D15 to
D0) as well as display data. However, for the access to the instruction registers, the lower 8-bit data
(D7 to D0) of the 16-bit data is valid. For the access to the DDRAM, all of the 16-bit data (D15 to D0) is
valid.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
1
0
0
1
0
0
1
D3
D2
HSW ABS
D1
D0
CKS WLS
# HSW register
HSW =0: High Speed access mode OFF
HSW=1: High Speed access mode ON (only in the 8-bit data bus length)
# ABS register
ABS=0: ABS mode OFF (normal)
ABS=1: ABS mode ON
# WLS register
WLS=0: 8-bit data bus length
WLS =1: 16-bit data bus length
# CKS register
CKS =0:
CKS =1:
Internal oscillation
(The OSC1 terminal must be fixd “1” or “0”.)
External oscillation
(By the external clock into the OSC1 or external resister between the OSC1 and
OSC2. OSC2 should be open when clock is inputted from OSC1.)
- 71 -
NJU6820
(31-20) EVR control
The “EVR control” instruction is used to fine-tune the LCD driving voltage (VLCD) so that it is
possible to optimize the contrast level for a LCD panel.
This instruction must be programmed by upper 3-bit data first, next lower 4-bit data. And it
becomes enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high
voltage for the VLCD from being generated.
CSb
RS
0
1
CSb
RS
0
1
RDb WRb RE2
1
0
1
RDb WRb RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
0
DV3
DV2
DV1
DV0
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
*
DV6
DV5
DV4
1
0
1
0
DV6
0
0
DV5
0
0
DV4
0
0
1
1
1
DV3
0
0
:
:
1
DV2
0
0
DV1
0
0
DV0
0
1
1
1
1
VLCD
Low
:
:
:
High
The formula of the VLCD is shown below.
VLCD [V] = 0.5 x VREG + M (VREG – 0.5 x VREG) / 127
VBA = VEE x 0.9
VREG = VREF x N
- 72 -
VBA
VREF
VREG
N
M
: Output voltage of the reference voltage generator
: Input voltage of the voltage regulator
: Output voltage of the voltage regulator
: Register value for the voltage booster
: Register value for the EVR
NJU6820
(31-21) Frequency control
The “Frequency control” instruction is used to control the frame frequency for a LCD panel.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
0
1
*
Rf2
Rf1
Rf0
# Rfx register (x=0, 1, 2)
The “Rfx” register is used to determine the feed back resister value for the internal oscillator
and it is possible to adjust the frame frequency for the LCD modules.
Rf 2
0
0
0
0
1
1
1
1
Rf 1
0
0
1
1
0
0
1
1
Rf 0
0
1
0
1
0
1
0
1
Feedback resistor value
Reference value
0.8 x reference value
0.9 x reference value
1.1 x reference value
1.2 x reference value
0.7 x reference value
1.3 x reference value
Inhibited
(31-22) Discharge ON/OFF
Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and the
VLCD terminals. The “Discharge ON/OFF” instruction is usually required just after the internal power
supply is turned off by setting “0” into the “DCON” and “AMPON” registers, or just after the external
power supply is turned off. During the discharge operation, the internal or external power supply must
not be turned on.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
1
0
*
*
DIS2
DIS
DIS=0:
DIS=1:
Discharge OFF
Discharge ON
(Capacitors on the VLCD, V1, V2, V3 and V4)
(Capacitors on the VLCD, V1, V2, V3 and V4)
DIS2=0:
DIS2=1:
Discharge OFF
Discharge ON
(Resistance between VOUT and VEE)
(Resistance between VOUT and VEE)
Note ) VOUT and VEE are internally connected with the resistor (100kΩ typical) in the power-ON.
- 73 -
NJU6820
(31-23) Instruction register address
The “Instruction register address” is used to specify the instruction register address, so that it is
possible to read out the contents of the instruction registers in combination with the “Instruction
register read” instruction.
CSB
RS
0
1
RDB WRB RE2
1
0
1
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
0
RA3
RA2
RA1
RA0
(31-24) Instruction register read
The “Instruction register read” instruction is used to read out the contents of the instruction register
in combination with the “Instruction register address” instruction.
CSb
RS
0
1
RDb WRb
0
1
RE2
RE1
RE0
D7
D6
D5
D4
0/1
0/1
0/1
*
*
*
*
D3
D2
D1
D0
Internal register data read
(31-25) Window end column address
The “Window end column address” is used to specify the column address for the window end point.
The lower 4-bit data is required to be programmed first and then the upper 4-bit data can be
programmed.
CSb
RS
0
1
CSb
RS
0
1
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
0
0
EX3
EX2
EX1
EX0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
0
1
EX7
EX6
EX5
EX4
(31-26) Window end row address set
The “Window end row address” is used to specify the row address for the window end point. The
lower 4-bit data is required to be programmed first and then the upper 2-bit data can be programmed.
CSb
RS
0
1
CSb
RS
0
1
- 74 -
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
1
0
EY3
EY2
EY1
EY0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
1
1
*
*
EY5
EY4
NJU6820
(31-27) Initial reverse line
The “Initial reverse line” instruction is used to specify the initial reverse line address for the reverse
line display. Lower 4-bit data must be programmed first, next upper 2-bit data. It is programmed in
between 00H and 27H and the line address beyond 27H is inhibited. The address relation: LSi < LEi
(i=7 to 0) must be maintained in the reverse line display.
CSb
RS
0
1
CSb
RS
0
1
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
0
LS3
LS2
LS1
LS0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
1
*
*
LS5
LS4
(31-28) Last reverse line
The “Last reverse line” instruction is used to specify the last reverse line address for the reverse
line display. Lower 4-bit must be programmed first, next upper 2-bit data. It is programmed in
between 00H and 27H and the line address beyond 27H is inhibited. The address relation: LSi < LEi
(i=7 to 0) must be maintained in the reverse line display.
CSb
RS
0
1
CSb
RS
0
1
RDb WRb
1
0
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
1
0
LE3
LE2
LE1
LE0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
1
1
*
*
LE5
LE4
(31-29) Reverse line display ON/OFF
The “Reverse line display ON/OFF” is used to enable or disable the reverse line display for the
blink operation and determine the reverse line display mode.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
0
0
0
*
*
BT
LREV
# LREV register
The “LREV” register is used to enable or disable the reverse line display.
LREV =0:
LREV =1:
Reverse line display OFF (Normal)
Reverse line display ON
- 75 -
NJU6820
# BT register
The “BT” register is used to determine the reverse line display mode in the reverse line display
ON (LREV=1) status.
BT =0:
BT =1:
Normal reverse line display
Blink once every 32 frames
Display examples in the LREV=”1” and BT=”1”
!"""!
"!!!"
"!!!!
!"""!
!!!!"
"!!!"
!"""!
!!!!!
"!!!"
!"""!
!""""
"!!!"
""""!
!"""!
"!!!"
"""""
Blink once every 32 frames
NJRC
LCD DRIVER
Low Power and
Low Voltage
Blink once every 32 frames
NJRC
←Initial reverse line address
LCD DRIVER
←Last reverse line address
Low Power and
Low Voltage
(31-30) Gradation Palette setting control
CSb
RS
0
1
RDb WRb
1
# PS register
PS=0:
PS=1:
- 76 -
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
0
0
1
*
*
*
PS
Lower 8 Gradation setting
Upper 8 Gradation setting
NJU6820
(31-31) PWM control
The “PWM control” is used to determine the PWM type for the segment waveforms, where the type
can be specified for each of the SEGAi, SEGBi and SEGCi (i=0-127) drivers.
CSb
RS
0
1
RDb WRb
1
0
RE2
RE1
RE0
D7
D6
D5
D4
1
0
1
1
0
1
0
D3
D2
D1
D0
PWMS PWMA PWMB PWMC
# PWMS register
PWMS=0: Type 1
PWMS=1: Type 2
# PWMA, B and C registers
The “PWMA, PWMB and PWMC” registers are used to select the type 1-O or type 1-E.
PWMZ=0 (Z=A, B and C): Type 1-O
PWMZ=1 (Z=A, B and C): Type 1-E
PWM type1 (PWMS=”0”)
“H”
CL
Odd line
Even line
“L”
VLCD
Type-O
→
←
V2
SEG
VLCD
Type-E
→
←
V2
PWM type2 (PWMS=”1”)
CL
“H”
“L”
SEG
VLCD
→
→
V2
- 77 -
NJU6820
(32) The relationship between Common drivers and row addresses
Row address assignment of common drivers is programmed by the “ SHIFT ” register of the “ Display
control (1) ” , “ Duty cycle ratio ”, “ Internal display line ” and “ Initial COM line ” instructions.
#
When initial display line is “0”
If the “ SHIFT “ is “ 0 “, the scan direction is normal. When the “ LA0 to LA6 ” registers of the
“ Initial display line “instruction is “ 0 “, the “ MY “ corresponding to the initial COM line is “ 0 “ and is
increasing during display.
#
When initial display line is not “0”
If the “ SHIFT “ is “ 1 “, the scan direction is inversed. When the “ LA0 to LA6 ” registers of the
“ Initial display line “instruction is not “ 0 “, the “ MY “ corresponding to the initial COM line is this
setting value and is increasing during display.
The following are examples of setting the start-line 0 or 5 at 1/41, 1/17, or 1/17 duty.
- 78 -
NJU6820
(32-1) Initial display line “0”, 1/41 duty cycle (Common forward scan, DSE=”0”)
SC3
SC2
SC1
SC0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
(40rd COM period) *1
0000
0
SHIFT=”0”(Common forward scan), DS3, 2, 1, 0=”0000”, LA5….LA0=”00000000”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
36
32
28
24
20
16
12
8
4
39
0
39
0
39
0
39
0
39
0
39
0
39
0
39
0
39
0
39
39
35
39
31
39
27
39
23
39
19
39
15
39
11
39
7
39
3
39
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 40th COM period is not selected.
(32-2) Initial display line “0”, 1/41 duty cycle (Common backward scan, DSE=”0”)
SC3
SC2
SC1
SC0
0000
SHIFT=”1”(Common forward scan), DS3, 2, 1, 0=”0000”, LA5….LA0=”00000000”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
39
3
7
11
15
19
23
27
31
35
0
4
8
12
16
20
24
28
32
36
(40rd COM period) *1
39
39
39
39
39
39
39
39
39
39
0
39
0
39
0
39
0
39
0
39
0
39
39
0
39
0
39
0
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 40th COM period is not selected.
- 79 -
NJU6820
(32-3) Initial display line “0”, 1/17 duty cycle (Common forward scan, DSE=”0”)
SC3
SC2
SC1
SC0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
(17rd COM period) *1
0000
SHIFT=”0”(Common forward scan), DS3, 2, 1, 0=”0110”, LA5….LA0=”00000000”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
0
12
8
4
15
0
15
0
15
0
15
0
15
0
15
0
15
0
15
0
15
0
16
16
16
16
16
16
15
16
11
16
7
16
3
16
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 17th COM period is not selected.
(32-4) Initial display line “0”, 1/17 duty cycle (Common backward scan, DSE=”0”)
SC3
SC2
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
SC1
SC0
0000
SHIFT=”1”(Common forward scan), DS3, 2, 1, 0=”0110”, LA5….LA0=”00000000”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
15
7
3
0
15
0
15
0
15
0
15
0
15
0
15
0
0
0
0
0
0
0
(17rd COM period) *1
16
16
16
16
16
16
16
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 17th COM period is not selected.
- 80 -
11
12
8
4
16
16
16
NJU6820
(32-5) Initial display line “0”, 1/5 duty cycle (Common forward scan, DSE=”0”)
SC3
SC2
SC1
SC0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
(5rd COM period) *1
0000
SHIFT=”0”(Common forward scan), DS3, 2, 1, 0=”1001”, LA5….LA0=”00000000”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
4
4
4
4
4
4
4
4
4
3
4
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 5th COM period is not selected.
(32-6) Initial display line “0”, 1/5 duty cycle (Common backward scan, DSE=”0”)
SC3
SC2
SC1
SC0
0000
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
0
(5rd COM period) *1
4
SHIFT=”1”(Common forward scan), DS3, 2, 1, 0=”1001”, LA5….LA0=”00000000”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
4
4
4
4
4
4
4
4
4
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 5th COM period is not selected.
- 81 -
NJU6820
(32-7) Initial display line “5”, 1/41 duty cycle (Common forward scan, DSE=”0”)
SC3
SC2
SC1
SC0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
(40rd COM period) *1
0000
5
SHIFT=”0”(Common forward scan), DS3, 2, 1, 0=”0000”, LA5….LA0=”00000101”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
1
37
33
29
25
21
17
13
9
39
0
5
39
0
5
39
0
5
39
0
5
39
0
5
39
0
5
39
0
5
39
0
5
39
0
5
4
39
39
0
39
36
39
32
39
28
39
24
39
20
39
16
39
12
39
8
39
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 40th COM period is not selected.
(32-8) Initial display line “5”, 1/41 duty cycle (Common backward scan, DSE=”0”)
SC3
SC2
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
SC1
SC0
0000
4
SHIFT=”1”(Common forward scan), DS3, 2, 1, 0=”0000”, LA5….LA0=”00000101”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
0
39
36
32
28
24
20
12
8
0
39
0
39
0
39
0
39
0
39
0
39
0
39
0
39
0
39
(40rd COM period) *1
5
1
37
33
29
25
21
17
13
9
39
39
39
39
39
39
39
39
39
39
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 40th COM period is not selected.
- 82 -
16
NJU6820
(32-9) Initial display line “5”, 1/17 duty cycle (Common forward scan, DSE=”0”)
SC3
SC2
SC1
SC0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
(17rd COM period) *1
0000
SHIFT=”0”(Common forward scan), DS3, 2, 1, 0=”0110”, LA5….LA0=”00000101”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
5
17
13
9
20
5
20
5
20
5
20
5
20
5
20
5
20
5
20
5
20
5
16
16
16
16
16
16
20
16
16
16
12
16
8
16
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 17th COM period is not selected.
(32-10) Initial display line “5”, 1/17 duty cycle (Common backward scan, DSE=”0”)
SC3
SC2
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
SC1
SC0
0000
SHIFT=”1”(Common forward scan), DS3, 2, 1, 0=”0110”, LA5….LA0=”00000101”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
20
16
12
8
5
20
5
20
5
20
5
20
5
20
5
20
5
20
5
20
5
20
5
(17rd COM period) *1
16
16
16
16
16
16
16
17
13
9
16
16
16
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 17th COM period is not selected.
- 83 -
NJU6820
(32-11) Initial display line “5”, 1/5 duty cycle (Common forward scan, DSE=”0”)
SC3
SC2
SC1
SC0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
(5rd COM period) *1
0000
SHIFT=”0”(Common forward scan), DS3, 2, 1, 0=”1001”, LA5….LA0=”00000101”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
5
8
5
8
5
8
5
8
5
8
5
8
5
8
5
8
5
8
5
4
4
4
4
4
4
4
4
4
DS: Duty
cycle ratio, SC: Initial COM line, LA: Initial display line
th
*1 : 5 COM period is not selected.
8
4
(32-12) Initial display line “5”, 1/5 duty cycle (Common forward scan, DSE=”0”)
SC3
SC2
SC1
SC0
0000
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
5
(5rd COM period) *1
4
SHIFT=”1”(Common forward scan), DS3, 2, 1, 0=”1001”, LA5….LA0=”00000101”(Initial display line 0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
8
5
8
5
8
5
8
5
8
5
8
5
8
5
8
5
8
5
3
8
4
4
4
4
4
4
4
4
DS: Duty
cycle ratio, SC: Initial COM line, LA: Initial display line
th
*1 : 5 COM period is not selected.
- 84 -
4
NJU6820
(32-13) Initial display line “0”, 1/40 duty cycle (Common forward scan, DSE=”1”)
SC3
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
SC2
SC1
SC0
0000
0
SHIFT=”0”(Common forward scan), DS3, 2, 1, 0=”0000”, LA5….LA0=”00000000”(Initial display line 0) DSE=”1”
0001
0010
0011
0100
0101
0110
0111
1000
1001
Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
36
32
28
24
20
16
12
8
4
39
0
39
0
39
0
39
0
39
0
39
0
39
0
39
0
39
0
39
35
31
27
23
19
15
11
7
3
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 85 -
NJU6820
■ ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage (1)
Supply Voltage (2)
Supply Voltage (3)
Supply Voltage (4)
Supply Voltage (5)
Supply Voltage (6)
Input Voltage
Storage Temperature
SYMBOL
VDD
VEE
VOUT
VREG
VLCD
V1, V2, V3, V4
VI
Tstg
CONDITION
VSS=0V
Ta = +25°C
TERMINAL
VDD
VEE
VOUT
VREG
VLCD
V1, V2, V3, V4
*1
RATING
-0.3 to +4.0
-0.3 to +4.0
-0.3 to +19.0
-0.3 to +19.0
-0.3 to +19.0
-0.3 to VLCD + 0.3
-0.3 to VDD + 0.3
-45 to +125
UNIT
V
V
V
V
V
V
V
°C
Note 1) D0 to D15, CSb, RS, RDb, WRb, OSC1, RESb, TEST1, TEST2, terminals.
Note 2) To stabilize the voltage booster operation, decoupling capacitors must be connected between
the VDD and VSS pins and between the VEE and VSSH pins.
!
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Operating Voltage
Operating
Temperature
Note1)
Note2)
Note3)
Note4)
SYMBOL
VDD1
VDD2
VEE
VLCD
VOUT
VREG
VREF
Topr
TERMINAL
VDD
VEE
VLCD
VOUT
VREG
VREF
MIN
1.7
2.4
2.4
5
TYP
2.1
MAX
3.3
3.3
3.3
18.0
18.0
VOUT × 0.9
3.3
UNIT
V
V
V
V
V
V
V
-30
85
°C
Applies to the condition when the reference voltage generator is not used.
Applies to the condition when the reference voltage generator is used.
Applies to the condition when the voltage booster is used.
The following relationship among the supply voltages must be maintained.
VSS<V4<V3<V2<V1<VLCD<VOUT
Note5) The relationship: VREF<VEE must be maintained.
- 86 -
NOTE
*1
*2
*3
*4
*5
NJU6820
■ DC CHARACTERISTICS 1
VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85°C
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
SYM
BOL
VIH
VIL
VOH1
VOL1
VOH2
VOL2
ILI
ILO
IOH = -0.4mA
IOL = 0.4mA
IOH = -0.1mA
IOL = 0.1mA
VI = VSS or VDD
VI = VSS or VDD
Driver ON-resistance
RON1
|∆VON| = 0.5V
VLCD = 10V
VLCD = 6V
ISTB
CSb=H, Ta=25°C
VDD = 3V
PARAMETER
Stand-by current
Internal oscillation
Frequency
External oscillation
Frequency
fOSC1
fOSC2
fOSC3
fr1
fr2
fr3
CONDITION
MIN
TYP
0.8 VDD
0
VDD - 0.4
MAX
VDD
0.2VDD
0.4
VDD - 0.4
-10
-10
VDD = 3V
Ta = 25°C
Rf=51kΩ
Rf=240kΩ
Rf=1800kΩ
N-time booster (N=2 to 5)
RL = 500kΩ (VOUT - VSS)
VDD = 3V, 5-time booster
Whole ON pattern
VDD = 3V, 5-time booster
Checker pattern
VDD = 3V,4-time booster
Whole ON pattern
VDD = 3V, 4-time booster
Checker pattern
Voltage converter
output voltage
VOUT
Supply current (1)
IDD1
Supply current (2)
IDD2
Supply current (3)
IDD3
Supply current (4)
IDD4
VBA Operating voltage
VBA
VEE = 2.4 to 3.3V
VREG Operating voltage
VREG
VEE = 2.4 to 3.3V
VREF = 0.9 x VEE
N-time booster (N=2 to 5)
Output Voltage
V2
V3
VD12
VD34
VD24
1
2
152
34
4.9
186
42
6.0
172
40
5.5
0.4
10
10
2
4
15
220
50
7.1
(N x VEE)
x 0.95
(0.9 VEE)
x 0.98
(VREF x N)
x 0.97
-100
-100
-30
-30
-30
520
780
650
980
360
540
450
680
0.9 VEE
(0.9 VEE)
x 1.02
(VREF x N)
0
0
0
0
0
(VREF x N)
x 1.03
+100
+100
+30
+30
+30
UNIT NOTE
V
V
V
V
V
V
µA
µA
*1
*1
*2
*2
*3
*3
*4
*5
kΩ
*6
µA
*7
*8
*9
*10
kHz
kHz
*11
V
*12
µA
*13
V
*14
V
*15
mV
*16
- 87 -
NJU6820
■ CLOCK and FRAME FREQUENCY
PARAMETER SYMBOL
Internal
clock
fOSC
Display mode
Display duty cycle ratio (1/D) <DSE=0>
1/41 to 1/25
1/21 to 1/13
1/9
1/5
16 Gradation mode
fOSC / (62xD)
fOSC / (62xDx2)
fOSC / (62xDx4)
fOSC / (62xDx8)
Simplified
8 gradation mode
fOSC / (14xD)
fOSC / (14xDx2)
fOSC / (14xDx4)
fOSC / (14xDx8)
B&W mode
fOSC / (2xD)
fOSC / (2xDx2)
fOSC / (2xDx4)
fOSC / (2xDx8)
16 Gradation mode
fCK / (62xD)
fCK / (62xDx2)
fCK / (62xDx4)
fCK / (62xDx8)
Simplified
8 gradation mode
fCK / (14xD)
fCK / (14xDx2)
fCK / (14xDx4)
fCK / (14xDx8)
B&W mode
fCK / (2xD)
fCK / (2xDx2)
fCK / (2xDx4)
fCK / (2xDx8)
NOTE
FLM
External
clock
- 88 -
fCK
NJU6820
APPLIED TERMINALS and CONDITIONS
Note 1) D0-D15, CSb, RS, RDb, WRb, P/S, SEL68, RESb
Note 2) D0-D15
Note 3) CL, FLM, FR, CLK
Note 4) CSb, RS, SEL68, RDb, WRb, P/S, RESb, OSC1
Note 5) D0-D15 in the high impedance
Note 6) SEGA0-SEGA127, SEGB0-SEGB127, SEGC0-SEGC127, COM0-COM39
- Defines the resistance between the COM/SEG terminals and each of the power supply terminals
(VLCD, V1, V2, V3 and V4) at the condition of 0.5V deference and 1/8 LCD bias ratio.
Note 7) VDD
- The oscillator is halted, CSb=”1” (disabled), No-load on the COM/SEG drivers
Note 8) OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the variable gradation mode.
Note 9) OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the fixed gradation mode.
Note 10) OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the Black & White mode.
Note 11) VDD=3V, Ta=25°C
Note 12) VOUT
- Applies to the condition when the internal voltage booster, the internal oscillator and internal
power circuits are used.
- VEE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1), 1/4 to 1/8 LCD bias, 1/41 duty cycle, No-load on
COM/SEG drivers
- RL=500KΩ between the VOUT and the VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”
Note 13) VDD
- Applies to the condition using the internal oscillator and internal power circuits, no access
between the LSI and MPU.
- EVR= (1,1,1,1,1,1,1), All pixels turned-on or checkerboard display in gradation mode.
No-load on the COM/SEG drivers.
- VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”
1/41 Duty cycle, Ta=25°C
Note 14) VBA
- Applies to the condition that VBA=VREF and voltage booster N= 1. DCON=”0”, VOUT=13.5V input.
Note 15) VREG
- VEE=2.4V to 3.3V, VREF=0.9VEE, VOUT=18V, 1/4 to 1/8 LCD bias ratio, 1/41 duty cycle,
EVR=(1,1,1,1,1,1,1)
- Checkerboard display, No-load on the COM/SEG drivers, the voltage booster N=2 to 5
CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”, AMPON=”1”, NLIN=”0”
Note 16) VLCD, V1, V2, V3, V4
- VEE=3.0V, VREF=0.9VEE, VOUT=15V, 1/4 to 1/8 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, Noload on the COM/SEG drivers, voltage booster N=5, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”,
AMPON=”1”
(1)
(2)
(3)
(4)
VLCD
V1
V2
V3
V4
VSS
VD12: (1)-(2)
VD34: (3)-(4)
VD24: (2)-(4)
- 89 -
NJU6820
■ AC CHARACTERISTICS
!
Write operation (80-type MPU)
tAS8
tAH8
CSb
RS
WRb
tWRLW8
tWRHW8
tDS8
tDH8
D0 to D15
tCYC8
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Data setup time
Data hold time
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Data setup time
Data hold time
SYMBOL
tAH8
tAS8
CONDITION
MIN.
0
0
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
tCYC8
tWRLW8
tWRHW8
90
35
35
ns
ns
ns
WRb
tDS8
tDH8
30
5
ns
ns
D0 to D15
SYMBOL
tAH8
tAS8
CONDITION
MIN.
0
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
tCYC8
tWRLW8
tWRHW8
160
70
70
ns
ns
ns
WRb
tDS8
tDH8
40
5
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
SYMBOL
tAH8
tAS8
tCYC8
tWRLW8
tWRHW8
CONDITION
MIN.
0
0
MAX.
UNIT
ns
ns
TERMINAL
CSb
RS
180
80
80
ns
ns
ns
WRb
Data setup time
tDS8
70
Data hold time
tDH8
10
Note) Each timing is specified based on 20% and 80% of VDD.
ns
ns
D0 to D15
- 90 -
NJU6820
!
Read operation (80-type MPU)
tAH8
tAS8
CSb
RS
tWRLR8
RDb
tWRHR8
tRDH8
D0 to D15
tRDD8
tCYC8
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Read Data delay time
Read Data hold time
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Read Data delay time
Read Data hold time
SYMBOL
tAH8
tAS8
CONDITION
tCYC8
tWRLR8
tWRHR8
tRDD8
tRDH8
SYMBOL
tAH8
tAS8
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
180
80
80
CL=15pF
CONDITION
tCYC8
tWRLR8
tWRHR8
tRDD8
tRDH8
MIN.
0
0
60
0
MIN.
0
0
RDb
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
180
80
80
CL=15pF
ns
ns
ns
60
0
ns
ns
ns
RDb
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
SYMBOL
tAH8
tAS8
tCYC8
tWRLR8
tWRHR8
CONDITION
MIN.
0
0
MAX.
250
120
120
Read Data delay time
tRDD8
CL=15pF
Read Data hold time
tRDH8
0
Note) Each timing is specified based on 20% and 80% of VDD.
110
UNIT
ns
ns
TERMINAL
CSb
RS
ns
ns
ns
RDb
ns
ns
D0 to D15
- 91 -
NJU6820
!
Write operation (68-type MPU)
tAH6
tAS6
CSb
RS
R/W
(WRb)
tELW6
tEHW6
E
(RDb)
tDS6
tDH6
D0 to D15
tCYC6
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Data setup time
Data hold time
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Data setup time
Data hold time
SYMBOL
tAH6
tAS6
CONDITION
MIN.
0
0
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
tCYC6
tELW6
tEHW6
90
35
35
ns
ns
ns
E
tDS6
tDH6
40
5
ns
ns
D0 to D15
SYMBOL
tAH6
tAS6
CONDITION
MIN.
0
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
tCYC6
tELW6
tEHW6
160
70
70
ns
ns
ns
E
tDS6
tDH6
50
5
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
SYMBOL
tAH6
tAS6
tCYC6
tELW6
tEHW6
CONDITION
MIN.
0
0
MAX.
UNIT
ns
ns
TERMINAL
CSb
RS
180
80
80
ns
ns
ns
E
Data setup time
tDS6
70
Data hold time
tDH6
10
Note) Each timing is specified based on 20% and 80% of VDD.
ns
ns
D0 to D15
- 92 -
NJU6820
!
Read operation (68-type MPU)
tAS6
tAH6
CSb
RS
R/W
(WRb)
tELR6
tEHR6
E
(RDb)
tRDH6
D0 to D15
tRDD6
tCYC6
PARAMETER
Address hold time
Address setup time
SYMBOL
tAH6
tAS6
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
Read Data delay time
Read Data hold time
tRDD6
tRDH6
PARAMETER
Address hold time
Address setup time
SYMBOL
tAH6
tAS6
CONDITION
MIN.
0
0
180
80
80
CL=15pF
0
CONDITION
MIN.
0
0
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
Read Data delay time
Read Data hold time
tRDD6
tRDH6
CL=15pF
0
SYMBOL
CONDITION
MIN.
PARAMETER
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
70
ns
ns
ns
E
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
180
80
80
70
ns
ns
ns
E
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
250
120
120
ns
ns
ns
E
Read Data delay time
Read Data hold time
tRDD6
tRDH6
ns
ns
D0 to D15
CL=15pF
0
110
Note) Each timing is specified based on 20% and 80% of VDD.
- 93 -
NJU6820
!
Serial interface
CSb
tCSH
tCSS
RS
tASS
SCL
tAHS
tSLW
tSHW
tCYCS
tDSS
tDHS
SDA
PARAMETER
Serial clock cycle
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CSb – SCL time
CSb hold time
PARAMETER
Serial clock cycle
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CSb – SCL time
CSb hold time
SYMBOL CONDITION
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
tCSS
tCSH
SYMBOL CONDITION
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
tCSS
tCSH
MIN.
50
20
20
20
20
20
20
20
20
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
UNIT
MAX.
TERMINAL
ns
ns
SCL
ns
ns
RS
ns
ns
SDA
ns
ns
CSb
ns
MIN.
50
20
20
20
20
20
20
20
20
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
UNIT
MAX.
TERMINAL
ns
ns
SCL
ns
ns
RS
ns
ns
SDA
ns
ns
CSb
ns
PARAMETER
SYMBOL CONDITION
MIN.
80
Serial clock cycle
tCYCS
35
SCL ”H” level pulse width
tSHW
35
tSLW
SCL ”L” level pulse width
35
Address setup time
tASS
35
Address hold time
tAHS
35
Data setup time
tDSS
35
Data hold time
tDHS
35
CSb – SCL time
tCSS
35
t
CSH
CSb hold time
Note) Each timing is specified based on 20% and 80% of VDD.
- 94 -
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
UNIT
MAX.
TERMINAL
ns
ns
SCL
ns
ns
RS
ns
ns
SDA
ns
ns
CSb
ns
NJU6820
!
Display control timing
CLK
tDCL
CL
tDFLM
tDFLM
FLM
tFR
FR
Output timing
PARAMETER
FLM delay time
FR delay time
CL delay time
Output timing
PARAMETER
FLM delay time
FR delay time
CL delay time
SYMBOL CONDITION
tDFLM
CL=15pF
tFR
tDCL
SYMBOL CONDITION
tDFLM
CL=15pF
tFR
tDCL
MIN.
0
0
0
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
500
ns
FLM
500
ns
FR
200
ns
CL
MIN.
0
0
0
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
1000
ns
FLM
1000
ns
FR
200
ns
CL
Note) Each timing is specified based on 20% and 80% of VDD.
- 95 -
NJU6820
!
Input clock timing
tCKLW
OSC1
PARAMETER
OSC1 “H” level pulse width (1)
OSC1 “L” level pulse width (1)
OSC1 “H” level pulse width (2)
OSC1 “L” level pulse width (2)
OSC1 “H” level pulse width (3)
OSC1 “L” level pulse width (3)
tCKHW
SYMBOL
tCKHW1
tCKLW1
tCKHW2
tCKLW2
tCKHW3
tCKLW3
CONDITION
MIN.
2.27
2.27
10
10
70
70
(VDD=1.7 to 3.3V, Ta=-30 to +85°C)
UNIT
MAX.
TERMINAL
OSC1
3.29
µs
∗1
3.29
µs
OSC1
14.7
µs
∗2
14.7
µs
OSC1
103
µs
∗3
103
µs
Note) Each timing is specified based on 20% and 80% of VDD.
Note 1) Applied to the variable gradation / mode MON=”0”,PWM=”0”
Note 2) Applied to the fixed gradation / mode MON=”0”,PWM=”1”
Note 3) Applied to the B&W mode / MON=”1”
- 96 -
NJU6820
!
Reset input timing
tRW
RESb
tR
Internal circuit
status
PARAMETER
Reset time
RESb “L” level pulse width
PARAMETER
Reset time
RESb “L” level pulse width
End of reset
During reset
SYMBOL CONDITION
MIN.
tR
tRW
SYMBOL CONDITION
1.0
MIN.
RESb
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
UNIT
MAX.
Terminal
1.5
10.0
µs
µs
10.0
tR
tRW
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
UNIT
MAX.
Terminal
µs
µs
RESb
Note) Each timing is specified based on 20% and 80% of VDD.
- 97 -
NJU6820
!
Typical characteristic
PARAMETER
Basic delay time of gate
!
SYMBOL
Ta=+25°C, VSS=0V, VDD=3.0V
MIN
TYP
10
MAX
Input output terminal type
(a) Input circuit
VDD
Terminals:
CSb, RS, RDb, WRb, SEL68,
P/S, RESb
I
Input signal
VSS(0V)
(b) Output circuit
Terminals:
VDD
FLM, CL, FR, CLK
Output control signal
O
Output signal
VSS(0V)
(c) Input/Output circuit
VDD
Terminals:
D0 to D15
I/O
Input signal
VSS(0V)
VSS(0V)
Input control signal
VDD
Output control signal
Output signal
VSS(0V)
- 98 -
UNIT
ns
NJU6820
(d) Display output circuit
VLCD
VLCD
VLCD
V1/V2
Output control
signal 1
Output control signal 2
Output control
signal 3
Output control signal 4
O
VSS(0V)
Terminals:
V3/V4
VSS(0V)
VSS(0V)
SEGA0 to SEGA127
SEGB0 to SEGB127
SEGC0 to SEGC127
COM0 to COM39
- 99 -
NJU6820
■ APPLICATION CIRCUIT EXAMPLES
(1) MPU Connections
80-type MPU interface
1.7V to 3.3V
VCC
A0
A1 to A7
7
(80-type MPU)IORQb
D0 to D7
RS
Decoder
8
RDb
WRb
RESb
VDD
NJU6820
CSb
D0 to D7
RDb
WRb
RESb V
SS
GND
RESET
68-type MPU interface
1.7V to 3.3V
VCC
A0
A1 to A15
(68-type MPU) VMA
RS
15
D0 to D7
Decoder
8
E
R/W
RESb
NJU6820
CSB
D0 to D7
RDb (E)
WRb(R/W)
RESb
GND
VDD
VSS
RESET
Serial interface
1.7V to 3.3V
VCC
A0
A1 to A7
(MPU)
RS
7
Decoder
SDA
SCL
RESb
RESb
RESET
- 100 -
NJU6820
CSb
PORT1
PORT2
GND
VDD
VSS
NJU6820
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 101