Ordering number:ENN2648 CMOS IC LC66PG5XX EPROM-Mountable Type 4-bit Microcomputer Evaluation Chip for The LC665XX Series Microcomputers Overview Pin assignment The LC66PG5XX is an EPROM-mountable type 4-bit microcomputer for developing and evaluating programs written for the CMOS 4-bit single-chip LC665XX series microcomputers. Either 2764 or 27128 type EPROM can be mounted on the LC66PG5XX. The LC66PG5XX with the EPROM mounted can carry out the same functions as those of the LC665XX series microcomputers. Therefore, you can evaluate programs developed for application products controlled by the LC665XX series microcomputers by incorporating the LC66PG5XX into the applications before the programs are masked in the ROMs. Features • Either 2764 or 27128 type EPROM can be mounted. • Shrink type 64-pin configuration compatible with the LC665XX series microcomputers. Note that pull-up resistors need to be externally added. • Options provided for selecting functions. Options allowing the user to select output signal level for ports 0, 1 and 8 at the initial reset or to specify whether the watchdog timer function is employed by setting external pin levels • Instruction cycle time 0.92 to 10 microseconds. • +5V single power source. The LC66PG5XX has the 28-pin soket and 14-pin soket on the top face of the package. It also has the shrink type 64-pin terminals on the bottom face of the package. The 28-pin soket is used for mounting the EPROM containing the programs and 14-pin soket for selecting functions by options (input/output options not included). The shrink type 64-pin terminals are compatible with the LC665XX series microcomputers. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N3001TN (KT)/7317KI, TS No.2648–1/14 LC66PG5XX Configurations of the LC665XX series microcomputers Model name LC66506A LC66508A LC66512A LC66516A LC66PG5XX LC66599 ROM capacity 6KB 8KB 12KB 16KB 16K bytes. Externally added 16K bytes. Externally added RAM capacity 512× 4 512× 4 512× 4 512× 4 512× 4 512× 4 Package DIP64S FLP64 ← ← ← DIC64S PGA120 Remarks Available ← ← ← Piggyback EVA chip Notes on use The LC66PG5XX is a product for developing and evaluating programs for the LC665XX series microcomputers. Keep always in mind the following considerations when using the LC66PG5XX. 1. The operating conditions are different from those of the production mask ROM . It is not recommended that the LC66PG5XX is used under the environmental conditions including high temperature and terrible humidity. 2. The electric characteristics are not the same as those of the production mask ROM. To evaluate strictly the electric characteristics at the interface with external circuits, use the recommended electric characteristics values of the production mask ROM. 3.The discrepancy in internal circuit pattern configuration between the LC66PG5XX and the production mask ROM results in the following differences between them. •Differrent initial values are set in RAMs at power ON. •Differrent noise figures (NF) are recorded. That is, the static noise intensity of the LC66PG5XX is different from that of the production mask ROM. Keep it always in mind. External dimension No.2648–2/14 LC66PG5XX Overview of terminal function Terminal name P00 Input/ output I/O P01 Input/output port P00 to P03 LC66PG5XX output format •Nch OD output I/O Input/output port P10 to P13 •Nch OD output •Data input and output in 4-bit units or in 1- H or L (optional) •Output level at initial reset P13 P20/SI0 •Pull-up MOS or Nch OD output bit units. P12 H or L (optional) reset •P00 to P03 used for controlling HALT mode. P11 •Pull-up MOS or Nch OD At initial reset •Output level at initial bit units. P03 Option (production chip) (open drain) output •Data input and output in 4-bit units or in 1- P02 P10 Function I/O Input/output port P20 to P23 •Nch OD output •Data input and output in 4-bit units or in 1- P21/SO0 •CMOS or Nch OD H output bit units. P22/SCK0 •P20 also used as SI0 terminal for serial P23/INT0 input. •P21 also used as SO0 for serial output. •P22 also used as SCK0 for serial clock signal input/output. •P23 also used as INT0 terminal for INT0 interrupt request input . In addition, it is used for timer 0 event count input and pulse width measurement input. P30/INT1 I/O Input/output port P30 to P32 •Nch OD output •Data input and output in 3-bit units or in 1- P31/POUT0 •CMOS or Nch OD H output bit units. P32/POUT1 •P30 also used as INT1 terminal for INT1 interrupt request signal. •P31 also used for burst pulse signal output from timer 0. •P32 also used for burst pulse signal output from timer 1 and PWM signal output. P33/HOLD I HOLD mode control input. – – – •Pull-up MOS or Nch OD H •When HOLD=L, HOLD mode to be set by the HOLD instruction. •During HOLD mode "ON", restart up to the CPU by applying "H"-level signal to the HOLD terminal. •Also used as input port P33 if used together with port P30 to P32. •CPU not to be reset even if "L"-level signal is applied to the RES terminal with the P33/HOLD set to "L". The output level of the P33/HOLD terminal at power ON must not be set "L"on your application products. P40 P41 P42 P43 I/O Input/output port P40 to P43 •Data input and output in 4-bit units and 1-bit •Nch OD output output units. •Also used for data input/output in 8-bit units if jointly used with port P50 to P53. •Used for ROM data output in 8-bit units if jointly used with port P50 to P53. Continued on next page No.2648–3/14 LC66PG5XX Continued from preceding page Terminal name P50 Input/ output I/O Function Input/output port P50 to P53 LC66PG5XX output format •Nch OD output •Data input/output in 4-bit units and 1-bit P51 Option (production chip) At initial reset •Pull-up MOS or Nch OD H output unit. P52 •Used for input/output in 8-bit units if jointly P53 used with port P40 to P43. •Used for ROM data output in 8-bit units if jointly used with port P40 to P43. P60/SI1 I/O Input/output port P60 to P63 •Nch OD output •Data input/output in 4-bit units and 1-bit P61/SO1 •CMOS or Nch OD H output units. P62/SCK1 •P60 terminal also used as terminal SI1 for P63/PIN1 serial input. •P61 terminal also used as terminal SO1 for serial output. •P62 terminal also used as terminal SCK1 for serial clock signal input/output. •P63 terminal also used for event count input to timer 1. P70 O Output port P70 to P73 P71 •Data output in 4-bit units and in 1-bit units. P72 •The contents of output latch circuit to be •Pull-up MOS or Nch OD H output input with input-related instructions. P73 P80 •Nch OD output O Output port P80 to P83 P81 •Data output in 4-bit units and in 1-bit units. P82 •The contents of output latch circuit to be •Pch OD output (optional) output •Output level at the initial input with input-related instructions. P83 H or L •CMOS or Pch OD reset •Pch OD output option available. P90/INT2 I/O P91/INT3 Input/output port P90 to P93 •Nch OD output P92/INT4 •CMOS or Nch OD H output •Data input and output in 4-bit units and in 1bit units. P93/INT5 •P90 also used as the INT2 terminal for INT2 interrupt request input. •P91 also used as the INT3 terminal for INT3 interrupt request input. •P92 also used as the INT4 terminal for INT4 interrupt request input. •P93 also used as the INT5 terminal for INT5 interrupt request input. PA0 O Output port PA0 to PA3 PA1 •Data output in 4-bit units and in 1-bit units. PA2 •The contents of output latch circuit to be PB1 PB2 PB3 •Pull-up MOS or Nch OD H output input with input-related instructions. PA3 PB0 •Nch OD output O Output port PB0 to PB3 •Data output output in 4-bit units and in 1-bit •Nch OD output •Pull-up MOS or Nch OD H output units. •The contents of output latch circuit to be input with input-related instructions. Continued on next page No.2648–4/14 LC66PG5XX Continued from preceding page Terminal name PC0 Input/ output I/O PC1 Function Input/output port PC0 to PC3 LC66PG5XX output format •Nch OD output •CMOS or Nch OD At initial reset H output •Data input and output in 4-bit units and in PC2/VREF0 Option (production chip) 1-bit units. PC3/VREF1 •PC2 also used as the VREF0 terminal for reference voltage input. •PC3 also used as the VREF1 terminal for reference voltage input. PD0/CMP0 I PD1/CMP1 Input port PD0 to PD3 – – Normal input – – Normal input •Can be selected as comparator input PD2/CMP2 terminals on programs. PD3/CMP3 PD0 : reference voltage input (VREF0). PD1 to PD3 : reference voltage input (VREF1) •PD0, PD1 (PD2 to PD3) selectable as comparator input ports on programs in this unit. PE0/TRA I Input port •Selectable as three-state input port on PE1/TRB programs. OSC1 I Terminals for system clock oscillator OSC2 O externally added. – •Ceramic resonator – oscillation, RC (resistor •Leave OSC2 open and close OSC1 for and capacitor) or external clock signal input when external external clock selection. clock mode is selected. RES I Terminal for system reset signal input. – – – – – – – – – •CPU to be initialized when P33/HOLD="H" plus "L" level voltage is applied to the RES terminal. TEST I Terminal for CPU test signal input. •Always connected to VSS during operation. VDD – Power source terminal VSS No.2648–5/14 LC66PG5XX LC66PG5XX special terminals Terminal name Input/ output Output type Function P0HL P1HL P8HL I – Terminals for signal input to select output level at ports 0, 1 and 8 at the RAMC0 I – Terminal for signal input to control RAM capacity. I – Terminal for signal input to contorol whether the watchdog timer reset. "H" level output to be selected if "H" level signal is input to the terminals. RAMC1 WDC function is used. The watchdog timer function to be selected if "H" level signal is input. CP1 O Pu MOS output Terminal for signal output to select clock signal edge for output latch of extended ports. IM0 to IM7 I – Terminals for instruction input from external circuits. PM0 to PM13 O Pu MOS output Terminals for PC output to external circuits. CE O Pu MOS output Terminal for signal output to contorol the CE terminal of memory externally added. Remarks : Pu MOS output ................. Pull-up MOS transistor output. CMOS output .................... Complementary MOS output. OD output .......................... Open drain output. How to mount and use EPROM on the LC66PG5XX You write assembled program data into an EPROM and mount it on the LC66PG5XX. To write data into the EPROM, you can use the EPROM writer function of the EVA-800. No.2648–6/14 LC66PG5XX Power source for EPROM Normal current drain per EPROM is in the range of 50mA and 100mA. When power capacity of an application product is not sufficient, power can be supplied to the EPROM from external independent power source. That is, the power source which is different from that on the application system can be selected. At the factory shipment, the +5V pin and VDD pin are connected on the LC66PG5XX. Therefore, power is supplied to the EPROM from the LC66PG5XX power source terminal (pin64). Of the power source pads on the package surface, +5V pad is used to supply power to the EPROM. Note The LC66PG5XX is a CMOS type IC. This reminds us that latch-up may be caused by input voltage level below the VSS level or above the VDD level. The latch-up is specific to this type of IC and destroys IC device structure or adversely affects operating functions. You should be careful about the voltage level range of the LC66PG5XX and EPROM. To start the LC66PG5XX and EPROM operation, first turn on the LC66PG5XX and then the EPROM. To stop the LC66PG5XX and EPROM operation, first turn off the EPROM and then the LC66PG5XX. Function selection by options Select the port 0, port 1 or port 8 output level at the reset, watchdog timer function and internal RAM capacity according to the options and functions of the microcomputer to be evaluated. Set as below pins 1 to 6 of the 14-pin socket on the package surface. Function type Pin No. Pin name Port 0, port 1 and Port 8 output level at reset 1 2 3 P0HL P1HL P8HL Watchdog timer 6 Pin setting Function mode ON Port output level "H" OFF Port output level "L" ON Operation OFF Stop WDC Pin setting RAM capacity Internal RAM capacity 4 5 RAMC0 RAMC1 RAMC1 RAMC0 OFF OFF OFF ON ON OFF ON ON No setting for the LC665XX series microcomputers 512W ON : +5V voltage input, OFF : Open. Pins 14, 13, 12, 11, 10 and 9 of the 14-pin socket are assigned as the +5V terminals. These terminals can be used only for supplying +5V voltage to the pins 1, 2, 3, 4, 5, and 6. Note that pin 8 is reserved for future use and should be left open. No.2648–7/14 LC66PG5XX Notes on use 1. The port output format for the LC66PG5XX is as follows : The Pch OD format is employed only for port 8. The Nch OD format is employed for the rest. Add resistors to each port according to the port output formats employed for production chips. •When optional pull-up resistors are selected for ports P0, P1, P4, P5, P7, PA and PB, add resistors of about 10kΩ to them and connect the port to the VDD terminal. •When the optional CMOS output format is selected for port P8, add the resistor of about 1kΩ to it and connect the port to the VSS terminal. Select the resistor in the range of 0.5kΩ to 10kΩ according to load balance. •When the optional CMOS output format is selected for ports P2, P3 (P33 not included), P6, P9 and PC, add the resistors of about 10 kΩ to them and connect them to the VDD terminal. (add the resistors of more than 1 kΩ if sink current is used.) 2. The LC66PG5XX has no feedback resistors. Add the external feedback resistor of about 1 MΩ to the LC66PG5XX when the ceramic resonator oscillation is selected. The external capacitance is the same as that of production chips. 3. The constants and oscillation characteristics of the RC (resistor and capacitor) oscillation circuit are different from those of production chips. Set them to the oscillation frequency of production chips by making adjustments to volume resistor. 4. The operating voltage level of the LC66PG5XX must be within the range of the operating voltage of the EPROM and other ICs. That is, the level is : VDD=5Vwith 5% margin. 5. The operating environment temperature is in the range of 10°C to 40°C. Absolute maximum ratings at Ta = 25˚C, VSS = 0V Parameter Maximum voltage level Input voltage Symbol VDD max VIN1 VIN2 Output voltage VOUT1 VOUT2 Terminal and note Condition VDD P2, P3(P33/HOLD not included), P6 Other inputs P2, P3(P33/HOLD not included), P6, P7 and PA Other outputs Ratings Unit Note –0.3 to +7.0 V –0.3 to +15.0 V 1 –0.3 to VDD+3.0 V 2 –0.3 to +15.0 V 1 –0.3 to VDD+3.0 V 2 mA 3 20 mA 3 4 mA 4 75 mA 3 75 mA 3 25 mA 4 600 mW P0, P1, P2, P3(P33/HOLD not ION1 Total terminal current included), P4, P5, P6, P8, P9 and 4 PC Output current per terminal ION2 P7, PA, PB –IOP2 P8 ∑ION1 P2, P3(P33/HOLD not included), ∑ION2 P0, P1, P9, PA, PB, PC P4, P5, P6, P7 and P8 –∑IDP1 8 Allowable power dissipation Pd max Ta=10 to 40° C Operating temperature Topr +10 to +40 °C Storage tempurature Tstg +55 to +125 °C DIC-64S Note 1: Applicable only when open drain output format is selected. If the format is not selected, another standard value is used. Note 2: The self oscillation voltage level can be included in the standard value range as far as oscillation input/output is concerned. Note 3: Sink current (applicable to P8 only when CMOS output format is selected). Note 4: Source current (applicable to terminals other than P8 only when pull-up output format or CMOS output format is selected). No.2648–8/14 LC66PG5XX Recomemended operating conditions at Ta = 10˚C to 40˚C, VSS = 0V, unless otherwise specified Codnitions Parameter Operating power Symbol Terminal Ratings VDD(V) VDD VDD Memory hold voltage VDDH VDD HOLD mode High-level input voltage VIH1 P2, P3 (33/HOLD Output Nch Tr OFF min typ 4.0 Unit Note max 5.0 6.0 V 1.8 6.0 V 4.0 to 6.0 0.75VDD +13.5 V 1 Output Nch Tr OFF 4.0 to 6.0 0.75VDD VDD V 2 Output Nch Tr OFF 4.0 to 6.0 0.7VDD VDD V 3 voltage not included),P6 VIH2 P33/HOLD P9, RES, OSC1 VIH3 P0, P1, P4, P5, PC, PD, PE Medium-level input VIH4 PE 3-state input format 4.0 to 6.0 0.8VDD VDD V VIM PE 3-state input format 4.0 to 6.0 0.4VDD 0.6VDD V VCMM PD, PC2, PC3 Comparator input 4.0 to 6.0 1.0 VDD–1.5 V 4.0 to 6.0 VSS 0.25VDD V 1.8 to 6.0 VSS 0.25VDD V Output Nch Tr OFF 4.0 to 6.0 VSS 0.3VDD V 3-state input format 4.0 to 6.0 VSS 0.2VDD V voltage In-phase input voltage range mode Low-level input voltage VIL1 P2, P3 (33/HOLD Output Nch Tr OFF 2 not included),P6, P9, RES, OSC1 VIL2 P33/HOLD VIL3 P0, P1, P4, P5, 3 PC, PD, PE, TEST VIL4 fop (instruction cycle time) (Tcyc) Externanl clock pulse input condition Operating frequency Frequency 4.0 to 6.0 OSC1 0.4 4.35 MHz (10) (0.92) (µs) 4.0 to 6.0 0.4 4.35 MHz Same as sbove. 4.0 to 6.0 7.0 Same as sbove. 4.0 to 6.0 See Figure 1. Input to the OSC1 terminal. OSC2 terminal left open. Pulse width textH ns textL Fall/rise time textR 30 ns textF Ceramic resonator oscillation Frequency Self osillation conditions fext PE Oscillation fCF OSC1, OSC2 fCFS See Figure 2. 4MHz 4.0 to 6.0 See Figure 3. 4MHz 4.0 to 6.0 MHz 4.0 10 ms stabilization time External RC Cext oscillation Rext OSC1, OSC2 See FIgure 4. 4.0 to 6.0 100 pF 2.2 kΩ constants Note 1: Applicable to terminals with open drain output format. VIH2 applied to P33/HOLD terminal. Note 2: Applicable to terminals with open drain output format. Note 3: VIH4, VIM and VIL4 applied when PE is used for 3-state input operation. No.2648–9/14 LC66PG5XX Electric characteristics at Ta = 10˚C to 40˚C, VSS = 0, unless otherwise specified Codnitions Parameter Symbol High-level input current IIH1 IIH2 Terminal Ratings VDD(V) P2, P3 (33/HOLD VIN =13.5V not included),P6 Output Nch Tr OFF P0, P1, P4, P5, P9 VIN =VDD PC, OSC1, RES, Output Nch Tr OFF min typ Unit Note max 4.0 to 6.0 +5.0 µA 1 4.0 to 6.0 +1.0 µA 1 +1.0 µA 1 P33/HOLD (PD, PE, PC2 and PC3, not included) Low-level input current IIH3 PD, PE, PC2, PC3 VIN=VDD Output Nch Tr OFF 4.0 to 6.0 IIL1 Input level to VIN=VSS 4.0 to 6.0 –1.0 µA 2 terminals other Output Nch Tr OFF 4.0 to 6.0 –1.0 µA 2 IOH= –1mA 4.0 to 6.0 VDD–1.0 V IOH= –0.1mA 4.0 to 6.0 VDD–0.5 than PD, PE, PC2 and PC3 IIL2 PC2, PC3, PD, PE VIN=VSS Output Nch Tr OFF High-level output voltage VOH1 P8 Low-level output voltage P0, P1, P2, P3, P4, IOL= 1.6mA P5, P6, P9, and PC VOL1 4.0 to 6.0 0.4 V (P33/HOLD not included) Output off leak current VOL2 P7, PA, PB IOL= 10mA 4.0 to 6.0 1.5 V IOFF1 P2, P3, P6, P7, PA VIN=13.5V 4.0 to 6.0 5.0 µA 6 IOFF2 (P2, P3, P6, P7, P8 VIN=VDD 4.0 to 6.0 1.0 µA 6 µA 7 and PA not included) Comparator offset IOFF3 P8 VIN=VSS 4.0 to 6.0 VOFF PD VIN=1.0V to VDD–1.5V 4.0 to 6.0 ±50 VHYS P2, P3, RES, P6, 4.0 to 6.0 0.1VDD voltage Hysteresis voltage –1.0 ±300 mV V Schmidt characteristics P9 and OSC1. VtH High-level threshold voltage Low-level OSC1 for external clock signal input. VtL 0.75VDD 0.25VDD 0.5VDD threshold voltage RC (resistor and fRC OSC1, OSC2 4.0 to 6.0 2.0 See the timing shown 4.0 to 6.0 0.92 µs in Figure 5 and the 4.0 to 6.0 2.0 Tcyc 4.0 to 6.0 0.4 µs 1.0 Tcyc See Figure 4. capacitor) oscillation Cext=100pF±5% frequency) Rext=2.2kΩ±1% Cycle time Serial clock 0.5VDD Input tCKCY Outnput Low-level/ Input tCKL high-level/ pulse width Outnput tCKH Fall/rise time Input SCK0, SCK1 test load in Figure 6. 4.0 to 6.0 3.0 4.0 tCKR 4.0 to 6.0 3.0 Outnput tCKF 4.0 to 6.0 0.1 MHz µs Continued on next page No.2648–10/14 LC66PG5XX Continued from preceding page Codnitions Serial input Parameter Symbol Data setup time tICK Data hold time tCKI Terminal SI0, SI1 Ratings VDD(V) min Unit typ Note max See Figure 5 "Serial 4.0 to 6.0 0.3 µs input/output timing" 4.0 to 6.0 0.3 µs Synchronized with the rise (↑) of the SCK0 and SCK1 signals. Output delay time tCKO See Figure 5 "Serial SO0, SO1 4.0 to 6.0 0.3 µs Serial output input/output timing" and Figure 6 "Timing load". Synchronized with the fall (↓) of the SCK0 and SCK1 signals. INT0 high-level/ tI0H low-level/pulse tI0L INT0 See Figure 7. width •When INT0 interrupt 4.0 to 6.0 2 Tcyc 2 Tcyc 2 Tcyc 3 Tcyc is accepted. •When timer 0 event Pulse input conditions counter/pulse width measure input is accepted. Interrupt input to tI1H INT1, INT2 terminals other tI1L INT3, INT4 than INT0. High- •When each interrupt is accepted. INT5 level/low-level/ pulse width. PIN1 high-level/ tPINH low-level/pulse tPINL •When timer 1 event PIN1 counter input is accepted. width RES high-level/ tRSH low-level/pulse tRSL •When reset signai is RES accepted. width Comparator response TRS PD 30 µs 4.5 8 mA 8 4MHz external clock 6.5 11 RC oscillation 4.0 8 1.0 2.5 mA 9 2 3.5 1.2 2.5 0.01 10 µA 9 See 4.0 to 6.0 Figure speed 8. Operating mode current IDDop VDD drain 4MHz ceramic 4.0 to 6.0 resonator oscillation HALT mode current IDDHALT VDD drain 4MHz ceramic 4.0 to 6.0 resonator oscillation 4MHz external clock RC oscillation HOLD mode current IDDHOLD VDD 1.8 to 6.0 drain Note 1: Note 2: Note 6: Note 7: Note 8: Note 9: Open drain output format and output Nch Tr OFF for input/output common ports. Open drain output format and output Nch Tr OFF for input/output common ports. Open drain output format and output Nch Tr OFF. Open drain output format and output Pch Tr OFF. Reset status. EPROM current drain not included. EPROM current drain not included. No.2648–11/14 LC66PG5XX Fig. 1 External clock input waveform (1) Capacitor externally connected type (2) Capacitor contained type Fig. 2 Ceramic resonator oscillation circuit Capacitor contained type Capacitor externally connected type 4MHz (Murata) Fig. 3 Oscillation stable time C1 33pF±10% C2 33pF±10% C1 33pF±10% C2 33pF±10% CSA4.00MG 4MHz (Kyocera) KBR4.0MS 4MHz CST4.00MG (Murata) 4MHz KBR-4.0MES (Kyocera) Table1 : Recommended ceramic resonator constants Fig. 4 RC oscillation No.2648–12/14 LC66PG5XX Fig. 6 Test Loads Fig. 5 Serial input/output timing Fig. 7 INT0, INT1, INT2, INT3, INT4, INT5, PIN1, RES input timing Fig. 8 Comparator response Trs timing No.2648–13/14 LC66PG5XX Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2001. Specifications and information herein are subject to change without notice. PS No.2648–14/14