SANYO LV8224FN

Ordering number : ENN7813
SANYO Semiconductors
DATA SHEET
Bi-CMOS IC
LV8224FN
Motor driver system in CD and MD players
Overview
The LV8224FN is a system motor driver IC that implements all the motor driver circuits needed for CD and MD
products. The LV8224FN provides a three-phase PWM spindle driver, a sled driver (either three-phase or PWM H
bridge operation can be selected), and focus and tracking drivers (as two PWM H bridge driver channels). Since the
LV8224FN uses BICDMOS devices, it can contribute to further miniaturization, thinner from factors, and lower power
in end products.
The adoption of the direct PWM sensorless drive method for the spindle driver makes it possible to implement highefficiency motor drive with few external parts.
Functions
• PWM H bridge motor drivers (2 channels)
• Three-phase stepping motor driver, and direct PWM sensorless motor driver
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Supply voltage
Conditions
Ratings
Unit
VCC max
5.0
Output block supply voltage
VS max
4.5
V
Predriver voltage (gate voltage)
VG max
6.5
V
Output current
IO max
Pd max1
Allowable power dissipation
Pd max2
Independent IC
Mounted on a 50.0 × 50.0 × 0.8 mm glass epoxy
PCB (reference value)
V
0.8
A
0.35
W
1.10
W
Operating temperature
Topr
–30 to +85
°C
Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Supply voltage
Conditions
Ratings
VCC
Unit
1.9 to 4.0
V
Output block supply voltage
VS
0 to VG – 3.0
V
Predriver voltage (gate voltage)
VG
VS + 3 to 6.3
V
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
62504TN (OT) No. 7813-1/16
LV8224FN
Electrical Characteristics at Ta = 25°C, VCC = 2.3 V
Parameter
Symbol
Conditions
Current drain 1
ICC1
S/S pin: high
Current drain 2
ICC2
S/S pin: low (standby mode)
Ratings
min
typ
Unit
max
1.0
1.5
mA
20
µA
6.2
V
mV
[Charge Pump Output]
Output voltage
VG
5.4
Input offset voltage
VAOFS
–9
+9
Common-mode input voltage range
VACM
0
VCC
V
High-level output voltage
VACH
IO = –0.5 mA
VCC – 0.5
VCC
V
Low-level output voltage
VACL
IO = 0.5 mA
0.5
V
0.4
0.6
Ω
0.4
0.6
Ω
Ω
5.9
Actuator Block
[Position Detector Comparator Block]
[Output Block] (OUT1F/R, OUT2F/R, and SUO to SWO pins)
SOURCE1
Ron (H1)
SOURCE2
Ron (H2)
Forward transistor
IO = 0.5 A, VS = 1.2 V, VG = 6 V,
Reverse transistor
Ron (L)
IO = 0.5 A, VS = 1.2 V, VG = 6 V
0.4
0.6
Ron (H+L)
IO = 0.5 A, VS = 1.2 V, VG = 6 V
0.8
1.2
Ω
SINK
SOURCE + SINK
IO = 0.5 A, VS = 1.2 V, VG = 6 V,
Output transmission delay time
TRISE
Design target value*
0.1
1.0
µs
(H bridge)
TFALL
Design target value*
0.1
0.7
µs
Minimum input pulse width
(H bridge)
tmin
With the channel 1 and channel 2 pulse
widths ≥ 2/3 tmin, Design target value*
200
ns
[Decoder and Actuator Input Pins] (IN1F/R, IN2F/R, and S1 to S3 pins)
High-level input voltage range
VIH
VCC – 0.5
VCC
V
Low-level input voltage range
VIL
0
0.5
V
High-level actuator input pin current
IINH
When the input pin voltage is 2.3 V
9.5
13
µA
Low-level actuator input pin current
IINL
When the input pin voltage is 0 V
1
µA
[MUTE Pin]
High-level input voltage range
VMUH
MUTE OFF
Low-level input voltage range
VMUL
MUTE ON
High-level input pin current
IMUTEH
When the input pin voltage is 2.3 V
Low-level input pin current
IMUTEL
When the input pin voltage is 0 V
*: Design target value parameters are not tested.
VCC – 0.5
VCC
V
0
0.5
V
9.5
13
µA
1
µA
Continued on next page.
No.7813-2/16
LV8224FN
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Spindle Motor Driver Block
[Output Block]
SOURCE1
Ron (H1)
SOURCE2
Ron (H2)
SINK
SOURCE + SINK
IO = 0.5 A, VS = 1.2 V, VG = 6 V,
Forward transistor
IO = 0.5 A, VS = 1.2 V, VG = 6 V,
Reverse transistor
0.4
0.6
Ω
0.4
0.6
Ω
Ron (L)
IO = 0.5 A, VS = 1.2 V, VG = 6 V
0.4
0.6
Ω
Ron (H+L)
IO = 0.5 A, VS = 1.2 V, VG = 6 V
0.8
1.2
Ω
[Position Detector Comparator]
Input offset voltage
VSOFS
–9
OSC pin high-level voltage
VOSCH
0.85
1.05
1.25
V
OSC pin low-level voltage
VOSCL
0.40
0.60
0.80
V
9
mV
[Startup Oscillator Pin]
[S/S Pin]
High-level input voltage range
VSSH
Start
VCC – 0.5
VCC
V
Low-level input voltage range
VSSL
Stop
0
0.5
V
High-level input pin current
ISSH
When the input pin voltage is 2.3 V
9.5
13
µA
Low-level input pin current
ISSL
When the input pin voltage is 0 V
1
µA
High-level input voltage range
VBRH
Brake off
VCC – 0.5
VCC
V
Low-level input voltage range
VBRL
Brake on
0
0.5
V
High-level input pin current
IBRKH
When the input pin voltage is 2.3 V
9.5
13
µA
Low-level input pin current
IBRKL
When the input pin voltage is 0 V
1
µA
[BREAK Pin]
[PWM Pin]
High-level input voltage range
VPWMH
VCC – 0.5
VCC
V
Low-level input voltage range
VPWML
0
0.5
V
High-level input pin current
IPWMH
When the input pin voltage is 2.3 V
9.5
13
µA
Low-level input pin current
IPWML
When the input pin voltage is 0 V
1
µA
190
kHz
PWM input frequency
VPWMIN
[CLK Pin]
High-level input voltage range
VCLKH
VCC – 0.5
VCC
V
Low-level input voltage range
VCLKL
0
0.5
V
High-level input pin current
ICLKH
When the input pin voltage is 2.3 V
9.5
13
µA
Low-level input pin current
ICLKL
When the input pin voltage is 0 V
1
µA
High-level output voltage
VFGH
IO = –0.5 mA
VCC
V
Low-level output voltage
VFGL
IO = 0.5 mA
0.5
V
[FG Output Pin]
VCC – 0.5
Package Dimensions
unit : mm
3272
Pd max — Ta
BOTTOM VIEW
0.2
7.2
7.0
36
25
0.3
5.0
5.0
0.3
7.0
7.2
48
0.4
24
37
13
1
12
0.5
0.2
SIDE VIEW
(0.8)
0.85max
(0.75)
0.4
SANYO : VQFN48 (7 × 7)
Allowable power dissipation, Pdmax — W
1.5
TOP VIEW
(50.0 × 50.0 × 0.8 mm glass epoxy PCB)
Mounted on a thermal resistance evaluation PCB
1.1
1.0
0.57
0.5
Independent IC
0.35
0.18
0
–20
0
20
40
60
Ambient temperature, Ta — °C
80
100
ILV00175
No.7813-3/16
LV8224FN
Actuator Truth Tables
Focus and Tracking Blocks
MUTE
IN1, 2F
IN1, 2R
OUT1, 2F
H
L
L
L
OUT1, 2R
L
H
H
L
H
L
H
L
H
L
H
H
H
H
L
L
L
×
×
Z
Z
Sled Drive Block Stepping Drive Mode (When the 3/H pin (pin 47) is high)
MUTE
S1
S2
S3
SUO
SVO
SWO
H
L
L
L
H
L
Z
H
H
L
L
H
Z
L
H
L
H
L
Z
H
L
H
H
H
L
L
H
Z
H
L
L
H
L
Z
H
H
H
L
H
Z
L
H
H
L
H
H
Z
Z
Z
H
H
H
H
Z
Z
Z
L
×
×
×
Z
Z
Z
Z: Open
Sled Drive Block H Bridge Drive Mode (When the 3/H pin (pin 47) is low)
MUTE
S1
S2
SUO
SVO
MUTE
S3
H
L
L
L
L
H
L
SWO
L
H
H
L
H
L
H
H
H
H
L
H
L
H
L
×
Z
H
H
H
L
L
L
×
×
Z
Z
Z: Open
Notes:
When the 3/H pin is set to select H bridge mode, SUO and SVO operate as PWM H bridge outputs according to the S1 and S2 inputs, and SWO operates
as a half-bridge circuit output according to the S3 input.
No.7813-4/16
LV8224FN
SVO
SUO
OUT2R
PGND2
VS2
OUT2F
OUT1R
PGND1
VS1
OUT1F
WOUT
VOUT
Pin Assignment VQFN48 (7 × 7)
36
35
34
33
32
31
30
29
28
27
26
25
24
UOUT
23
SPGND
39
22
SPVS
CLK
40
21
IN1F
CP2
41
20
IN1R
CP1
42
19
IN2F
CPC1
43
18
IN2R
CPC2
44
17
MUTE
VG
45
16
GND
VCC
46
15
PWM
3/H
47
14
BRK
SUCO
48
13
S/S
1
2
3
4
5
6
7
8
9
10
11
12
S2
S3
SLCOM
SPCOM
SPCIN
SPFIL
SOFT
OSC
SLVS
LV8224FN
S1
38
SPFG
SLGND
SWCO
37
SVCO
SWO
Top view
No.7813-5/16
LV8224FN
Pin Functions
Pin No.
Pin Name
Pin Description
48
1
2
SUCO
SVCO
SWCO
Sled driver block position detector comparator outputs
3
SPFG
FG pulse output.
This pin outputs a three Hall sensor system equivalent
pulse signal.
Equivalent circuit
VCC
4
5
6
S1
S2
S3
200 kΩ
VCC
Three-phase sled block logic inputs. Pins 35, 36, and 37
are the corresponding outputs.
10 kΩ
VG
7
SLCOM
Sled driver block position detector comparator common
input
1 kΩ
7
VCC
11
SOFT
Spindle driver block drive current waveform selection. Set
this pin low when using a cored motor and high when
using a coreless motor.
10 kΩ
11
VCC
12
OSC
Startup oscillator connection. When this pin is connected
to VCC, the startup frequency will be equivalent to
fCLK/4096, and connected to ground, that frequency will be
fCLK/3072. If any other startup frequency is to be set,
insert a capacitor between this pin and ground. The
startup frequency can be set freely by changing the value
of the capacitor.
500 Ω
12
500 Ω
Continued on next page.
No.7813-6/16
LV8224FN
Continued from preceding page.
Pin No.
Pin Name
Pin Description
Equivalent circuit
VG
8
SPCOM
Spindle motor common point connection
200 kΩ
SPCIN
Position detector comparator differential input.
Insert a capacitor between this pin and the SPFIL pin
(pin 10).
12 kΩ
9
9
1 kΩ
8
VG
200 kΩ
Waveform synthesis signal filter connection.
Insert a capacitor between this pin and the SPCIN pin
(pin 9).
SPFIL
13
S/S
Spindle motor block start/stop control. A high-level input
sets the block to start mode.
14
BRK
Spindle motor block braking control. A low-level input sets
the block to reverse torque braking.
15
PWM
PWM signal input. The output transistor is on when this
input is high.
17
MUTE
Muting control for the H bridge 1 and 2 blocks and the sled
driver block.
When a low level is input, these channel outputs all go to
the high-impedance state.
21, 20
19, 18
IN1F/R
IN2F/R
Actuator H bridge block logic inputs
40
CLK
Logic circuit operation reference clock input. Supply a
frequency 32 times that of the spindle PWM frequency.
16
GND
Small-signal system circuit ground
10
12 kΩ
10
VCC
200 kΩ
10 kΩ
Continued on next page.
No.7813-7/16
LV8224FN
Continued from preceding page.
Pin Name
Pin Description
22
SPVS
Spindle motor drive power supply. Insert a capacitor
between this pin and ground.
24
25
26
UOUT
VOUT
WOUT
Spindle driver outputs. Connect these pins to the spindle
motor.
23
SPGND
Spindle output block ground
Equivalent circuit
22
1 kΩ
25
1 kΩ
24
26
1 kΩ
Pin No.
23
28
28
27, 30
29
VS1
OUT1F/R
PGND1
H bridge 1 output block.
Insert a capacitor between the VS1 pin (pin 28) and
ground.
27
30
31
34
29
32
32
31, 34
33
VS2
OUT2F/R
PGND2
H bridge 2 output block.
Insert a capacitor between the VS2 pin (pin 32) and
ground.
33
SLVS
35
36
37
SUO
SVO
SWO
38
SLGND
39
Sled motor drive power supply.
Insert a capacitor between this pin and ground.
Sled driver outputs. Connect these pins to the sled motor.
36
1 kΩ
1 kΩ
35
37
1 kΩ
39
38
Sled output block ground
42
CP1
Charge pump step-up pulse output. Insert a capacitor
between this pin and the CPC1 pin (pin 43). Leave this pin
open when using this circuit as a 2× step-up circuit.
41
CP2
Charge pump step-up pulse output. Insert a capacitor
between this pin and the CPC2 pin (pin 44).
42
41
VCC
Continued on next page.
No.7813-8/16
LV8224FN
Continued from preceding page.
Pin No.
Pin Name
43
CPC1
Pin Description
Charge pump step-up connection. Insert a capacitor
between this pin and the CP1 pin (pin 42).
Equivalent circuit
43
VCC
44
45
Charge pump step-up connection. Insert a capacitor
between this pin and the CP2 pin (pin 41).
44
CPC2
45
VG
Charge pump stepped up voltage output.
Insert a capacitor between this pin and ground.
46
VCC
Small-signal system power supply.
Insert a capacitor between this pin and ground.
VCC
47
3/H
Sled drive mode selection. A high-level input selects
three-phase stepping mode, and a low-level input selects
H bridge + half bridge mode. This pin must not be left
open.
1 kΩ
47
1 kΩ
No.7813-9/16
LV8224FN
Block Diagram
PGND2 VS2 OUT2R
OUT2F IN2R IN2F OUT1R
OUT1F IN1R IN1F
VS1
PGND1
Pre driver
Logic
Pre driver
Logic
MUTE
LV8224FN
VCC
VG
CP1
GND
Charge
pump
CPC1
CP2
1/N
CPC2
SUCO
SVCO
SWCO
CLK
S/S
Waveform
distributor
BRK
SOFT
3/H
OSC
SEL
S1
S2
S3
SLCOM
Logic
SEL
OSC
CIN
Sensorless logic
FIL
Waveform
synthesizer
Spindle pre driver
Sled pre driver
Waveform
synthesizer
SPCOM
SLVS
SPVS
SUO
SVO
SWO
UOUT
VOUT
WOUT
SPGND
SLGND
SPFG PWM
No.7813-10/16
LV8224FN
Sample Application Circuit 1
VS
Sled
motor
Spindle
motor
35
34
33
32
31
30
29
28
27
26
25
SVO
OUT2R
PGND2
VS2
OUT2F
OUT1R
PGND1
VS1
OUT1F
WOUT
VOUT
37 SWO
SPVS 22
39 SLVS
40 CLK
IN1F 21
41 CP2
IN1R 20
LV8224FN
42 CP1
IN2F 19
43 CPC1
IN2R 18
44 CPC2
MUTE 17
5
DSP
Notes
• Startup with automatic oscillation mode
• Sled three-phase stepping mode
• Cored motor spindle motor mode
SOFT
4
SPFIL
3
SPCIN
2
SPCOM
1
OSC
6
7
8
9
10
11
12
To the spindle motor
SVCO
48 SUCO
SLCOM
BRK 14
To the sled motor
47 3/H
S2
PWM 15
S1
46 VCC
SPFG
GND 16
SWCO
45 VG
S3
DSP
UOUT 24
SPGND 23
38 SLGND
VS
To SPCOM
36
SUO
To SLCOM
VS
VS
DSP
DSP
S/S 13
Capacitors must be inserted between each VS and PGND pair, and between each VCC and GND pair.
No.7813-11/16
LV8224FN
Application Circuit Example 2
VS
Sled
motor
Spindle
motor
35
34
33
32
31
30
29
28
27
26
25
SVO
OUT2R
PGND2
VS2
OUT2F
OUT1R
PGND1
VS1
OUT1F
WOUT
To SP
36
SUO
SLCOM
VS
VOUT
37 SWO
UOUT 24
SPGND 23
38 SLGND
SPVS 22
VS
39 SLVS
SP
40 CLK
IN1F 21
41 CP2
IN1R 20
42 CP1
43 CPC1
IN2R 18
44 CPC2
MUTE 17
4
5
DSP
Notes
• Startup with internal oscillation control mode (L selected)
• Sled three-phase stepping mode
• Cored motor spindle motor mode
• Using an external stepped-up power supply
SOFT
3
SPFIL
2
SPCIN
1
SPCOM
SVCO
48 SUCO
OSC
6
7
8
9
10
11
12
To the spindle motor
BRK 14
SLCOM
47 3/H
To the sled motor
PWM 15
S3
46 VCC
S2
GND 16
S1
45 VG
SPFG
VCC
IN2F 19
LV8224FN
SWCO
VG
VS
S/S 13
Capacitors must be inserted between each VS and ground, between each VCC and ground, and between each VG and ground.
No.7813-12/16
LV8224FN
LV8224FN Functional Description and Notes on External Components
The LV8224FN is a system driver IC that implements, in a single chip, all the motor driver circuits required for CD and
MD players. Since the LV8224FN provides a spindle motor driver (three-phase PWM sensorless drive), a sled stepping
motor driver that supports either three-phase stepping or PWM H bridge drive, and two PWM H bridge drivers for the
focus and tracking blocks, it can contribute to thinner form factors and further miniaturization in end products. Since the
spindle motor driver uses a direct PWM sensorless drive technique, it achieves high-efficiency motor drive with a
minimal number of external components.
Read the following notes before designing driver circuits using the LV8224FN to design a system with fully satisfactory
characteristics.
Output Drive Circuit and Speed Control Methods
The LV8224FN adopts the synchronous commutation direct PWM drive method to minimize power loss in the output
circuits. Low on-resistance DMOS devices (total high and low side on-resistance: 0.8 Ω, typical) are used as the output
transistors.
The spindle motor driver speed is controlled by BRK and PWM signals provided by an external DSP. The PWM signal
controls the sink side transistor. That transistor is switched according to the input duty of the signal input to the PWM
pin (pin 15) to control the motor speed. (The sink side transistor is on when the PWM input is high, and off when the
PWM input is low.)
The LV8224FN also uses variable duty soft switching to achieve quieter motor drive.
Soft Switching Mode Selection
The LV8224FN spindle drive block uses variable PWM duty soft switching to reduce motor drive noise. The SOFT pin
(pin 11) selects the soft switching drive mode, that is, it selects different conditions for optimally quiet drive depending
on the motor structure (coil inductance). Set the SOFT pin to the high level for coreless motors (motors with a low
inductance) and to the low level for cored motors (motors with a high inductance) for optimal soft switching.
Although the SOFT pin has an MOS input circuit, it does not have a built-in pull-up or pull-down resistor, and thus
must be set to the high or low level. This pin must not be left open.
S/S and MUTE Circuits
The S/S pin (pin 13) functions as the spindle motor driver’s start/stop pin; a high-level input specifies that the operation
is in the start state. The MUTE pin (pin 17) operates on all driver blocks other than the spindle block; a low-level input
mutes these outputs. In the muted state, the corresponding drivers (H bridge and three-phase sled drivers) all go to the
high-impedance state, regardless of the states of the logic inputs. Since the S/S and MUTE pins operate independently,
low-level inputs must be applied to both the S/S and MUTE pins to set the IC to the standby state (power saving mode).
Braking Circuit
The BRK pin (pin 14) switches the direction of the torque applied by the spindle motor driver; when a low level is
applied to the BRK pin, the driver switches to reverse torque braking mode. When the motor decelerates to an
adequately low speed in reverse torque braking mode, the driver switches to short-circuit braking mode to stop the
motor. (Note: the IC cannot be set to low-power mode at this time.)
Notes on the CLK and PWM Signals
The LV8224FN CLK pin (pin 40) is used as the sensorless logic reference clock, for step-up circuit pulse generation,
and for other purposes. Therefore, the CLK signal must be supplied at all times when the LV8224FN is in start mode.
The CLK input signal must have a frequency 32 times that of the PWM input signal. We recommend that the CLK
input frequency be less than 6 MHz.
FG Output Circuit
The SPFG pin (pin 3) is the spindle block FG output. It outputs a pulse signal equivalent to a three Hall sensor FG
output. This output has an MOS circuit structure.
No.7813-13/16
LV8224FN
Spindle Block Position Detector Comparator Circuit
The spindle block position detection comparator circuit is provided to detect the position of the rotor using the back
EMF generated when the motor turns. The IC determines the timing with which the output block applies current to the
motor based on the position information acquired by this circuit. Startup problems due to comparator input noise can be
resolved by inserting a capacitor (about 1000 to 4700 pF) between the SPCIN pin (pin 9) and the SPFIL pin (pin 10).
Note that if this capacitor is too large, the output commutation timing may be delayed at higher speeds and efficiency
may be reduced.
OSC Circuit
The OSC pin (pin 12) is an oscillator pin provided for sensorless motor startup commutation. The LV8224FN provides
two main clock dividing modes and a self-oscillation mode.
The main clock division modes are selected by setting the OSC pin to either VCC or ground. The startup frequency is
created by dividing the signal input to the CLK pin (pin 40), and is either CLK/4096 (when the OSC pin is connected to
VCC) or CLK/3072 (when the OSC pin is connected to ground). Self-oscillation mode is set up by inserting a capacitor
between the OSC pin and ground. When self-oscillation mode is selected, the OSC pin starts self-oscillating, and that
frequency becomes the startup frequency. The oscillator frequency can be adjusted by changing the value of the
external capacitor (reducing the value of the capacitor increases the startup frequency).
The number of external components can be reduced if there are no problems with the startup characteristics when the
OSC pin is connected to either VCC or ground. However, if there are problems, select self-oscillation mode and select a
value of the capacitor that provides optimal startup characteristics.
Charge Pump Circuit
The LV8224FN n-channel DMOS output structure allows it to provide a charge pump based voltage step-up circuit. A
voltage 3 times the VCC voltage (or about 6.0 V) can be acquired from the VG pin (pin 45) by inserting capacitors
(recommended value: 0.1 µF or larger) between the CP1 (pin 42) and CPC1 (pin 43) pins and between the CP2 (pin 41)
and CPC2 (pin 44) pins. We recommend using this circuit with values such that the voltage relationship between the
stepped-up voltage (VG) and the motor supply voltage (VS) is VG – VS ≥ 3.0 V. Note that this circuit is designed so
that the stepped-up voltage (VG) is clamped at about 6.0 VDC. A larger capacitor must be used on the VG pin if the
ripple on the stepped-up voltage (VG) results in VGmax exceeding 6.5 V.
Observe the following points if the VG voltage is supplied from external circuits.
• The VG voltage supplied from the external circuits must not exceed the absolute maximum rating VGmax.
• The capacitors between the CP and CPC pins (pins 41 to 44) are not required.
• There is an IC-internal diode between the VCC and VG pins. Therefore, supply voltages such that VCC > VG must
never be applied to this IC.
Sled Driver
The LV8224FN sled driver block provides two output circuit structures: one appropriate for a three-phase motor and
one appropriate for a DC motor. Connect the 3/H pin (pin 47) to VCC to set the block to use the three-phase sensorless
drive structure, and connect the 3/H pin to ground to set the block to use the PWH H bridge drive structure. The S1 to
S3 pins (pins 4 to 6) are the sled driver block control inputs, and the signals are supplied by the DSP. The S1 to S3 pins
have built-in pull-up resistors.
The SUC0 to SWC0 pins (pins 48, 1, and 2) are the sled driver position detector comparator output pins. These signals
are only output in three-phase stepping mode, and output the low-level potential in standby mode and PWM H bridge
mode. These pins are used to feed back the sled motor speed and position information to the DSP or microcontroller.
Actuator Block
The LV8224FN incorporates two H bridge channels for use as actuator drivers for the focus and tracking systems. The
logic input pin circuits incorporates pull-down resistors. A PWM signal is used for control, and the circuit supports
synchronous commutation.
The OUT1F/R output (pins 27 and 30) is the output corresponding to the IN1F/R (pins 21 and 20) channel 1 control
input, and the OUT2F/R output (pins 31 and 34) is the output corresponding to the IN2F/R (pins 19 and 18) channel 2
control input.
The figures show the dead band characteristics during motor control and the test circuit used for measuring those
characteristics.
No.7813-14/16
LV8224FN
Actuator Small-Signal I/O Characteristics (magnified)
VCC = 2.3 V, VS = 1.2 V, PWM = 132 kHz (0–2.3 V)
VCC = 2.3 V, VS = 1.2 V, PWM = 132 kHz (0–2.3V)
1.0
100
0.8
0.6
0.4
0.2
0.0
–100
–80
–60
–40
–20
0
20
40
60
80
100
–0.2
–0.4
–0.6
–0.8
–1.0
IN1F/R (%)
(IN1R is shown as negative.)
The output is passed through 22 µH inductors and
smoothed with a low-pass filter consisting of a 2.0 Ω
resistor and two 1 µF capacitors.
OUT1 output voltage — V
(OUT1R is shown as negative.)
OUT1 output voltage — V
(OUT1R is shown as negative.)
Actuator Small-Signal I/O Characteristics
80
60
40
20
–10
–8
–6
–4
–2
0
–20
2
4
6
8
10
–40
–60
–80
–100
IN1F/R (%)
(IN1R is shown as negative.)
The output is passed through 22 µH inductors and
smoothed with a low-pass filter consisting of a 2.0 Ω
resistor and two 1 µF capacitors.
OUT1F
22 µH
OUT1R
2.0 Ω
1 µF
Notes on PCB Pattern Design
The LV8224FN is a system driver IC implemented in a Bi-DMOS process; the IC chip includes bipolar circuits, MOS
logic circuits, and MOS drive circuits integrated on the same chip. As a result, extreme care is required with respect to
the pattern layout when designing application circuits.
• Ground and VCC/VS wiring layout
The LV8224FN ground and power supply pins are classified as follows.
Small-signal system ground pin → GND (pin 16)
Large-signal system ground pins → PGND1 (pin 29), PGND2 (pin 33), SPGND (pin 23), SLGND (pin 38)
Small-signal system power supply pin → VCC (pin 46)
Large-signal system power supply pins → VS1 (pin 28), VS2 (pin 32), SPVS (pin 22), SLVS (pin 39)
A capacitor must be inserted, as close as possible to the IC, between the small-signal system power supply pin (pin
46) and ground pin (pin 16).
The large-signal system ground pins (PGND1, PGND2, SPGND, and SLGND) must be connected with the shortest
possible lines, and furthermore in a manner such that there is no shared impedance with the small-signal system
ground lines. Capacitors must also be inserted, as close as possible to the IC, between the large-signal system power
supply pins (VS1, VS2, SPVS, and SLVS) and the corresponding large-signal system ground pins.
• Positioning the small-signal system external components
The small-signal system external components that are also connected to ground must be connected to the small-signal
system ground with lines that are as short as possible.
• Notes on components connected between IC pins
External components connected between IC pins must be connected using the shortest lines possible.
The capacitor between CP1 (pin 42) and CPC1 (pin 43)
The capacitor between CP2 (pin 41) and CPC2 (pin 44)
The capacitor between SPFIL (pin 10) and SPCIN (pin 9)
No.7813-15/16
LV8224FN
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be expor ted without obtaining the expor t license from the author ities
concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of June, 2004. Specifications and information herein are subject to
change without notice.
PS No.7813-16/16