Ordering number : ENA0793B LV8224T Bi-CMOS LSI Motor driver system in CD and MD players Overview The LV8224T is a system motor driver IC that implements all the motor driver circuits needed for CD and MD products. The LV8224T provides a three-phase PWM spindle driver, a sled driver (either three-phase or PWM H bridge operation can be selected), and focus and tracking drivers (as two PWM H bridge driver channels). Since the LV8224T uses BiCDMOS devices, it can contribute to further miniaturization, thinner from factors, and lower power in end products. The adoption of the direct PWM sensorless drive method for the spindle driver makes it possible to implement high efficiency motor drive with few external parts. Features • PWM H bridge motor divers (2 channels) • Three-phase stepping motor driver, and direct PWM sensorless motor driver Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Symbol Conditions Ratings Unit VCC max 5.0 V Output block power supply voltage VS max 4.5 V Predriver voltage (gate voltage) VG max 6.5 V Output current IO max Allowable power dissipation Pd max1 Independent IC Pd max2 * Mounted on a board. 0.8 A 0.4 W 1.1 W Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C * : Mounted on a board : 50×50×1.6mm3, glass epoxy board Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 60607 TI PC / 53007 TI PC B8-8449, 8836 No.A0793-1/15 LV8224T Recommended operating Ranges at Ta = 25°C Parameter Symbol Supply voltage Conditions Ratings VCC Unit 1.9 to 4.0 V Output block supply voltage VS 0 to VG-3.0 V Predriver voltage (gate voltage) VG VS+3 to 6.3 V max Unit Electrical Characteristics at Ta = 25°C, VCC = 2.3V Parameter Symbol Conditions Current drain 1 ICC1 S/S pin H Current drain 2 ICC2 S/S pin L(at standby) min typ 1.0 1.5 mA 20 μA 6.2 V mV Charge Pump Output Output voltage VG 5.4 5.9 Actuator Block : Ta = 25°C, VCC = 2.3V Position Detection Comparator Block Input offset voltage VAOFS -9 +9 Common-mode input voltage range VACM 0 VCC V High-level output voltage VACH IO = -0.5mA VCC-0.5 VCC V Low-level output voltage VACL IO = 0.5mA 0.5 V Output block (OUT1F/R, OUT2F/R, SUO to SWO pins) SOURCE 1 Ron (H1) IO = 0.5A, VS = 1.2V, VG = 6V, forward drive transistor 0.4 0.6 Ω SOURCE 2 Ron (H2) IO = 0.5A, VS = 1.2V, VG = 6V, reverse drive transistor 0.4 0.6 Ω SINK Ron (L) IO = 0.5A, VS = 1.2V, VG = 6V 0.4 0.6 Ω SOURCE+SINK Ron (H+L) IO = 0.5A, VS = 1.2V, VG = 6V 0.8 1.2 Ω Output transmission delay time TRISE *Design target 0.1 1.0 μs (H bridge) TFALL *Design target 0.1 0.7 μs Minimum input pulse width tmin ch1, 2 output pulse width ≥ 2/3tmin (H bridge) 200 ns *Design target Decoder and Actuator Input Pins (IN1F/R, IN2F/R, S1 to S3 pins) High-level input voltage range VIH VCC-0.5 VCC V Low-level input voltage range VIL 0 0.5 V High-level actuator input pin current IINH When input pin voltage is 2.3V 9.5 13 μA Low-level actuator input pin current IINL When input pin voltage is 0V 1 μA VCC-0.5 VCC V 0 0.5 V 9.5 13 μA 1 μA MUTE Pin High-level input voltage range VMUH MUTE OFF Low-level input voltage range VMUL MUTE ON High-level input pin current IMUTEH When input pin voltage is 2.3V Low-level input pin current IMUTEL When input pin voltage is 0V Spindle Motor Driver block : Ta = 25°C, VCC = 2.3V Output Block SOURCE1 Ron (H1) IO = 0.5A, VS = 1.2V, VG = 6V, forward drive transistor 0.4 0.6 Ω SOURCE2 Ron (H2) IO = 0.5A, VS = 1.2V, VG = 6V, reverse drive transistor 0.4 0.6 Ω SINK Ron (L) IO = 0.5A, VS = 1.2V,VG = 6V 0.4 0.6 Ω SOURCE+SINK Ron (H+L) IO = 0.5A, VS = 1.2V, VG = 6V 0.8 1.2 Ω Position Detector Comparator Input offset voltage VSOFS -9 9 mV OSC high-level voltage VOSCH 0.85 1.05 1.25 V OSC low-level voltage VOSCL 0.40 0.60 0.80 V Startup Oscillator Pin S/S pin High-level input voltage range VSSH Start VCC-0.5 VCC V Low-level input voltage range VSSL Stop 0 0.5 V High-level input pin current ISSH When input pin voltage is 2.3V 9.5 13 μA Low-level input pin current ISSL When input pin voltage is 0V 1 μA Continued on next page. No.A0793-2/15 LV8224T Continued from preceding page. Parameter Symbol Conditions min typ max Unit BREAK Pin High-level input voltage range VBRH Brake off VCC-0.5 VCC V Low-level input voltage range VBRL Brake on 0 0.5 V High-level input pin current IBRKH When input pin voltage is 2.3V 9.5 13 μA Low-level input pin current IBRKL When input pin voltage is 0V 1 μA VCC-0.5 VCC V 0 0.5 V 9.5 13 μA PWM Pin High-level input voltage range VPWMH Low-level input voltage range VPWML High-level input pin current IPWMH When input pin voltage is 2.3V Low-level input pin current IPWML When input pin voltage is 0V PWM input frequency VPWMIN 1 μA 190 kHz CLK Pin High-level input voltage range VCLKH VCC-0.5 VCC V Low-level input voltage range VCLKL 0 0.5 V High-level input pin current ICLKH When input pin voltage is 2.3V 9.5 13 μA Low-level input pin current ICLKL When input pin voltage is 0V 1 μA High-level output voltage VFGH IO = -0.5mA VCC V Low-level output voltage VFGL IO = 0.5mA 0.5 V FG output Pin VCC-0.5 Package Dimensions unit : mm (typ) 3254 9.0 0.5 7.0 36 25 24 7.0 9.0 37 13 48 0.125 1.2max (0.75) 12 0.2 (1.0) 0.5 0.1 1 Allowable power dissipation, Pd max – W 1.5 1.1 Pd max – Ta Specified circuit board : 50×50×1.6mm3 glass epoxy board Mounted on the thermal resistance evaluation PCB 1.1 1 0.57 0.5 0 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C SANYO : TQFP48(7X7) No.A0793-3/15 LV8224T Actuator Truth Tables Focus and Tracking Blocks MUTE IN1, 2F IN1, 2R OUT1, 2F OUT1, 2R H L L L L H H L H L H L H L H H H H L L L × × Z Z Sled Drive Block Stepping Drive Mode (When 3/H pin (pin 47) is high) MUTE S1 S2 S3 SUO SVO SWO H L L L H L Z H H L L H Z L H L H L Z H L H H H L L H Z H L L H L Z H H H L H Z L H H L H H Z Z Z H H H H Z Z Z L × × × Z Z Z Z : Open Sled Drive Block H Bridge Drive Mode (When 3/H pin (pin 47) is low) MUTE S1 S2 SUO SVO MUTE S3 SWO H L L L L H L L H H L H L H H H H L H L H L × Z H H H L L L × × Z Z Z : Open Notes : When the 3/H pin is set to select H bridge mode, SUO and SVO operate as PWM H bridge outputs according to the S1 and S2 inputs, and SWO operates as a half-bridge circuit output according to the S3 input. No.A0793-4/15 LV8224T VOUT WOUT OUT1F VS1 PGND1 OUT1R OUT2F VS2 PGND2 OUT2R SUO SVO Pin Assignment 36 35 34 33 32 31 30 29 28 27 26 25 UOUT 37 24 SWO SPGND 38 23 SLGND SPVS 39 22 SLVS IN1F 40 21 CLK IN1R 41 20 CP2 IN2F 42 19 CP1 LV8224T IN2R 43 18 CPC1 MUTE 44 17 CPC2 GND 45 16 VG PWM 46 15 VCC BRK 47 14 3/H 1 2 3 4 5 6 7 8 9 10 11 12 SOFT SPFIL SPCIN SPCOM SLCOM S3 S2 S1 SPFG SWCO SVCO 13 SUCO OSC S/S 48 No.A0793-5/15 LV8224T Block Diagram PGND2 VS2 OUT2R OUT2F IN2R IN2F OUT1R OUT1F IN1R IN1F VS1 PGND1 Pre driver Logic Pre driver Logic MUTE VG VCC CP1 GND CPC1 Charge pump 1/N CP2 CPC2 SUCO SVCO SWCO CLK S/S Waveform distributor BRK SOFT 3/H OSC SEL S1 S2 S3 SLCOM Logic SEL OSC CIN Sensorless logic FIL Waveform synthesizer Sled pre driver Spindle pre driver Waveform synthesizer SPCOM SLVS SPVS SUO SVO SWO UOUT VOUT WOUT SLGND SPGND SPFG PWM No.A0793-6/15 LV8224T Sample Application Circuit 1 34 33 32 31 30 29 28 27 26 VS1 PGND1 OUT1R OUT2F VS2 PGND2 OUT2R SUO 37 UOUT Spindle motor OUT1F 36 35 VOUT WOUT To SPCOM VS VS Spindle motor 38 SPGND VS DSP SWO 24 39 SPVS SLVS 22 40 IN1F CLK 21 41 IN1R CP2 20 42 IN2F VS DSP CP1 19 LV8224T CPC1 18 44 MUTE CPC2 17 S3 S2 S1 SPFG SWCO 2 3 4 5 6 7 8 9 10 11 To Sled motor 1 To Spindle motor SLCOM 3/H 14 SPCOM 47 BRK SPCIN VCC 15 SPFIL 46 PWM SOFT VG 16 OSC 45 GND 48 S/S To SLCOM SLGND 23 43 IN2R DSP 25 SVO SUCO 13 SVCO 12 DSP Notes • Startup with automatic oscillation mode • Sled three-phase stepping mode • Cored motor spindle motor mode Capacitors must be inserted between VS and PGND, and between VCC and ground. No.A0793-7/15 LV8224T Sample Application Circuit 2 External parts minimum plan VS 34 33 32 31 30 29 28 27 26 PGND1 OUT1R OUT2F VS2 PGND2 OUT2R SUO 37 UOUT Spindle motor VS1 36 35 VOUT WOUT To SPCOM VS OUT1F Spindle motor 38 SPGND VS DSP 25 SVO To SLCOM SWO 24 SLGND 23 39 SPVS SLVS 22 40 IN1F CLK 21 41 IN1R CP2 20 42 IN2F VS DSP CP1 19 LV8224T CPC1 18 44 MUTE CPC2 17 S2 S1 SPFG SWCO 2 3 4 5 6 7 8 9 10 11 To Sled motor 1 To Spindle motor 48 S/S S3 3/H 14 SLCOM 47 BRK SPCOM VCC 15 SPCIN 46 PWM SPFIL VG 16 SOFT 45 GND OSC DSP 43 IN2R VG VCC SUCO 13 SVCO 12 DSP Notes • Startup with internal oscillation control mode (Low-level selected) • Sled three-phase stepping mode • Cored motor spindle motor mode • External stepped-up power supply used Capacitors must be inserted between each VS and ground, Between each VCC and ground, and between each VG and ground. No.A0793-8/15 LV8224T Pin Description Pin No. 1 Pin name OSC Pin circuit Equivalent Circuit Startup oscillator connection. When this pin is VCC connected to VCC, the startup frequency will be equivalent to fCLK/4096, and connected to ground, that frequency will be fCLK/3072. If any other startup frequency is to be set, insert a capacitor 500Ω between this pin and ground. The startup frequency can be set freely by changing the 1 500Ω value of the capacitor. 2 SOFT Spindle driver block drive current waveform VCC selection. Set this pin to low when using a cored motor and to high when using a coreless motor. 2 3 SPFIL Waveform synthesis signal filter connection. 10kΩ VG Insert a capacitor between this pin and SPCIN (pin 4). 200kΩ 3 12kΩ 4 SPCIN Position detection comparator differential input. Insert a capacitor between this pin and SPFIL (pin 3). 5 SPCOM Spindle motor common point connection. VG 5 4 1kΩ 200kΩ 12kΩ Continued on next page. No.A0793-9/15 LV8224T Continued from preceding page. Pin No. 6 Pin name SLCOM Pin circuit Equivalent Circuit Sled driver block position detection comparator VG common input. 1kΩ 6 9 S1 Three-phase sled block logic inputs. Pins 35, 36, 8 S2 and 37 are the corresponding outputs. 7 S3 VCC 200kΩ 10kΩ 10 SPFG FG pulse output. VCC This pin outputs a three Hall sensor system equivalent pulse signal. 13 SUCO Sled driver block position detection comparator 12 SVCO outputs. 11 SWCO 14 3/H Sled drive mode selection. A high-level input selects three-phase stepping mode, and a low-level VCC input selects H-bridge + half bridge mode. This pin must not be left open. 1kΩ 14 15 VCC Small-signal system power supply. 16 VG Charge pump stepped up voltage output. 1kΩ Insert a capacitor between this pin and ground. Insert a capacitor between this pin and ground. 18 VCC 17 CPC2 17 16 Charge pump step-up connection. Insert a capacitor between this pin and CP2 (pin 20). 18 CPC1 Charge pump step-up connection. Insert a capacitor between this pin and CP1 (pin 19). Continued on next page. No.A0793-10/15 LV8224T Continued from preceding page. Pin No. 19 Pin name CP1 Pin circuit Equivalent Circuit Charge pump step-up pulse output. Insert a capacitor between this pin and CPC1 (pin 18). Leave this pin open when using this circuit as a 19 20 VCC 2×step-up circuit. 20 CP2 Charge pump step-up pulse output. Insert a capacitor between this pin and CPC2 (pin 17). 21 CLK Logic circuit operation reference clock input. Supply a frequency 32 times that of the spindle PWM frequency. 40, 41 IN1F/R 42, 43 IN2F/R 44 MUTE Actuator H-bridge block logic input. VCC Muting control for the H bridge 1 and 2 blocks and the sled driver block. When a low level is input, these channel outputs all 10kΩ go to the high-impedance state. 46 PWM PWM signal input. The output transistor is on when 200kΩ this input is high. 47 BRK 48 S/S 22 SLVS Spindle motor block braking control. A low-level input sets the block to reverse torque braking. Spindle motor block start/stop control. A high-level input sets the block to start mode. Sled motor drive power supply. 22 Insert a capacitor between this pin and ground. 26 SUO Sled driver outputs. Connect these pins to the sled 25 SVO motor. 24 SWO 23 SLGND Sled output block ground. 29 VS2 H bridge 2 output block. OUT2F/R Insert a capacitor between VS2 (pin 29) and PGND2 ground. 30, 27 28 26 25 1kΩ 1kΩ 24 1kΩ 23 29 27 30 31 34 28 33 34, 31 32 VS1 H-bridge 1 output block. OUT1F/R Insert a capacitor between VS1 (pin 33) and PGND1 ground. 33 32 Continued on next page. No.A0793-11/15 LV8224T Continued from preceding page. Pin No. 39 Pin name SPVS Pin circuit Equivalent Circuit Spindle motor drive power supply. 39 Insert a capacitor between this pin and ground. 37 UOUT Spindle driver outputs. 36 VOUT Connect these pins to the spindle motor. 35 WOUT 38 SPGND Spindle output block ground. 45 GND Small-signal system circuit ground. 37 36 1kΩ 1kΩ 35 1kΩ 38 LV8224T Functional Description and Notes on External Components The LV8224T is a system driver IC that implements, in a single chip, all the motor driver circuits required for CD and MD players. Since the LV8224T provides a spindle motor driver (three-phase PWM sensorless drive), a sled stepping motor driver that supports either three-phase stepping or PWM H-bridge drive, and two PWM H-bridge drivers for the focus and tracking blocks, it can contribute to thinner form factors and further miniaturization in end products. Since the spindle motor driver uses a direct PWM sensorless drive technique, it achieves high-efficiency motor drive with a minimal number of external components. Read the following notes before designing driver circuits using the LV8224T to design a system with fully satisfactory characteristics. 1. Output Drive Circuit and Speed Control Methods The LV8224T adopts the synchronous commutation direct PWM drive method to minimize power loss in the output circuits. Low on-resistance DMOS devices (total high and low side on-resistance : 0.8Ω, typical) are used as the output transistors. The spindle motor driver speed is controlled by BRK and PWM signals provided by an external DSP. The PWM signal controls the sink side transistor. That transistor is switched according to the input duty of the signal input to the PWM pin (pin 46) to control the motor speed. (The sink side transistor is on when the PWM input is high-level, and off when the PWM input is low-level.) The LV8224T also uses variable duty soft switching to achieve quieter motor drive. 2. Soft Switching Mode Selection The LV8224T spindle drive block uses variable PWM duty soft switching to reduce motor drive noise. The SOFT pin (pin 2) selects the soft switching drive mode, that is, it selects different conditions for optimally quiet drive depending on the motor structure (coil inductance). Set the SOFT pin to the high-level for coreless motors (motors with a low inductance) and to the low-level for cored motors (motors with a high inductance) for optimal soft switching. Although the SOFT pin has an MOS input circuit, it does not have a built-in pull-up or pull-down resistor, and thus must be set to the high or low level. This pin must not be left open. 3. S/S and MUTE Circuits The S/S pin (pin 48) functions as the spindle motor driver’s start/stop pin; a high-level input specifies that the operation is in the start state. The MUTE pin (pin 44) operates on all driver blocks other than the spindle block; a low-level input mutes these outputs. In the muted state, the corresponding drivers (H-bridge and three-phase sled drivers) all go to the high-impedance state, regardless of the states of the logic inputs. Since the S/S and MUTE pins operate independently, low-level inputs must be applied to both the S/S and MUTE pins to set the IC to the standby state (power saving mode). 4. Braking Circuit The BRK pin (pin 47) switches the direction of the torque applied by the spindle motor driver; when a low-level is applied to the BRK pin, the driver switches to the reverse torque braking mode. When the motor decelerates to an adequately low speed in the reverse torque braking mode, the driver switches to the short-circuit braking mode to stop the motor. (Note : the IC cannot be set to low-power mode at this time.) No.A0793-12/15 LV8224T 5. Notes on the CLK and PWM Signals The LV8224T CLK pin (pin 21) is used as the sensorless logic reference clock, for step-up circuit pulse generation, and for other purposes. Therefore, the CLK signal must be supplied at all times when the LV8224T is in start mode. The CLK input signal must have a frequency 32 times that of the PWM input signal. We recommend that the CLK input frequency be less than 6MHz. 6. FG Output Circuit The SPFG pin (pin 10) is the spindle block FG output. It outputs a pulse signal equivalent to a three Hall sensor FG output. This output has an MOS circuit structure. 7. Spindle Block Position Detection Comparator Circuit The spindle block position detection comparator circuit is provided to detect the position of the rotor using the back EMF generated when the motor turns. The IC determines the timing with which the output block applies current to the motor based on the position information acquired by this circuit. Startup problems due to comparator input noise can be resolved by inserting a capacitor (about 1000 to 4700pF) between the SPCIN pin (pin 4) and the SPFIL pin (pin 3). Note that if this capacitor is too large, the output commutation timing may be delayed at higher speeds and efficiency may be reduced. 8. OSC Circuit The OSC pin (pin 1) is an oscillator pin provided for sensorless motor startup commutation. The LV8224T provides two main clock dividing modes and a self-oscillation mode. The main clock division modes are selected by connecting OSC pin to either VCC or ground. The startup frequency is created by dividing the signal input to the CLK pin (pin 21), and is either CLK/4096 (when the OSC pin is connected to VCC) or CLK/3072 (when the OSC pin is connected to ground). Self-oscillation mode is set up by inserting a capacitor between the OSC pin and ground. When self-oscillation mode is selected, the OSC pin starts self-oscillating, and that frequency becomes the startup frequency. The oscillator frequency can be adjusted by changing the value of the external capacitor (reducing the value of the capacitor increases the startup frequency). The number of external components can be reduced if there are no problems with the startup characteristics when the OSC pin is connected to either VCC or ground. However, if there are problems, select self-oscillation mode and select a value of the capacitor that provides optimal startup characteristics. 9. Charge Pump Circuit The LV8224T n-channel DMOS output structure allows it to provide a charge pump based voltage step-up circuit. A voltage 3 times the VCC voltage (or about 6.0V) can be acquired from the VG pin (pin 16) by inserting capacitors (recommended value : 0.1μF or larger) between the CP1 (pin 19) and CPC1 (pin 18) pins and between the CP2 (pin 20) and CPC2 (pin 17) pins. We recommend using this circuit with values such that the voltage relationship between the stepped-up voltage (VG) and the motor supply voltage (VS) is VG-VS ≥ 3.0V. Note that this circuit is designed so that the stepped-up voltage (VG) is clamped at about 6.0VDC. A larger capacitor must be used on the VG pin if the ripple on the stepped-up voltage (VG) results in VG exceeding 6.5V(VG max). Observe the following points if the VG voltage is supplied from external circuits. 1) The VG voltage supplied from the external circuits must not exceed the absolute maximum rating VG max. 2) The capacitors between the CP and CPC pins (pins17 to 20) are not required. 3) There is an IC-internal diode between the VCC and VG pins. Therefore, supply voltages such that VCC > VG must never be applied to this IC. 10. Sled Driver The LV8224T sled driver block provides two output circuit structures: one appropriate for a three-phase motor and one appropriate for a DC motor. Connect the 3/H pin (pin 14) to VCC to set the block to use the three-phase stepping drive structure, and connect the 3/H pin to ground to set the block to use the PWH H bridge drive structure. The S1 to S3 pins (pins 7 to 9) are the sled driver block control inputs, and the signals are supplied by the DSP. The S1 to S3 pins have built-in pull-up resistors. The SUC0 to SWC0 pins (pins13, 12, and 11) are the sled driver position detection comparator output pins. These pins output the signals only in the three-phase stepping mode, and they output the low-level potential in standby mode and PWM H bridge mode. These pins are used to feed back the sled motor speed and position information to the DSP or microcontroller. No.A0793-13/15 LV8224T 11. Actuator Block The LV8224T incorporates two H bridge channels for use as actuator drivers for the focus and tracking systems. The logic input pin circuits incorporates pull-down resistors. A PWM signal is used for control, and the circuit supports synchronous commutation. The OUT1F/R output (pins 34 and 31) is the output corresponding to the IN1F/R (pins 40 and 41) channel 1 control input, and the OUT2F/R output (pins 30 and 27) is the output corresponding to the IN2F/R (pins 42 and 43) channel 2 control input. The figures show the dead band characteristics during motor control and the test circuit used for measuring those characteristics. LV8224T Actuator small signal I/O characteristics VCC = 2.3V, VS = 1.2V PWM = 132kHz(0-2.3V) 100 0.8 80 0.6 60 OUT1 output voltage (V) [OUT1R indicated with "-" ] OUT1 output voltage (V) [OUT1R indicated with "-" ] 1.0 LV8224T Actuator small signal I/O characteristics (magnified) VCC = 2.3V, VS = 1.2V PWM = 132kHz(0-2.3V) 0.4 0.2 0.0 – 0.2 – 0.4 – 0.6 20 0 – 20 – 40 – 60 – 80 – 0.8 – 1.0 – 100 – 80 40 – 60 – 40 – 20 0 20 40 60 80 100 – 100 – 10 –8 –6 –4 –2 0 2 4 6 8 10 IN1F/R(%) [IN1R indicated with "-" ] IN1F/R(%) [IN1R indicated with "-" ] Output measured with 2.0Ω, A1.0μF LPF after passing through the 22μH coil Output measured with 5.0Ω, A1.0μF LPF after passing through the 22μH coil OUT1F 22μH 2.0Ω OUT1R 1μF 12. Notes on PCB Pattern Design The LV8224T is a system driver IC implemented in a Bi-CMOS process; the IC chip includes bipolar circuits, MOS logic circuits, and MOS drive circuits integrated on the same chip. As a result, extreme care is required with respect to the pattern layout when designing application circuits. 1) Ground and VCC/VS wiring layout The LV8224T ground and power supply pins are classified as follows. Small-signal system ground pin → GND (pin 45) Large-signal system ground pins → PGND1 (pin 32), PGND2 (pin 28), SPGND (pin 38), SLGND (pin 23) Small-signal system power supply pin → VCC (pin 15) Large-signal system power supply pins → VS1 (pin 33), VS2 (pin 29), SPVS (pin 39), SLVS (pin 22) A capacitor must be inserted, as close as possible to the IC, between the small-signal system power supply pin (pin 15) and ground pin (pin 45). The large-signal system ground pins (PGND1, PGND2, SPGND, and SLGND) must be connected with the shortest possible lines, and furthermore in a manner such that there is no shared impedance with the small-signal system ground lines. Capacitors must also be inserted, as close as possible to the IC, between the large-signal system power supply pins (VS1, VS2, SPVS, and SLVS) and the corresponding large-signal system ground pins. No.A0793-14/15 LV8224T 2) Positioning the small-signal system external components The small-signal system external components that are also connected to ground must be connected to the small-signal system ground with lines that are as short as possible. 3) Notes on components connected between IC pins External components connected between IC pins must be connected using the shortest lines possible. The capacitor between CP1 (pin 19) and CPC1 (pin 18) The capacitor between CP2 (pin 20) and CPC2 (pin 17) The capacitor between SPFIL (pin 3) and SPCIN (pin 4) SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2007. Specifications and information herein are subject to change without notice. PS No.A0793-15/15