SC1470 Synchronous Buck Pseudo Fixed Frequency Power Supply Controller POWER MANAGEMENT Description Features The SC1470 is a single output, constant on-time synchronous-buck PWM controller intended for use in notebook computers and other battery operated portable devices. Features include high efficiency and fast dynamic response with no minimum on time. The excellent transient response means that SC1470 based solutions will require less output capacitance than competing fixed frequency converters. The frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady state operation. At light loads, Power-Save Mode enables the SC1470 to skip PWM pulses for better efficiency. The output voltage can be adjusted from 0.5V to VCCA. A frequency setting resistor sets the on-time for flexibility in choosing filter components. The integrated gate drivers feature adaptive shoot-through protection and soft switching. Additional features include cycle-by-cycle current limit, digital soft-start, over-voltage and undervoltage protection, and a Power Good output. Applications Typical Application Circuit VBAT Constant on-time for fast dynamic response Programmable VOUT range = 0.5 – VCCA VBAT range = 1.8V – 25V DC current sense using low-side RDS(ON) sensing or sense resistor Resistor programmable frequency Cycle-by-Cycle current limit Digital soft-start Combined EN and PSAVE functions Over-voltage/under-voltage fault protection and Power Good output 10µA typical shutdown current Low quiescent power dissipation 14 Lead TSSOP package Industrial temperature range 1% Internal reference (2% system DC accuracy) Integrated gate drivers with soft switching 5VSUS Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies 5VSUS VBAT D1 R1 R2 RTON 10R 1 2 VOUT 3 R3 4 R5 PGOOD 1nF Revision: April 29, 2005 EN/PSV TON VOUT VCCA SC1470 BST DH LX ILIM C1 14 0.1uF Q1 13 C2 10uF 12 11 L1 R4 VOUT C3 + 5 6 C5 U1 R6 C6 7 FB PGD VSSA VDDP DL PGND 10 Q2 9 8 C4 1uF 1uF 1 www.semtech.com SC1470 POWER MANAGEMENT Absolute Maximum Ratings (1) Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Parameter Symbol Maximum Units TON to VSSA -0.3 to +25.0 V DH, BST to PGND -0.3 to +30.0 V LX to PGND -2.0 to +25.0 V PGND to VSSA -0.3 to +0.3 V BST to LX -0.3 to +6.0 V DL, ILIM, VDDP to PGND -0.3 to +6.0 V EN/PSV, FB, PGD, VCCA, VOUT to VSSA -0.3 to +6.0 V VCCA to EN/PSV, FB, PGD, VOUT -0.3 to +6.0 V Thermal Resistance Junction to Ambient (2) θJA 100 °C/W Operating Junction Temperature Range TJ -40 to +125 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7. Electrical Characteristics Test Conditions: VBAT = 15V, EN/PSV = 5V, VCCA = VDDP = 5V, VOUT = 1.25V, RTON = 1MΩ Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Max Units Input Supplies VC C A 5.0 4.5 5.5 V VD D P 5.0 4.5 5.5 V VBAT Input Voltage Offtime > 800ns VDDP Operating Current FB > regulation point, ILOAD = 0A 70 150 µA VCCA Operating Current FB > regulation point, ILOAD = 0A 700 1100 µA TON Operating Current RTON = 1MΩ 15 Shutdown Current EN/PSV = 0V -5 -10 µA VC C A 5 10 µA VDDP, TON 0 1 µA 2005 Semtech Corp. 1.8 2 25 V µA www.semtech.com SC1470 POWER MANAGEMENT Electrical Characteristics (Cont.) Test Conditions: VBAT = 15V, EN/PSV = 5V, VCCA = VDDP = 5V, VOUT = 1.25V, RTON = 1MΩ Parameter Conditions 25°C Min Typ -40°C to 125°C Max Units Min Max -1% +1% V 0.5 VC C A V Controller Error Comparator Threshold (FB Turn-on Threshold)(1) VCCA = 4.5V to 5.5V 0.500 Output Voltage Range On-Time, VBAT = 2.5V RTON = 1MΩ 1761 1497 2025 ns RTON = 500kΩ 936 796 1076 ns 550 ns Minimum Off Time 400 VOUT Input Resistance 500 FB Input Bias Current kΩ -1.0 +1.0 µA 9 11 µA -5 5 mV Over-Current Sensing ILIM Sink Current DL High Current Comparator Offset PGND - ILIM 10 PSAVE Zero-Crossing Threshold (PGND - LX), EN/PSV = 5V 5 mV (PGND-LX), RILIM = 5kΩ 50 35 65 mV (PGND-LX), RILIM = 10kΩ 100 85 115 mV (PGND-LX), RILIM = 20kΩ 200 175 225 mV Current Limit (Negative) (PGND-LX) -140 -200 -100 mV Output Under-Voltage Fault With respect to internal reference -30 -40 -25 % Output Over-Voltage Fault With respect to internal reference +10 +8 +12 % Over-Voltage Fault Delay FB forced above OV threshold PGD Low Output Voltage Sink 1mA PGD Leakage Current FB in regulation, PGD = 5V PGD UV Threshold With respect to internal reference Fault Protection Current Limit (Positive) (2) 2005 Semtech Corp. 3 5 -10 µs -12 0.4 V 1 µA -8 % www.semtech.com SC1470 POWER MANAGEMENT Electrical Characteristics (Cont.) Test Conditions: VBAT = 15V, EN/PSV = 5V, VCCA = VDDP = 5V, VOUT = 1.25V, RTON = 1MΩ Parameter Conditions 25°C Min Typ PGD Fault Delay FB forced outside PGD window. VCCA Undervoltage Threshold Falling (100mV Hysteresis) 4.0 Over Temperature Lockout 10°C Hysteresis 165 -40°C to 125°C Max Min Units Max 5 µs 3.7 4.3 V °C Inputs/Outputs Logic Input Low Voltage EN/PSV low 1.2 Logic Input High Voltage EN High, PSV low (Floating) Logic Input High Voltage EN/PSV high EN/PSV Input Resistance R Pullup to VCCA 1.5 MΩ R Pulldown to VSSA 1.0 MΩ Soft-Start Ramp Time EN/PSV high to PGD high 440 clks(3) Under-Voltage Blank Time EN/PSV high to UV high 440 clks(3) ns 2.0 V V 3.1 V Soft Start Gate Drivers Shoot-Through Delay (4) DH or DL rising 30 DL Pull-Down Resistance DL low 0.8 1.6 Ω DL Pull-Up Resistance DL high 2 4 Ω DH Pull-Down Resistance DH low, BST - LX = 5V 2 4 Ω DH Pull-Up Resistance DH high, BST - LX = 5V 2 4 Ω (5) DL Sink Current DL = 2.5V 3.1 A DL Source Current DL = 2.5V 1.3 A DH Sink/Source Current DH = 2.5V 1.3 A Notes: (1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the lowside MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests. (3) clks = switching cycles. (4) Guaranteed by design. See Shoot-Through Delay Timing Diagram. (5) Semtech’s SmartDriverTM FET drive first pulls DH high with a pullup resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this point, an additional pullup device is activated, reducing the resistance to 2Ω (typ.). This negates the need for an external gate or boost resistor. 2005 Semtech Corp. 4 www.semtech.com SC1470 POWER MANAGEMENT Pin Configuration Ordering Information DEVICE Top View EN/PSV 1 14 BST TON 2 13 DH VOUT 3 12 LX VCCA 4 11 ILIM FB 5 10 VDDP PGD 6 9 DL VSSA 7 8 PGND (1) PACKAGE SC1470ITSTR TSSOP-14 SC1470ITSTRT(2) TSSOP-14 S C 1470E V B EVALUATION BOARD Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free option. This product is fully WEEE and RoHS compliant. (14 Pin TSSOP) Pin Descriptions Pin # Pin Name Pin Function 1 EN/PSV Enable/Power Save input. Pull down to VSSA to shut down the output. Pull up to enable the output and activate PSAVE mode. Float to enable the output and activate continuous conduction mode (CCM). If floated, bypass to VSSA with a 10nF ceramic capacitor. 2 TON This pin is used to sense VBAT through a pullup resistor, RTON, and to set the top MOSFET ontime. Bypass this pin with a 1nF ceramic capacitor to VSSA. 3 VOUT Output voltage sense input. Connect to the output at the load. 4 VC C A Supply voltage input for the analog supply. Use a 10 Ohm / 1µF RC filter from 5VSUS to VSSA. 5 FB Feedback input. Connect to a resistor divider located at the IC from VOUT to VSSA to set the output voltage from 0.5V to VCCA. 6 PGD Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles) following power up. 7 VSSA Ground reference for analog circuitry. Connect to PGND at the bottom of the output capacitor. 8 PGND Power ground. 9 DL 10 VD D P +5V supply voltage input for the gate drivers. Decouple this pin with a 1µF ceramic capacitor to PGND. 11 ILIM Current limit input. Connect to drain of low-side MOSFET for RDS(ON) sensing or the source for resistor sensing through a threshold sensing resistor. 12 LX Phase node (junction of top and bottom MOSFETs and the output inductor) connection. 13 DH Gate drive output for the high side MOSFET switch. 14 BST Boost capacitor connection for the high side gate drive. 2005 Semtech Corp. Gate drive output for the low side MOSFET switch. 5 www.semtech.com SC1470 POWER MANAGEMENT Shoot-Through Delay Timing Diagram LX DH DL DL tplhDL tplhDH Block Diagram VCCA (4) EN/SPV (1) POR / SS OT BST (14) TON (2) VOUT (3) ON TON OFF PWM CONTROL LOGIC HI DH (13) LX (12) TOFF OC 1.5V REF ZERO I + ISENSE FB (5) ILIM (11) VDDP (10) X3 LO PGD (6) DL (9) PGND (8) OV VSSA (7) FAULT MONITOR UV REF + 10% REF - 10% REF - 30% Figure 1 - SC1470 Block Diagram 2005 Semtech Corp. 6 www.semtech.com SC1470 POWER MANAGEMENT Application Information zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need for a clock generator. +5V Bias Supplies The SC1470 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951. For VOUT < 3.3V: For optimal operation, the controller has its own ground reference, VSSA, which should be tied by a single trace to PGND at the negative terminal of the output capacitor (see Layout Guidelines). All external components referenced to VSSA in the Typical Applications Circuit on Page 1 should be connected to VSSA. The supply decoupling capacitor should be tied directly between the VCCA and VSSA pins. A 10Ω resistor should be used to decouple VCCA from the main VDDP supply. PGND can then be a separate plane which is not used for routing traces. All PGND connections are connected directly to the ground plane with special attention given to avoiding indirect connections which may create ground loops. As mentioned above, VSSA must be connected to the PGND plane at the negative terminal of the output capacitor only. The VDDP input provides power to the upper and lower gate drivers. A decoupling capacitor is required. No series resistor between VDDP and 5V is required. See Layout Guidelines for more details. V t ON = 3.3 x10 −12 • (R TON + 37 x10 3 ) • OUT + 50ns VBAT For 3.3V ≤ VOUT ≤ 5V: V t ON = 0.85 • 3.3 x10 −12 • (R TON + 37x103 ) • OUT + 50ns VBAT RTON is a resistor connected from the input supply (VBAT) to the TON pin. Due to the high impedance of this resistor, the TON pin should always be bypassed to VSSA using a 1nF ceramic capacitor. Enable & Psave The EN/PSV pin enables the supply. When EN/PSV is tied to VCCA the controller is enabled and power save will also be enabled. If PSAVE is enabled, the SC1470 PSAVE comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (LX) to PGND. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve light-load efficiency and add hysteresis, the on-time is increased by 50% in power save. The efficiency improvement at light-loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when psave is enabled. Pseudo-fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant ontime, pseudo fixed frequency PWM controller (see Figure 1, SC1470 Block Diagram). The output ripple voltage developed across the output filter capacitor’s ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns. On-Time One-Shot (tON) When the EN/PSV pin is tri-stated, an internal pull-up will activate the controller and power save will be disabled. The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage-proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from 2005 Semtech Corp. When the EN/PSV pin is pulled low, the supply is disabled and the MOSFET drivers are tri-stated. 7 www.semtech.com SC1470 POWER MANAGEMENT Output Voltage Selection sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. In an extreme overcurrent situation, the top MOSFET will never turn back on and eventually the part will latch off due to output undervoltage (see Output Undervoltage Protection). The output voltage is set by the feedback resistors R3 & R7 of Figure 2 below. The internal reference is 1.5V, so the voltage at the feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can be set to a minimum of 0.5V. The equation for setting the output voltage is: The current sensing circuit actually regulates the inductor valley current (see Figure 3). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below: R3 VOUT = 1 + • 0 .5 R7 2 C5 56p 0402 VOUT 3 R3 20k0 0402 4 5 6 R7 14k3 0402 7 U1 EN/PSV TON SC1470 BST DH VOUT LX VCCA ILIM FB PGD VSSA VDDP DL PGND 14 13 12 IPEAK INDUCTOR CURRENT 1 11 10 9 ILOAD ILIMIT 8 TIME Valley Current-Limit Threshold Point Figure 3: Valley Current Limiting Figure 2: Setting The Output Voltage Current Limit Circuit The equation for the current limit threshold is as follows: Current limiting of the SC1470 can be accomplished in two ways. The on-state resistance of the low-side MOSFET can be used as the current sensing element or sense resistors in series with the low-side source can be used if greater accuracy is desired. RDS(ON) sensing is more efficient and less expensive. In both cases, the RILIM resistor between the ILIM pin and LX pin sets the over current threshold. This resistor RILIM is connected to a 10µA current source within the SC1470 which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resistor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the ILIMIT = 10e -6 • 2005 Semtech Corp. RILIM A R SENSE Where (referring to Figure 4 on Page 15) RILIM is R4 and RSENSE is the RDS(ON) of Q2. For resistor sensing, a sense resistor is placed between the source of Q2 and PGND. The current through the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches the voltage drop across RILIM, a positive over-current exists and the high side MOSFET will not be allowed to turn on. When using an external sense resistor RSENSE is the resistance of the sense resistor. 8 www.semtech.com SC1470 POWER MANAGEMENT The current limit circuitry also protects against negative over-current (i.e. when the current is flowing from the load to PGND through the inductor and bottom MOSFET). In this case, when the bottom MOSFET is turned on, the phase node, LX, will be higher than PGND initially. The SC1470 monitors the voltage at LX, and if it is greater than a set threshold voltage of 125mV (nom.) the bottom MOSFET is turned off. The device then waits for approximately 2.5µs and then DL goes high for 300ns (typ.) once more to sense the current. This repeats until either the over-current condition goes away or the part latches off due to output overvoltage (see Output Overvoltage Protection). and allows switching to occur if the device is enabled. Switching always starts with DL to charge up the BST capacitor. With the softstart circuit (automatically) enabled, it will progressively limit the output current (by limiting the current out of the ILIM pin) over a predetermined time period of 440 switching cycles. The ramp occurs in four steps: 1) 110 cycles at 25% ILIM with double minimum off-time (for purposes of the on-time one-shot, there is an internal positive offset of 120mV to VOUT during this period to aid in startup) 2) 110 cycles at 50% ILIM with normal minimum off-time 3) 110 cycles at 75% ILIM with normal minimum off-time 4) 110 cycles at 100% ILIM with normal minimum off-time. At this point the output undervoltage and power good circuitry is enabled. Power Good Output The power good output is an open-drain output and requires a pull-up resistor. When the output voltage is 10% above or below its set voltage, PGD gets pulled low. It is held low until the output voltage returns to within +/-10% of the output set voltage. PGD is also held low during start-up and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. There is a 5µs delay built into the PGD circuitry to prevent false transitions. There is 100mV of hysteresis built into the UVLO circuit and when VCCA falls to 4.1V (nom.) the output drivers are shut down and tristated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off (below ~1V). Semtech’s SmartDriverTM FET drive first pulls DH high with a pullup resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this point, an additional pullup device is activated, reducing the resistance to 2Ω (typ.). This negates the need for an external gate or boost resistor. The adaptive dead time circuit also monitors the phase node, LX, to determine the state of the high side MOSFET, and prevents the low side MOSFET from turning on until DH is fully off (LX below ~1V). Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. Output Overvoltage Protection When the output exceeds 10% of the its set voltage the low-side MOSFET is latched on. It stays latched on and the controller is latched off until reset (see below). There is a 5µs delay built into the OV protection circuit to prevent false transitions. Output Undervoltage Protection When the output is 30% below its set voltage the output is latched in a tri-stated condition. It stays latched and the controller is latched off until reset (see below). There is a 5µs delay built into the UV protection circuit to prevent false transitions. Note: to reset from any fault, VCCA or EN/PSV must be toggled. Dropout Performance POR, UVLO and Softstart The output voltage adjust range for continuousconduction operation is limited by the fixed 550ns (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. An internal power-on reset (POR) occurs when VCCA exceeds 3V, starting up the internal biasing. VCCA undervoltage lockout (UVLO) circuitry inhibits the controller until VCCA rises above 4.2V. At this time the UVLO circuitry resets the fault latch and soft-start counter, 2005 Semtech Corp. 9 www.semtech.com SC1470 POWER MANAGEMENT The IC duty-factor limitation is given by: DUTY = schematic in Figure 4 on Page 15 will be designed. The maximum input voltage (VBAT(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (VBAT(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a VBAT range of 8V to 20V. t ON( MIN ) t ON( MIN ) + t OFF(MAX ) Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC1470 System DC Accuracy Four parameters are needed for the output: 1) nominal output voltage, VOUT (we will use 1.2V) 2) static (or DC) tolerance, TOLST (we will use +/-4%) 3) transient tolerance, TOLTR and size of transient (we will use +/-8% and 6A for purposes of this demonstration). 4) maximum output current, IOUT (we will design for 6A) Two IC parameters affect system DC accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. The error comparator threshold does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. A default RtON value of 1MΩ is suggested as a starting point, but this is not set in stone. The first thing to do is to calculate the on-time, tON, at VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT, VOUT and RtON. The on pulse in the SC1470 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be VOUT. For example: if VOUT is 2.5V and the ripple is 50mV with VBAT = 6V, then the measured DC output will be 2.525V. If the ripple increases to 80mV with VBAT = 25V, then the measured DC output will be 2.540V. For VOUT < 3.3V: VOUT −9 t ON _ VBAT(MIN) = 3.3 • 10 −12 • (R tON + 37 • 103 ) • + 50 • 10 s V BAT ( MIN) and VOUT −9 t ON _ VBAT (MAX ) = 3.3 • 10 −12 • (R tON + 37 • 10 3 ) • + 50 • 10 s V BAT ( MAX ) The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. It will not change the frequency. From these values of tON we can calculate the nominal switching frequency as follows: Switching frequency variation with load can be minimized by choosing MOSFETs with lower R DS(ON). High R DS(ON) MOSFETs will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. fSW _ VBAT (MIN ) = Design Procedure and Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage specifications. For purposes of demonstrating the procedure the output for the fSW _ VBAT (MAX ) = 2005 Semtech Corp. VOUT (VBAT (MIN) • t ON _ VBAT (MIN) )Hz VOUT (VBAT(MAX ) • t ON _ VBAT(MAX ) )Hz tON is generated by a one-shot comparator that samples 10 www.semtech.com SC1470 POWER MANAGEMENT VBAT via RtON, converting this to a current. This current is used to charge an internal 3.3pF capacitor to VOUT. The equations above reflect this along with any internal components or delays that influence tON. For our example we select RtON = 1MΩ: For our example: IINDUCTOR(MIN) = 7.1A(MIN) Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (R ESR_ST(MAX)) and transient ESR (R ESR_TR(MAX)): tON_VBAT(MIN) = 563ns and tON_VBAT(MAX) = 255ns fSW_VBAT(MIN) = 266kHz and fSW_VBAT(MAX) = 235kHz Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of IOUT which will give us a starting place. L VBAT (MIN) = (VBAT (MIN) − VOUT ) • t ON _ VBAT (MIN) (0.5 • I ) RESR _ ST (MAX ) = OUT and L VBAT (MAX ) = (VBAT (MAX ) − VOUT ) • (0.5 • I ) ST − ERRDC ) • 2 IRIPPLE _ VBAT (MAX ) Ohms Where ERRST is the static output tolerance and ERRDC is the DC error. The DC error will be 1% plus the tolerance of the feedback resistors, thus 2% total for 1% feedback resistors. H t ON _ VBAT (MAX ) (ERR For our example: H ERRST = 48mV and ERRDC = 24mV, therefore OUT For our example: RESR_ST(MAX) = 22mΩ LVBAT(MIN) = 1.3µH and LVBAT(MAX) = 1.6µH RESR _ TR (MAX ) = We will select an inductor value of 2.2µH to reduce the ripple current, which can be calculated as follows: IRIPPLE _ VBAT (MIN) = (VBAT (MIN) − VOUT ) • t ON _ VBAT (MIN) L A P −P t ON _ VBAT (MAX ) L TR − ERR DC ) I IOUT + RIPPLE _ VBAT (MAX ) 2 Ohms Where ERRTR is the transient output tolerance. Note that this calculation assumes that the worst case load transient is full load. For half of full load, divide the IOUT term by 2. and IRIPPLE _ VBAT (MAX ) = (VBAT (MAX ) − VOUT ) • (ERR For our example: A P −P ERRTR = 96mV and ERRDC = 24mV, therefore For our example: RESR_TR(MAX) = 10.2mΩ for a full 6A load transient IRIPPLE_VBAT(MIN) = 1.74AP-P and IRIPPLE_VBAT(MAX) = 2.18AP-P We will select a value of 12.5mΩ maximum for our design, which would be achieved by using two 25mΩ output capacitors in parallel. From this we can calculate the minimum inductor current rating for normal operation: IINDUCTOR (MIN) = IOUT (MAX ) + 2005 Semtech Corp. IRIPPLE _ VBAT (MAX ) 2 Note that for constant-on converters there is a minimum ESR requirement for stability which can be calculated as follows: A (MIN) 11 www.semtech.com SC1470 POWER MANAGEMENT RESR (MIN ) value of VFB based upon the selected CTOP: 3 = 2 • π • COUT • fSW R BOT = VRIPPLE _ VBAT(MIN) • 1 RBOT + 1 + 2 • π • fSW _ VBAT(MIN) • C TOP R TOP This criteria should be checked once the output capacitance has been determined. VFB _ VBAT(MIN) Now that we know the output ESR we can calculate the output ripple voltage: For our example: VFB_VBAT(MIN) = 14.8mVP-P - good VRIPPLE _ VBAT(MAX) = RESR • IRIPPLE _ VBAT(MAX) VP −P Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, VOUT_ST_POS, when a load release occurs: and VRIPPLE _ VBAT(MIN) = RESR • IRIPPLE _ VBAT(MIN) VP −P For our example: VOUT _ ST _ POS = VOUT + ERRDC V VRIPPLE_VBAT(MAX) = 27mVP-P and VRIPPLE_VBAT(MIN) = 22mVP-P For our example: Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mVP-P at minimum V BAT , and worst case no smaller than 10mV P-P . If VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component values should be revisited in order to improve this. Quite often a small capacitor, CTOP, is required in parallel with the top feedback resistor, RTOP, in order to ensure that V FB is large enough. C TOP should not be greater than 100pF. The value of CTOP can be calculated as follows, where R BOT is the bottom feedback resistor. Firstly calculating the value of ZTOP required: Z TOP VOUT_ST_POS = 1.224V POSLIM TR = VOUT • TOL TR V Where TOLTR is the transient tolerance. For our example: POSLIMTR = 1.296V The minimum output capacitance is calculated as follows: 2 R = BOT • (VRIPPLE _ VBAT (MIN) − 0.015 ) Ohms 0.015 C OUT (MIN) Secondly calculating the value of CTOP required to achieve this: C TOP I IOUT + RIPPLE _ VBAT (MAX ) 2 =L• F 2 2 POSLIM TR − VOUT _ ST _ POS ( ) This calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps my be calculated by substituting the desired current for the IOUT term. 1 1 − Z TOP R TOP F = 2 • π • fSW _ VBAT (MIN) For our example we will use R TOP = 20.0kΩ and RBOT = 14.3kΩ, therefore: For our example: COUT(MIN) = 610µF. ZTOP = 6.67kΩ and CTOP = 60pF We will select 440µF, using two 220µF, 25mΩ capacitors in parallel. For smaller load release overshoot, We will select a value of CTOP = 56pF. Calculating the 2005 Semtech Corp. VP −P 12 www.semtech.com SC1470 POWER MANAGEMENT 660µF may be used. Alternatively, one 15mΩ or 12mΩ 220µF, 330µF or 470µF capacitor may be used (with the appropriate change to the calculation for C TOP), depending upon the load transient requirements. Where: TA = ambient temperature (°C) PD = power dissipation in (W) θJA = thermal impedance junction to ambient from absolute maximum ratings (°C/W) Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage: IIN(RMS ) = VOUT • (VBAT (MIN) − VOUT ) • IOUT VBAT _ MIN The power dissipation may be calculated as follows: A RMS PD = VCCA • IVCCA + VDDP • IVDDP + Vg • Q g • f + VBST • 1mA • D For our example: IIN(RMS) = 2.14ARMS Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) VDDP = gate drive supply voltage (V) IVDDP = gate drive operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) VBST = boost pin voltage during tON (V) D = duty cycle Input capacitors should be selected with sufficient ripple current rating for this RMS current, for example a 10µF, 1210 size, 25V ceramic capacitor can handle approximately 3A RMS . Refer to manufacturer’s data sheets. Finally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the “valley current”, which is the average output current minus half the ripple current. We use the maximum room temperature specification for MOSFET RDS(ON) at VGS = 4.5V for purposes of this calculation: IRIPPLE _ VBAT (MIN) W Inserting the following values for VBAT(MIN) condition (since this is the worst case condition for power dissipation in the controller) as an example (VOUT = 1.2V): For our example: TA = 85°C θJA = 100°C/W VCCA = VDDP = 5V IVCCA = 1100µA (data sheet maximum) IVDDP = 150µA (data sheet maximum) Vg = 5V Qg = 60nC f = 266kHz VBAT(MIN) = 8V VBST(MIN) = VBAT(MIN)+VDDP = 13V D(MIN) = 1.2/8 = 0.15 IVALLEY = 5.13A, RDS(ON) = 9mΩ and RILIM = 7.76kΩ gives us: We select the next lowest 1% resistor value: 7.68kΩ PD = 5 • 1100 • 10 −6 + 5 • 150 • 10 −6 Thermal Considerations + 5 • 60 • 10 −9 • 266 • 10 3 + 13 • 1 • 10 −3 • 0.15 = 0.088 W IVALLEY = IOUT − 2 A The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions. RILIM = (IVALLEY • 1.2) • RDS( ON) • 1.4 10 • 10 − 6 Ohms and: The junction temperature of the device may be calculated as follows: TJ = 85 + 0.088 • 100 = 93 .8 TJ = TA + PD • θ JA 2005 Semtech Corp. °C °C 13 www.semtech.com SC1470 POWER MANAGEMENT As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout. 2005 Semtech Corp. 14 www.semtech.com SC1470 POWER MANAGEMENT Layout Guidelines VBAT 5VSUS R1 1M 0402 R2 10R 0402 5VSUS 1 2 C5 56p 0402 VOUT 3 R3 20k0 0402 4 U1 SC1470 EN/PSV TON VOUT VCCA BST DH LX ILIM VBAT D1 SOD323 C1 0.1uF 14 0603 13 Q1 IRF7811AV 12 6 PGOOD 1nF 0402 C4 0u1/25V 0603 10u/25V 1210 L1 2u2 R4 7k87 11 VOUT C6 FB VDDP PGD DL 10 + Q2 FDS6676S 9 C9 C8 C3 2n2/50V 0402 0402 5 R7 14k3 0402 C2 C10 1uF 0603 7 VSSA PGND 8 R6 0R (1) C7 + 220u/25m 7343 220u/25m 7343 0402 1uF 0603 N OTES (1) R 6 is not required but aids k eeping VSSA s eparate f rom PGN D ex c ept where des ired in lay out. VBAT = 8V to 20V VOUT = 1.2V @ 6A Figure 4: Reference Design One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground reference, VSSA, should be kept separate from power ground. All components that are referenced to VSSA should connect to it locally at the chip. VSSA should connect to power ground at the output capacitor(s) only. The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the feedback trace with VSSA as a differential pair from the output capacitor back to the chip. Run them in a “quiet layer” if possible. VSSA may be separated from PGND using a zero Ohm resistor (that will be placed at the bottom of the output capacitors) to aid in net separation. Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins (VDDP and PGND, VCCA and VSSA) and connected directly to them on the same side. Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in more detail. 2005 Semtech Corp. 15 www.semtech.com SC1470 POWER MANAGEMENT The layout can be considered in two parts, the control section referenced to VSSA and the power section. Looking at the control section first, locate all components referenced to VSSA on the schematic and place these components at the chip. Connect VSSA using either a wide (>0.020”) trace or a copper pour if room allows. Very little current flows in the chip ground therefore large areas of copper are not needed. VBAT 5VSUS R1 1M 0402 R2 10R 0402 5VSUS 1 2 VOUT C5 56p 0402 3 R3 20k0 0402 4 5 6 PGOOD U1 SC1470 EN/PSV BST TON DH VOUT LX VCCA ILIM FB VDDP PGD DL 14 13 12 11 10 9 C9 C8 1nF 0402 R7 14k3 0402 C10 7 VSSA PGND 1uF 0603 8 1uF 0603 Figure 5: Components Connected to VSSA Figure 6: Example VSSA 0.020” Trace In Figure 6 above, all components referenced to VSSA have been placed and have been connected using a 0.020” trace. Decoupling capacitors C9 and C10 are as close as possible to their pins. C9 should connect to the ground plane using two vias. 2005 Semtech Corp. 16 www.semtech.com SC1470 POWER MANAGEMENT As shown below, VOUT and VSSA should be routed as a differential pair to the output capacitor(s). 1 2 VOUT C6 56p 0402 3 R4 20k0 0402 4 U2 SC470 EN/PSV 14 BST TON 13 DH VOUT LX VCCA ILIM 12 VOUT 11 C14 + 5 6 R8 14k3 0402 7 C11 FB 10 VDDP PGD R12 0R (2) 9 DL VSSA C7 + 220u/25m 7343 220u/25m 7343 0402 8 PGND 1uF 0603 VSSA VOUT Figure 7: Differential Routing of Feedback and Ground Reference Traces Next, the schematic in Figure 8 below shows the power section. The highest di/dts occur in the input loop (highlighted in red) and thus this loop should be kept as small as possible. VBAT Q1 IRF7811AV C2 C3 C4 2n2/50V 0402 0u1/25V 0603 10u/25V 1210 L1 2u2 VOUT C6 + Q2 FDS6676S R6 0R (2) C7 + 220u/25m 7343 220u/25m 7343 0402 Figure 8: Power Section and Input Loop The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. See Figure 9 for an example. 2005 Semtech Corp. 17 www.semtech.com SC1470 POWER MANAGEMENT Figure 9: Power Component Placement and Copper Pours Key points for the power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. 4) Notice in Figure 9 above placement of the 0Ω resistor at the bottom of the output capacitor to connect to VSSA. 5) The current limit resistor should be placed as close as possible to the ILIM and LX pins. Connecting the control and power sections should be accomplished as follows (see Figure 10 below): 1) Route VSSA and VOUT as a differential pair routed in a “quiet” layer away from noise sources. 2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. 3) BST is also a noisy node and should be kept as short as possible. 4) Connect PGND pin on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the ground plane. 2005 Semtech Corp. 18 www.semtech.com SC1470 POWER MANAGEMENT 1 2 3 4 5 6 7 U1 EN/PSV TON VOUT VCCA FB PGD VSSA SC470 BST DH LX ILIM VDDP DL PGND Q1 IRF7811AV 14 13 12 11 10 R4 0402 L1 7k87 2u2 Q2 FDS6676S 9 8 Figure 10: Connecting the Control and Power Sections 2005 Semtech Corp. 19 www.semtech.com SC1470 POWER MANAGEMENT Typical Characteristics 1.2V Efficiency (Power Save Mode) 1.2V Efficiency (Continuous Conduction Mode) vs. Output Current vs. Input Voltage vs. Output Current vs. Input Voltage 100 100 95 95 VBAT = 8V 90 85 80 Efficiency (%) 85 Efficiency (%) VBAT = 8V 90 VBAT = 20V 75 70 80 70 65 65 60 60 55 55 50 VBAT = 20V 75 50 0 1 2 3 4 5 6 0 1 2 3 IOUT (A) 1.2V Output Voltage (Power Save Mode) vs. Output Current vs. Input Voltage 1.216 1.216 1.212 1.212 VOUT (V) VOUT (V) 1.208 VBAT = 20V 1.200 1.196 VBAT = 8V 1.192 VBAT = 20V 1.204 1.200 1.196 VBAT = 8V 1.192 1.188 1.188 1.184 1.184 1.180 1.180 0 1 2 3 4 5 6 0 1 2 3 IOUT (A) 4 5 6 IOUT (A) 1.2V Switching Frequency (Power Save Mode) 1.2V Switching Frequency (Continuous Conduction vs. Output Current vs. Input Voltage Mode) vs. Output Current vs. Input Voltage 400 400 VBAT = 8V VBAT = 8V 350 350 300 300 250 Frequency (kHz) Frequency (kHz) 6 vs. Output Current vs. Input Voltage 1.220 1.204 5 1.2V Output Voltage (Continuous Conduction Mode) 1.220 1.208 4 IOUT (A) VBAT = 20V 200 150 250 150 100 100 50 50 0 VBAT = 20V 200 0 0 1 2 3 4 5 6 0 1 2 IOUT (A) 3 4 5 6 IOUT (A) Please refer to Figure 4 on Page 15 for test schematic 2005 Semtech Corp. 20 www.semtech.com SC1470 POWER MANAGEMENT Typical Characteristics (Cont.) Load Transient Response, Continuous Conduction Mode, 0A to 6A to 0A Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40µs/div. Load Transient Response, Continuous Conduction Mode, 0A to 6A Zoomed Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10µs/div. Load Transient Response, Continuous Conduction Mode, 6A to 0A Zoomed Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10µs/div. Please refer to Figure 4 on Page 15 for test schematic 2005 Semtech Corp. 21 www.semtech.com SC1470 POWER MANAGEMENT Typical Characteristics (Cont.) Load Transient Response, Power Save Mode, 0A to 6A to 0A Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40µs/div. Load Transient Response, Power Save Mode, 0A to 6A Zoomed Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10µs/div. Load Transient Response, Power Save Mode, 6A to 0A Zoomed Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10µs/div. Please refer to Figure 4 on Page 15 for test schematic 2005 Semtech Corp. 22 www.semtech.com SC1470 POWER MANAGEMENT Typical Characteristics (Cont.) Startup (PSV), EN/PSV Going High Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div. Startup (CCM), EN/PSV 0V to Floating Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div. Please refer to Figure 4 on Page 15 for test schematic 2005 Semtech Corp. 23 www.semtech.com SC1470 POWER MANAGEMENT Marking Information Bottom Mark Top Mark xxxxxx = Wafer Lot Number xx = Assembly Lot Number yy = two-digit year of manufacture ww = two-digit week of manufacture Outline Drawing - TSSOP-14 A D DIM A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc 2X E/2 E1 E PIN 1 INDICATOR ccc C 2X N/2 TIPS 1 2 3 e B aaa C SEATING PLANE DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX .047 .006 .002 .042 .031 .012 .007 .003 .007 .193 .197 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 14 0° 8° .004 .004 .008 1.20 0.15 0.05 1.05 0.80 0.19 0.30 0.20 0.09 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 14 0° 8° 0.10 0.10 0.20 D A2 A A1 C bxN bbb C A-B D H c GAGE PLANE 0.25 L (L1) DETAIL SIDE VIEW SEE DETAIL 01 A A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB-1. 2005 Semtech Corp. 24 www.semtech.com SC1470 POWER MANAGEMENT Land Pattern - TSSOP-14 X DIM (C) G DIMENSIONS INCHES MILLIMETERS C G P X Y Z Z Y (.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2005 Semtech Corp. 25 www.semtech.com