SC2441A
1.8V to 20V Input 2-Phase Synchronous
Step-down Controllers with Step-up Converter
POWER MANAGEMENT
Description
Features
The SC2441A is a programmable frequency dual
independent or dual/multiple phase single output peak
current-mode step-down switching regulator controller. It
is capable of operating from 1.8V to 20V input. A 0.6A
step-up converter in the SC2441A generates an auxiliary
gate drive supply when VIN is below 4.5V. This makes the
SC2441A well suited for applications where a low-voltage
input (<3.3V) is to be stepped down for lower voltage logic,
yet the input is too low to drive power MOSFETs
efficiently.
2-Phase Synchronous Step-down Controllers
u 2-Phase Synchronous Continuous Conduction Mode
u Out of Phase Operation for Low Input Current Ripple
u Operates up to 1MHz Per Channel
u Excellent Current Sharing Between Phases
u Duty Cycle Up to 90%
u 0.5V Feedback voltages for Low-Voltage Outputs
u Starts into Pre-biased Outputs
u Adaptive Shoot-through Protection
u Lossless Inductor DCR Current Sensing
u 23mV Current-limit Threshold
u Individual Soft-start, Overload Hiccup and Enable
Step-up Regulator
u 0.27V VCESAT Switch at 0.6A
u Fixed frequency Current-mode Control
Common Features
u Wide input Voltage Range: 1.8V to 20V
u Synchronizing Frequency Equal to that of the Stepdown Converters
u 28-lead TSSOP-EDP Lead-free package, fully WEEE
and RoHS compliant
The SC2441A employs a phase-locked synchronizing
circuit that allows the step-up converter to operate at
twice the switching frequency of the step-down
controllers for miniaturization. The clock output signal
enables two or more SC2441As to be daisy chained with
programmable phase shift.
Tying the FB2 pin to VIN makes the second step-down
channel a slave of the first. Operating in this mode, the
SC2441A regulates a single output with shared current in
each channel. Each step-down controller has its own softstart and overload shutdown timer for hiccup overload
protection. In the single-output mode, the channel 1 timer
controls the soft-start and overload hiccup of both
controllers.
Applications
u Low voltage distributed DC-DC converters
u Telecommunication power supplies
u Servers and base stations
Typical Application Circuit
Vin
VCC
C1
VCC
R1
R2
C2
L1
R5
1
R6
27
21
C6
25
Q2
23
L2
C8
R8
FB3
IN
SW3
VCC
CKOUT
BST1
BST2
GDH1
GDH2
7
8
R7
28
18
C7
Q1
19
R9
D5
Q4
R11
C9
22
24
RCS+1
26
4
5
11
C19
R19
R20
12
GDL1
GDL2
20
R13
R12
PGND2
PLLF
CS1+
CS2+
CS1-
CS2-
FB1
FB2
COMP1
COMP2
RCS+2
2
16
15
14
C20
13
R18
C22
ROSC SYNC/SHDN
SS1/EN1
9
GND
C12
R16
C21
10
C11
PGND1
R25
Power
Ground
VOUT2
L3
D4
R15
Signal
Ground
COMP3
Q3
R10
C13
R3
C5
U1
D3
VOUT1
D1
C3
R4
C4
D2
SS2/EN2
6
R21
Vin
C23
R26
3
R23
R24
VCC
17
C26
R27
C25
C24
SC2441A
Figure 1
Revision: February 04, 2009
1
www.semtech.com
SC2441A
POWER MANAGEMENT
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum Ratings
Units
Input Voltage
VIN
-0.3 to 20
V
Supply Voltage For Step-Down Controller
VCC
-0.3 to 20
V
VBST1, VBST2
-0.3 to 28
V
VFB1, VFB2
-0.3 to 20
V
VCOMP1, VCOMP2
-0.3 to 4.5
V
VCS1(+), VCS1(-), VCS2(+), VCS2(-)
-0.3 to VCC
V
VS/S
-0.3 to VIN+1
V
VROSC
-0.3 to 2
V
VSS1, VSS2
-0.3 to 4
V
FB3 Voltage
VFB3
4
V
SW3 Voltage
VSW3
-0.3 to 30
V
Maximum Junction Temperature
TJ
150
°C
Thermal Resistance Junction to Case
θJC
2
°C/W
Thermal Resistance Junction to Ambient
θJA
37
°C/W
Storage Temperature Range
TSTG
-60 to 150
°C
Lead Temperature (Soldering) 10 sec
TLEAD
300
°C
ESD Ratings (Human Body Model)
ESD
2000
V
High-Side Driver Supply Voltages
FB1, FB2 Voltage
COMP1, COMP2 Voltages
CS1(+), CS1(-), CS2(+) and CS2(-)
Voltages
SY NC/SHDN Voltage
ROSC Voltage
SS1/EN1 AND SS2/EN2 Voltages
Electrical Characteristics
Unless specified: VIN = 2V, VCC = VBST1 = VBST2 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < TA = TJ < 105°C
Parameter
Symbol
Conditions
VCC Start Threshold
VCCTH
VCC UVLO Hysteresis
Min
Typ
Max
Units
VCC Increasing
4.45
4.55
V
VCCTL
VCC Decreasing
150
VCC = 8V, VS/S = 2V
VCC = 4V, VCCTL, VS/S = 2V
VCC = 8V, VS/S = 0V (2)
10
0.05
8
15
1.0
11
mA
ICC
V F B 1, V F B 2
VIN = 3V, 5V < VCC < 10V
0.494
0.500
0.506
V
VIN = 3V, 5V < VCC < 10V,
-40°C to 85°C
0.495
0.500
0.505
V
IFB1
-60
-200
nA
IFB2
-280
-500
nA
Amplifier Transconductance
GM1, GM2
315
µΩ−1
Open Loop Voltage Gain
a o1, a o2
75
dB
5
MHz
Undervoltage Lockout
VCC Input Current
mV
Channel 1 and 2 Error Amplifiers
Feedback Voltage
Feedback Pin Input Bias Current
Amplifier Unity Gain Bandwidth
(Note 1)
Amplifier Output Sink Current
VFB1, 2 = 1V, VCOMP1,2 = 2.5V
16
24
29
µA
Amplifier Output Source Current
VFB1, 2 = 0V, VCOMP1,2 = 2.5V
9
13
16
µA
2006 Semtech Corp.
2
www.semtech.com
SC2441A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VIN = 2V, VCC = VBST1 = VBST2 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < TA = TJ < 105°C
Parameter
Symbol
COMP Threshold for PWM Operation
Conditions
Min
Typ
Max
Units
VCS1(+) = VCS1(-) = 0
VCS2(+) = VCS2(-) = 0
1.67
1.85
2.05
V
FB2 Voltage For 2-Phase Single Output
Mode of Operation
1.55
V
Oscillator and Phase-Locked Loop
Free Running Frequency
fCCO
TJ = 25°C; VPLLF > 1V
450
500
Minimum Locking Frequency
V P LLF o p e n
Free Running Frequency / Minimum Locking
Frequency
TJ = 25°C
1.7
2.0
VPLLF=1V
10
15
88
90
Charge Pump Output Current
IPLLF
Maximum Duty Cycle
DMAX1,
DMAX2
Minimum Duty Cycle
DMIN1, DMIN2
SYNC/SHDN Input High Voltage
VS/SH
SYNC/SHDN Input Low Voltage
VS/SL
SYNC/SHDN Input Current
550
240
KHz
20
1.5
Shutdown Delay
µA
%
0
IS/S
KHz
%
V
0.5
V
1
60
µA
VS/S = 0.2V
VS/S = 2V
40
(Note 1)
85
µs
1.8
V
Clock Output High Voltage
CKOUTH
ICKOUT = -80µA
Clock Output Low Voltage
CKOUTL
ICKOUT = 200µA
1.6
0.4
V
V CC - 1
V
Current-Sense Amplifiers, PWM and Current-Limit Comparators
Input Common Mode Range
0
Current Limit Threshold
VILIM1, VILIM2
V C C = 8V
VCS1(-) = VCS2(-) = 0V
18
23
28
mV
Current Limit Threshold
VILIM1, VILIM2
V C C = 8V
VCS1(-) = VCS2(-) = 5V
18
23
28
mV
Positive Current-Sense Input Bias Current
ICS1(+), ICS2(+)
VCS1(+) = VCS1(-) = 0
VCS2(-) = VCS2(-) = 0
-0.4
-0.8
µA
Negative Current-Sense Input Bias Current
ICS1(-), ICS2(-)
VCS1(+) = VCS1(-) = 0
VCS2(+) = VCS2(-) = 0
-40
-75
µA
TA = 25°C, (Note 1)
180
ns
High-Side Gate Drive Peak Source Current
(Note 1)
2
A
High-Side Gate Drive Peak Sink Current
(Note 1)
2
A
Low-Side Gate Drive Peak Source Current
(Note 1)
2
A
Minimum PWM On-time
Gate Drivers
2006 Semtech Corp.
3
www.semtech.com
SC2441A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VIN = 2V, VCC = VBST1 = VBST2 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < TA = TJ < 105°C
Parameter
Symbol
Conditions
Low-Side Gate Drive Peak Sink Current
Min
Typ
Max
Units
(Note 1)
2
A
Gate Drive Rise Time
C L = 3300pF
30
ns
Gate Drive Fall Time
C L = 3300pF
30
ns
VSS1 and VSS2 Increasing
3.3
V
Soft-Start, Overload Shutoff and Enable
Soft-Start Voltage to Enable Overload
Hiccup
VSSEN1,
VSSEN2
Overload Hiccup FB Threshold
VFBOL1,
VFBOL2
Soft-Start Discharge Current
ISS1(DIS),
ISS2(DIS)
VFB1 = VFB2 = 0.3V
V S S 1 = V S S 2 = 3V
Soft-Start Voltage to Restart After
Overload Shutdown
VSSRST1,
VSSRST2
VSS1 and VSS2 Decreasing
VSS1, 2 = 3.5V
FB1 and FB2 Decreasing
0.35
0.38
0.41
V
6
9
12
µA
0.5
Channel Disable SS/EN Voltage
VCS1(+) = VCS1(-) = 0
VCS2(+) = VCS2(-) = 0
SS/EN Threshold for PWM Operation
1.23
V
0.6
V
1.28
1.33
V
1.73
1.76
V
Boost Converter
VIN Start Threshold
VINTH
VIN Hysteresis
VINTL
100
Feedback Pin Bias Current
IFB3
40
250
nA
Feedback Voltage
V FB 3
1.250
1.275
V
Feedback Amplifier Transconductance
GM3
70
µΩ-1
Feedback Amplifier Open-Loop Gain
a o3
50
dB
Boost Converter Switching Frequency
fOSC3
1
MHz
Maximum Switch Duty Cycle
DMAX3
92
%
Boost Converter Switch Saturation Voltage
VCESAT
ISW = 0.6A
0.27
V
Boost Switch Leakage Current
ILEAKAGE
V S W = 12V
Boost Switch Current Limit
VIN Increasing
1.8V < VIN < 16.5V
1.225
85
ILIMIT
mV
5
0.6
µA
0.8
A
Thermal Shutdown
155
°C
Thermal Shutdown Hysteresis
10
°C
Notes:
(1) Guaranteed by design not tested in production.
(2) Input current is dominated by the equivalent gate drive current to external MOSFETs in active switching condition.
2006 Semtech Corp.
4
www.semtech.com
SC2441A
POWER MANAGEMENT
Pin Configurations
Ordering Information
Device
Top View
SC2441ATETRT(1,2)
IN
1
28
CKOUT
PLLF
2
27
SW3
SS1/EN1
3
26
PGND2
CS1+
4
25
BST1
CS1-
5
24
PGND1
SYNC/SHDN
6
23
GDH1
FB3
7
22
GDL1
COMP3
8
21
VCC
GND
9
20
GDL2
ROSC
10
19
GDH2
FB1
11
18
BST2
COMP1
12
17
SS2/EN2
COMP2
13
16
CS2+
FB2
14
15
CS2-
S C 2441A E V B
P ackag e
Temperature
Range ( TA)
TSSOP-28-EDP
-40 to 85°C
Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices for the TSSOP-28-EDP
package.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
TSSOP-28 EDP
2006 Semtech Corp.
5
www.semtech.com
SC2441A
POWER MANAGEMENT
Pin Descriptions
Pin
Pin Name
1
IN
2
P LLF
3
SS1/EN1
4
C S 1+
The Non-inverting Input to the Channel 1 Current-sense Amplifier/Comparator.
5
C S 1-
The Inverting Input to the Channel 1 Current-sense Amplifier/Comparator. Normally tied to the
output of the converter.
6
SYNC/SHDN
Synchronization and Shutdown Input. Tie this pin to IN (Pin 1) or to a voltage above 1.5V to enable
the SC2441A. Pulling this pin below 0.5V shuts off both step-down controllers and the boost
regulator. Driving this pin with an external clock synchronizes the SC2441A. The boost converter
runs at twice of the external clock frequency whereas the step-down controllers operate at the
clock frequency.
7
FB 3
The Inverting Input to Boost Error Amplifier. FB3 is tied to an external resistive divider for OUT3
voltage setting.
8
COMP3
Boost Converter Error Amplifier Output. Used for loop compensation. Pulling this pin below 0.4V
disables the step-up converter.
9
GND
10
ROSC
11
FB 1
12
COMP1
Channel 1 Error Amplifier Output. Used for loop compensation.
13
COMP2
Channel 2 Error Amplifier Output. Used for loop compensation.
14
FB 2
The Inverting Input to the Channel 2 Error Amplifier. Tie to an external resistive divider between
OUT2 and the ground for output voltage sensing. Tie to IN or VCC for two-phase single output
operation.
15
C S 2-
The Inverting Input to the Channel 2 Current-sense Amplifier/Comparator. Normally tied to the
output of the converter.
16
C S 2+
The Non-inverting Input to the Channel 1 Current-sense Amplifier/Comparator.
17
SS2/EN2
An external resistor and an external capacitor tied to this pin set the second step-down converter
soft-start time and its overload hiccup cycle time. Pulling this pin below 0.6V shuts off channel 2
gate drivers. Leave open for two-phase single output operation.
18
BST2
Bootstrapped Supply for Channel 2 Upper Gate Drive. Connect to a bootstrap capacitor and an
external diode.
19
GDH2
Gate Drive Output for Channel 2 Upper MOSFET. Gate drive voltage swings from ground to
VBST2.
2006 Semtech Corp.
Pin Function
Supply Voltage for the Boost Converter. Tie to VCC if boost converter is not used to generate
auxiliary supply.
Compensation Pin for the Phase Lock Loop.
An external resistor and an external capacitor tied to this pin set the first step-down converter
soft-start time and its overload hiccup cycle time. Pulling this pin below 0.6V shuts off channel 1
gate drivers.
Analog Ground.
An external resistor connected from this pin to GND sets the oscillator free-running frequency.
The Inverting Input to the Channel 1 Error Amplifier. Tie to an external resistive divider between
OUT1 and the ground for output voltage sensing.
6
www.semtech.com
SC2441A
POWER MANAGEMENT
Pin Descriptions (Cont.)
GDL2
Gate Drive Output for Channel 2 Synchronous MOSFET. Gate drive voltage swings from
ground to VCC.
21
VC C
Supply Voltage for Both Step-down Controllers and the Synchronous MOSFET Gate Drivers. The
boost converter generates VCC if VIN is not high enough to fully enhance the power MOSFETs
and the boost converter provides an auxiliary supply voltage for the step-down controllers. Tie
VCC to VIN if the boost converter is not needed.
22
GDL1
Gate Drive Output for Channel 1 Synchronous MOSFET. Gate drive voltage swings from
ground to VCC.
23
GDH1
Gate Drive Output for Channel 1 Upper MOSFET. Gate drive voltage swings from ground to
VBST1.
24
PGND1
25
BST1
26
PGND2
27
SW3
28
CKOUT
20
Exposed PAD
2006 Semtech Corp.
Power Ground Return of the Gate Drivers.
Bootstrapped Supply for Channel 1 Upper Gate Drive. Connect to a bootstrap capacitor and an
external diode.
Boost Switch Emitter.
Boost Switch Collector. Connect to a boost inductor and freewheeling diode.
Clock output. See timing diagram in Figure 5(b).
Must be properly soldered to the signal ground plane to enhance thermal conduction.
7
www.semtech.com
SC2441A
POWER MANAGEMENT
Block Diagram
CKOUT
28
PLLF
1.25V
IN
VIN UVLO
1.6/1.7V
REFERENCE
1
2
SYNC/SHDN
6
CLK2
FREQUENCY
CLK1
DIVIDER
OSCILLATOR
AND
PHAS E
DETECTOR
ROS C
10
COMP 1
12
CLK
0.5V
0.35V
VCC
21
FAULT
SLOP E COMP
BST1
25
UVLO
4.3V/4.5V
SHDN
SHDN
GDH1
SLOP E2
+
+ EA1
0.5V
FB1
-
11
23
-
R
+
S
PWM1
Q
TG1ON
SS1/EN1
Adaptive
Shoot-through
Protection
GDL1
3
22
-
1.25V
+
A2
GND
2R
9
Soft-Start
And
Overload
Hiccup
Control 1
1.25V
R
CS1+
4
CS15
+
SLOP E1
+
ISEN1
-
S
+
OL1
PGND1
DSBL1
24
CH 1
+
25mV
CH 2
ILIM1
-
SEL
B
A
Y
1.25V
+
A1
18
SEL
GDH2
ANALOG
SWITCH
+
+ EA2
0.5V
FB2
14
19
-
R
+
S
PWM2
-
Q
TG2ON
SS2/EN2
Adaptive
Shoot-through
Protection
VCC
GDL2
20
17
-
1.25V
+
A3
2R
1.25V
CS215
BST2
CLK2
COMP 2
13
CS2+
16
MUX
R
+
+ S
ISEN2
-
+
+
Soft-Start
And
Overload
Hiccup
Control 2
OL2
DSBL2
SLOP E2
ILIM2
I
25mV
-
Figure 2 Functional Diagram of the Step-down Controllers
2006 Semtech Corp.
8
www.semtech.com
SC2441A
POWER MANAGEMENT
Block Diagram
SW3
COMP3
8
27
CLK
FB3
7
1.25V
+
EA3
-
R
+
S
PWM3
Q
+
ILIM3
-
SLOPE
COMP
+
Σ
I-LIMIT
+
R
SENSE
+
ISEN3
-
26
PGND2
Figure 3. Step-up Converter Functional Diagram
VCC
FB
+
C3
-
0.35V
RSS
S
0.5V/3.3V
CSS
0.8V
OL
(OVERLOAD)
Q
C1
SS/EN
HICCUP
DISABLE
R
TURN OFF
GATE DRIVES
L1
S
C2
+
Q
DSBL
R
L2
UV
FAULT
Q1
TGON
10µA
SHDN
UV = “1” IF VCC < 4.5V
SHDN = “1” IF SYNC/SHDN < 0.5V
Soft-Start and
Overload
Hiccup Control
Figure 2
Figure 4 Details of Soft-Start and Overload Hiccup Control Circuit
2006 Semtech Corp.
9
www.semtech.com
SC2441A
POWER MANAGEMENT
Block Diagram
1.5V
INTERNAL
CLAMP
SYNC/SHDN
6
XCLK
IPLLF
PHASE /
FREQUENCY
DETECTOR
QU
QD
CURRENTCONTROLLED
OSCILLATOR
PLLF
1K
2
S1
0.4V
S2
+
+
EXT CLOCK
BUFFER
V/I
ROSC
R1
IPLLF
C2
ROSC
C1
EXTERNAL PLL
COMPENSATION
CKOUT
10
R2
OPTIONAL
RESISTOR FOR
SETTING PHASE
SHIFT
SETS FREE RUNNNG
FREQUENCY
QT
28
TOGGLE
FLIP-FLOP
QT
CLK1
CLK
CLK2
(a)
CLK
XCLK
QT
QT
CKOUT
CLK1
CLK2
GDH1
GDH2
(b)
Figure 5. Phase-Locked Loop (a) and Its Timing Diagram in Locked Condition (R2 not Used) (b).
2006 Semtech Corp.
10
www.semtech.com
SC2441A
POWER MANAGEMENT
4.5V
Vcc
VSOFT-START
3.3V
Enable Hiccup
VCOMP
1.85V
VOUT
1.25V
PWM
Figure 6a. SC2441A Start-up Timing Diagram
VSOFT-START-CAP
3.3V
VO
0.8V
70% X VO Setpoint
1.25V
1.85V
Enable
Hiccup
VCOMP
VO
PWM
0.5V
Disable Hiccup
restart
Figure 6b. SC2441A Overload Hiccup Operation Timing Diagram
2006 Semtech Corp.
11
www.semtech.com
SC2441A
POWER MANAGEMENT
Typical Characteristics
Step-down Channel Feedback
vs Temperature
Step-down Channel Switching Frequency
v s Temperature
0.55
650
ROSC = 40.2KW
600
Frequency (KHz)
Reference Voltage (V)
0.53
0.51
0.49
550
ROSC = 51.1KW
500
450
0.47
ROSC = 66.5KW
400
V IN = 3V VCC = 8V
0.45
-50
-25
0
25
50
75
100
350
125
-50
Temperature (°C)
-25
0
25
50
75
100
125
Temperature (°C)
Feedback Pin Input Bias Current vs
Temperature
Percenatge Frequency Deviation
From Nominal vs Temperature
5
400
Feedback Pin Input Bias Current (nA)
ROSC = 66.5KW
4
3
Deviation (%)
2
1
ROSC = 40.2KW
0
-1
-2
-3
-4
ROSC = 51.1KW
-25
0
300
250
200
150
VCOMP1 = 3V
50
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Temperature (°C)
Amplifier Transconductance vs Temperature
Amplifier Open Loop Gain vs Temperature
400
80
380
79
Amplifier Open Loop Gain (dB)
Amplifier Transconductance ( mW -1 )
Channel 1
100
Temperature (°C)
360
340
320
300
280
260
240
220
200
78
77
76
75
74
73
72
71
70
-50
-25
0
25
50
75
100 125
-50
Temperature (°C)
2006 Semtech Corp.
Channel 2
0
-5
-50
V COMP2 = 3V
350
-25
0
25
50
75
100 125
Temperature (°C)
12
www.semtech.com
SC2441A
POWER MANAGEMENT
Typical Characteristics
SYNC/SHDN Input Voltage vs Temperature
Charge Pump Current IPLLF vs Temperature
1.5
VPLLF = 1V
19.0
SYNC/SHDN Input High Voltage (V)
Charge Pump Current I
PLLF
(µ A)
20.0
18.0
17.0
16.0
15.0
14.0
13.0
12.0
11.0
10.0
-50
-25
0
25
50
75
100 125
1.4
1.3
SYNC/SHDN Input High
1.2
1.1
1.0
SYNC/SHDN Input Low
0.9
Temperature (°C)
-50
-25
0
25
50
75
100 125
Temperature (°C)
Clock Output High Voltage vs Temperature
Clock Output Low Voltage vs Temperature
0.08
1.95
1.90
Clock Output Low Voltage (V)
Clock Output High Voltage (V)
2.00
ICLK_OUT = - 80 µA
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
-50
-25
0
25
50
75
0.07
0.06
ICLK_OUT = 200 µA
0.05
0.04
0.03
100 125
-50
Temperature (°C)
-25
0
25
50
75
100 125
Temperature (°C)
Current Sense Amplifier Input Bias Current vs
Temperature (Non-inverting Pin)
Current Sense Amplifier Input Bias
Current ( µ A)
-0.40
-0.45
-0.50
-0.55
V CC = 8V, VCS1 (-) = VCS2 (-) = 0V
-0.60
-50
-25
0
25
50
75
100
125
Temperature (°C)
2006 Semtech Corp.
13
www.semtech.com
SC2441A
POWER MANAGEMENT
Typical Characteristics
Current Sense Amplifier Input Bias Current vs
Temperature (Inverting Pin)
Overload Hiccup Threshold vs Temperature
4.0
0.400
-30
-35
V CC = 8V, VCS1 (-) = VCS2 (-) = 0V
-40
0.395
0.390
0.385
0.380
0.375
0.370
0.365
0.360
V SS1,2 = 3.5V
0.355
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
50
75
8.0
7.5
V F B1=VFB2=0.3V, VSS1=VSS2=3V
7.0
0.58
0.56
0.54
0.52
0.50
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100 125
1.22
V FB1=VFB2=0.03V
0
25
50
75
Temperature (°C)
2006 Semtech Corp.
100 125
75
100
125
0.81
0.79
0.77
V FB1=VF B2=0.45V, VCOMP1=VCOMP2=2V
0.75
-25
0
25
50
75
100 125
VIN Hysteresis Voltage vs Temperature
0.110
0.105
1.74
1.73
1.72
1.71
0.100
0.095
0.090
0.085
0.080
0.075
1.70
1.20
50
Temperature (°C)
VIN Hysteresis Voltage (V)
1.24
VIN Start-up Threshold Voltage (V)
1.26
25
0.83
-50
1.75
1.28
0
Soft-Start Disable Voltage vs Temperature
VIN Start-up Threshold Voltage vs Temperature
1.30
-25
-25
Temperature (°C)
Soft-Start Threshold Voltage (to Eable PWM
Operation) vs Temperature
-50
3.2
Temperature (°C)
Soft-Start Voltage (to Restart Overload
Shutdown) (V)
8.5
0
3.4
-50
100 125
0.60
Soft-Start Voltage (to Restart
Overload Shutdown) (V)
Soft-Start Discharge Current ( µA)
25
Soft-Start Voltage (to Restart Overload Shutdown)
vs Temperature
9.0
-25
3.6
Temperature (°C)
Soft-Start Discharge Current vs Temperature
-50
3.8
3.0
0.350
-50
Soft-Start Threshold Voltage (to
Eable PWM Operation) (V)
Soft-Start Voltage Threshold (to
Enable Overload Hiccup
Protection) (V)
Overload Hiccup Threshold (V)
Current Sense Amplifier Input Bias
Current ( µ A)
-25
Soft-Start Voltage Threshold (to Enable Overload
Hiccup Protection) vs Temperature
-50
-25
0
25
50
75
Temperature (°C)
14
100
125
-50
-25
0
25
50
75
100 125
Temperature (°C)
www.semtech.com
SC2441A
POWER MANAGEMENT
Typical Characteristics
Boost Section Feedback Pin Bias Current vs
Temperature
Boost Section Feedback Voltage vs Temperature
105
60
55
50
45
40
35
30
25
1.26
1.24
1.22
1.8V < VIN < 16.5V
1.20
-50
-25
0
25
50
75
100
125
-50
-25
0
53
52
51
50
25
50
75
100
100
75
65
-50
-25
0
75
100 125
Boost Section Switch Saturation Voltage vs
Temperature
0.80
0.75
0.70
0.65
0.33
0.31
0.29
0.27
ISW
=
0.6A
0.25
-25
0
25
50
75
-50
100 125
-25
0
25
50
75
100 125
Temperature (°C)
Temperature (°C)
Bottom Gate Driver Transition Time vs Load
Capacitance
100
100
VCC = 5V
VCC = 12V
80
80
60
Transition Time (nS)
tf
tr
40
tf
60
40
tr
20
20
25°C
25°C
0
0
1
0
10
1
10
Load Capacitance (nF)
Load Capacitance (nF)
2006 Semtech Corp.
50
0.35
Bottom Gate Driver Transition Time vs Load
Capacitance
0
25
Temperature (°C)
0.85
0.60
-50
125
Temperature (°C)
Transition Time (nS)
85
55
125
Boost Section Switch Saturation
Voltage (V)
Boost Section Switch Current Limit
(A)
54
0
75
0.90
55
-25
50
Boost Section Switch Current Limit vs
Temperature
Boost Section Amplifier Open Loop Gain vs
Temperature
56
-50
25
95
Temperature (°C)
Temperature (°C)
Boost Section Amplifier Open
Loop Gain (dB)
Boost Section Amplifier
Transconductance (mW -1 )
1.28
Boost Section Reference Voltage (V)
Boost Section Feedback Pin Bias
Current (nA)
65
Boost Section Amplifier Transconductance vs
Temperature
15
www.semtech.com
SC2441A
POWER MANAGEMENT
Typical Characteristics
Pe rce ntage De viation In
Phase Shift vs Temperature
Phase Shift vs Temperature
25
225
20
R2 = 36.5KW
R2 = 71.5KW
90
R2 = 143KW
45
0
0
5
R2 = 71.5KW
0
-5
25
50
75
100
R2 = 68.1KW
fSYNC = 500KHz
-50
-25
0
25
50
75
100
0
-50
125
Phase Shift vs Temperature
225
180
R2 = 31.6KW
135
R2 = 41.2KW
90
R2 = 61.9KW
-10
75
100
125
ROSC = 66.5KW
fSYNC = 400KHz
25
50
75
100
-50
125
-20
R2 = 61.9KW
-30
ROSC = 66.5KW
R2 = 121KW
fSYNC = 300KHz
-60
0
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Temperature (°C)
R2 = 31.6KW
R2 = 41.2KW
-50
fSYNC = 300KHz
R2 = 34.8KW
-20
0
-10
-40
R2 = 121KW
45
ROSC = 51.1KW
Upper Gate Driver Transition Time vs Load
Capacitance
Upper Gate Driver Transition Time vs Load
Capacitance
100
100
VCC = 12V
V CC = 5V
80
80
tf
60
Transition Time (nS)
Transition Time (nS)
50
10
Phase Deviation (%)
Phase (deg)
Phase Deviation (%)
R2 = 46.4KW
tr
40
tf
60
40
20
20
tr
25°C
25°C
0
0
0
1
0
10
1
10
Load Capacitance (nF)
Load Capacitance (nF)
2006 Semtech Corp.
25
20
R2 = 140KW
0
0
Percentage Deviation In
Phase Shift vs Temperature
30
10
-25
-25
Temperature (°C)
R2 = 68.1KW
-50
R2 = 140KW
fSYNC = 400KHz
R2 = 143KW
Temperature (°C)
Pe rce ntage De viation In
Phase Shift vs Temperature
0
ROSC = 51.1KW
ROSC = 40.2KW
Temperature (°C)
20
R2 = 46.4KW
90
45
-25
125
R2 = 34.8KW
135
-10
-20
fSYNC = 500KHz
-25
10
-15
ROSC = 40.2KW
-50
180
R2 = 36.5KW
Phase (deg)
R2 = 47.5KW
135
R2 = 47.5KW
15
Phase Deviation (%)
Phase (deg)
180
Phase Shift vs Temperature
225
16
www.semtech.com
SC2441A
POWER MANAGEMENT
Operation
Overview
The SC2441A is a constant-frequency switching regulator
capable of operating from 1.8V to 20V input. It consists of
two current-mode step-down switch-mode PWM controllers
driving all N-channel MOSFETs and an auxiliary step-up
current-mode converter with an integrated 0.6A power
switch. A local supply (>5V) can be generated from a low
voltage input (3.3V, 2.5V or 1.8V) to provide sufficient gate
drives for the step-down converters.
The two step-down channels of the SC2441A operate at
180 degrees out of phase from each other. Input currents
are interleaved in a two-phase converter so input ripple
current is lower and lower input capacitance can be used
for filtering.
The step-down controllers of the SC2441A operate in
synchronous continuous-conduction mode. They can
function either as two independent step-down controllers
producing two separate outputs or as a dual-phase singleoutput controller by tying the FB2 pin to VIN (Figure 2). In
single output mode, the channel 1 error amplifier controls
both channels and the channel 2 error amplifier is
disabled. Soft-start and overload hiccup of both channels
are also controlled by channel 1. In Figure 2 the output
SEL of the comparator A1 determines which error amplifier
outputs and fault signals are routed to channel 2. The
minimum required FB2 voltage for single output mode is
1.55V.
Phase-Locked Loop and Synchronization
The SC2441A utilizes a phase-locked oscillator (Figure 5)
for clock generation and external synchronization. The
advantages of using a phase-locked loop (PLL) are: (i) when
the step-down channels are synchronized, the auxiliary stepup regulator in the SC2441A can be made to run at twice
the external clock frequency to reduce component size and
(ii) two or more SC2441A can be daisy chained using the
clock output (pin 28) and interleaved with programmable
phase shift. Each step-down controller within a SC2441A
operates at 180 degrees out of phase from the other stepdown controller. The switching frequency of the step-down
controllers can be set with an external resistor ROSC. The
boost regulator and the step-down controllers are capable
of operating up to 2 MHz and 1 MHz respectively. It is
2006 Semtech Corp.
necessary to consider the operating duty-ratio range
before deciding the switching frequency. See Applications
Information section for more details.
Consider the detailed block diagram of the PLL in Figure
5. The phase/frequency detector compares the buffered
external clock XCLK with the Q T output of the toggle flipflop. If the rising edge of XCLK leads that of Q T , then QU
will go high between the two corresponding rising edges.
Switch S1 is closed, charge is delivered to the loop filter
and the voltage at the PLLF pin increases. This in turn
causes the current output of the voltage to current converter
(V/I) and the switching frequency of the current-controlled
oscillator (CCO) to increase. If Q T rises before XCLK, then
QD will go high from the rising edge of Q T to the rising
edge of XCLK. Switch S2 is closed, charge is drawn from
the loop filter and the PLLF voltage falls. The switching
frequency of the current-controlled oscillator (CCO)
decreases. When the PLL is in lock, the rising edges of
XCLK and Q T are aligned. QU and QD will go high for only a
few gate delays. The PLLF stabilizes to a constant DC
voltage and the CCO runs at the same frequency as the
external clock.
In the absence of an external clock, S2 is closed and the
PLL loop filter is continuously discharged. Not shown in
Figure 5 is an internal PLLF lower clamp circuit that limits
the minimum voltage at the PLLF pin to 0.17V. This sets
the lowest operating frequency and thus the lower bound
of the PLL lock-range. The V/I in Figure 5 is shown with
two non-inverting inputs. The lower voltage non-inverting
input takes control of the V/I. If the PLLF pin is tied to VIN
(>1.8V) through a current-limiting resistor, then the 0.4V
input of the V/I will predominate. The 0.4V input therefore
sets the upper excursion limit of the V/I and the maximum
operating frequency of the PLL at a given ROSC. The
maximum PLL frequency to the minimum locking frequency
ratio is about 2. When the SC2441A is not synchronized
externally, the PLLF pin should be tied high through a
resistor. The CCO will then run at its maximum frequency.
When two SC2441As are used in a master-slave
configuration, the PLLF pin of the master SC2441A is tied
high and its free running frequency is set with the resistor
ROSC. CKOUT of the master is then tied to the SYNC/ SHDN
input of the slave SC2441A. The free running and the
17
www.semtech.com
SC2441A
POWER MANAGEMENT
Operation (Cont.)
minimum locking frequencies of the slave should be
selected to accommodate the variation in the master’s
frequency. Phase shift between the master and the slave
can be programmed with an optional resistor (Figure 5).
More detailed discussion can be found in the Application
Information.
Pulling the SYNC/ SHDN pin below 0.5V shuts off the
SC2441A after 85µs time delay.
Control Loop
The step-down controllers and the boost regulator in the
SC2441A use peak current-mode control for fast transient
response and current sharing in single output operation.
Current-mode switching regulators utilize a dual-loop
feedback control system. The error amplifier output controls
the peak inductor current of that channel. This is the inner
current loop. The double reactive poles of the output LC
filter are reduced to a single real pole by the inner current
loop, easing loop compensation. Fast transient response
can be obtained with a simple Type-2 compensation
network. In the outer loop, the error amplifier regulates
the output voltage.
Referring to the block diagrams in Figures 2 and 3, the
sensed inductor current is summed with the slopecompensating ramp before compared to the output of the
error amplifier. The PWM comparator trip point determines
the switch turn-on pulse width. The current-limit comparator
ILIM turns off the power switch when the sensed current
exceeds the corresponding current-limit threshold. ILIM
therefore provides cycle-by-cycle current limit. All three
converters in the SC2441A have internal rampcompensation to prevent sub-harmonic oscillation when
operating above 50% duty cycle. The internal compensating
ramp is designed for an inductor ripple-current between
1
and
of the maximum inductor current and the peak4
to-peak current-sense voltage (CSP-CSN of the step-down
controllers) between
and
of the current-limit
threshold (25mV). The current-limits of all three
converters are unaffected by the compensation ramps.
2006 Semtech Corp.
Current-Sensing
The inductor current needs to be sensed for use as PWM
modulating ramp. Either sense resistor or inductor series
resistance (DCR) can be used as the sensing element for
the step-down controllers. Since the maximum currentsense voltage (CSP-CSN) is only 25mV, a precision sense
resistor in series with the inductor can be used at the output
without resulting in excessive power dissipation.
Alternatively the DCR of the inductor can also be used.
Both methods are less sensitive to supply and ground
transients than high-side or low-side sensing because the
sensed voltage is developed at the output of the stepdown converter. DCR sensing will be described in more
details in the Applications Information section.
Boost switch current is sensed with an integrated sense
resistor with a minimum current-limit of 0.6A.
Error Amplifiers
All error amplifiers in the SC2441A are of transconductance
type. Converters are compensated with series RC network
from the COMP pins to the ground. An additional small
parallel capacitor may be required for stability.
In Figure 2 the error amplifiers EA1 and EA2 are shown
with two non-inverting inputs. The non-inverting input with
lower voltage predominates. One positive input is biased
to a 0.5V precision reference. The other non-inverting input
of the error amplifier is tied to a voltage equal to
(VSS/EN - 1.25V)/3.
During converter start up, the effective positive input of
the error amplifier stays at 0 until the soft-start capacitor
at the SS/EN pin is charged above 1.25V. The
corresponding COMP pin is also pulled low by the
comparator A2 or A3. After the SS/EN voltage exceeds
1.25V, the COMP pin is released. Both the upper and the
lower gate drives remain low until the COMP voltage
exceeds 1.85V. If the soft-start capacitor charging time
is sufficiently long, then both the FB and the output
voltage will track the divided SS/EN voltage on their way
to regulation. If the starting output voltage is non-zero,
then the COMP voltage and the corresponding gate drives
will remain low until the divided SS/EN voltage exceeds
the feedback voltage. Starting into a pre-existing output
is seamless.
18
www.semtech.com
SC2441A
POWER MANAGEMENT
Operation (Cont.)
In closed loop operation, EA1 and EA2 output voltage
vary from 1.2V to 3.5V with the range 1.2V to 1.85V
corresponding to negative peak sense voltages. Both gate
drives are kept off until the COMP voltage exceeds 1.85V
in start up.
during start up. As mentioned above, there is no PWM
(=TGON) pulse until C SS is above 1.25V and the
corresponding COMP rises above 1.85V. Once the first
TGON pulse appears, L2 is reset and both gate drivers of
that channel are enabled.
The error amplifier of the step-up converter has a 1.25V
reference voltage. Its output voltage excursion is from 0.8V
to 1V in closed-loop operation.
After C SS is charged above 3.3V, C 1 output goes low.
Hiccup is armed. If the output voltage is less than 70%
of the set value due to improper start up or output
overload, then C3 will set the overload latch L1. Both gate
drivers of the channel are turned off and the 10µA
current source discharges CSS. RSS must be large enough
to ensure full discharge of CSS down to 0.5V. Soft-start
process should be slow enough to allow the output to
reach 70% of its final value before hiccup is armed. The
overload latch L 1 is reset when the C SS capacitor is
discharged below 0.5V. The 10µA current source turns
off. CSS capacitor is recharged by RSS and the converter
undergoes soft-start. If overload persists, the step-down
converters will undergo repetitive shutdown and restart
(hiccup).
Current-Limit
The 25mV maximum current sense voltage is the cycle-bycycle peak current limit of the step-down controller.
Gate Drivers
The SC2441A uses an adaptive non-overlapping control
scheme to switch the upper and the synchronous
MOSFETs. The synchronous MOSFET of each step-down
channel is turned off at the falling-edge of the phase
clock. The control (upper) MOSFET is not turned on until
the synchronous gate drive goes low. The phase inductor
current ramps up. When the sensed inductor current
reaches the threshold determined by the error amplifier
output and ramp compensation, the control MOSFET is
turned off. The synchronous MOSFET is not turned on
until the upper gate drive goes low.
The supply voltage for the upper gate driver is obtained
from a diode-capacitor bootstrap circuit. If the bootstrap
capacitor is charged from VCC, then the high-side gate drive
voltage will swing from approximately 2VCC to ground. The
synchronous gate drive swings from VCC to ground.
Soft-Start and Overload Protection
If the output is short-circuited, the inductor current will
not increase indefinitely between the times the inductor
current reaching its current limit and shutdown. This is
due to cycle skipping reduces the actual operating
frequency.
Pulling the SS/EN pin below 0.8V with an open-collector
transistor sets the disable latch L2 and turns off the gate
drives. The SS/EN pin can be used as the enable input for
the controller.
The soft start timing diagram and the hiccup operation
timing diagram are shown in Figures 6a and 6b
respectively.
Figure 4 shows the functional diagram of the soft-start
and overload protection circuit. The soft-start capacitor
CSS and its charging resistor RSS are tied to the SS/EN pin.
Together they set the soft-start time. Before VCC rises to
4.5V, the undervoltage lockout circuit discharges CSS to
ground. After VCC rises above 4.5V, Q1 turns off and CSS is
slowly charged by RSS. Comparator C2 and latch L2 first
disable both the upper and lower gate drives. Hysteretic
comparator C1 resets the latch L1 so that hiccup is disabled
2006 Semtech Corp.
19
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
Operating Frequency (fs)
The switching frequency in the SC2441A is userprogrammable. The advantages of constant frequency
operation are simple passive component selection and
fast transient response with simple frequency
compensation. Before setting the operating frequency,
the following trade-offs should be considered.
ROSC vs. Step-down
Channel
Switching
Frequency
Rosc vs Single Channel
Switching
Frequency
150
130
ROSC (KW )
110
1) passive component sizes
2) converter efficiency
3) EMI
4) Minimum switch on time and
5) Maximum duty ratio
90
70
50
30
10
100
300
500
700
900
1100
Switching Frequency (KHz)
For a given output power, the sizes of the passive
components are inversely proportional to the switching
frequency, whereas MOSFET’s/Diodes switching losses
are proportional to the operating frequency. Other issues
such as heat dissipation, packaging and the cost issues
should be considered. The frequency bands for signal
transmission should be avoided because of EM
interference.
The switching frequency of both step-down controllers is
set with an external resistor from Pin 10 to the signal
ground. The set frequency is inversely proportional to the
resistor value (Figure 7) and can be approximated as:
ROSC = 101618 × FSW
-1.22
ROSC is in KΩ and FSW is in KHz.
The internal oscillator starts to operate once VIN exceeds
its UVLO threshold. The oscillator output, CLK, (see Figure
2) clocks the step-up converter. The frequency divider
generates two out-of-phase clocks, CLK1 and CLK2, at
a half of CLK frequency. CLK1 and CLK2 clock the stepdown channels. The switching frequency of the step-up
converter is twice those of the step-down controllers. If
both step-down channels are running at 250KHz, then
the boost section will be running at 500KHz.
2006 Semtech Corp.
Figure 7. ROSC vs. Step-down Channel Free-running
Frequency
Minimum Switch On Time Limitation
In both step-down controllers, the falling edge of the
clock turns on the top MOSFET. The inductor current
ramps up so does the sensed voltage. After the sensed
voltage crosses a threshold determined by the error
amplifier output, the top MOSFET is turned off. The
propagation delay time from the turn-on of the controlling
FET to its turn-off is the minimum switch on time. The
SC2441A has a minimum on time of about 180ns at
room temperature. This is the shortest on interval of the
controlling FET. The controller either does not turn on
the top MOSFET at all or turns it on for at least 180ns.
For a synchronous step-down converter, the operating
duty cycle is VO /VIN. So the required on time for the top
MOSFET is VO/(VINfS). If the frequency is set such that the
required pulse width is less than 180ns, then the
converter will start skipping cycles. Due to minimum on
time limitation, simultaneously operating at very high
20
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
switching frequency and very short duty cycle is not
practical. If the input voltage is 3.3V and the operating
frequency is 1MHz, the lowest output voltage will be 0.6V.
There will not be enough modulation headroom if the on
time is simply made equal to the minimum on time of the
SC2441A. For ease of control, we recommend that the
required pulse width be at least 1.5 times the minimum
on time.
C2
GND
9
VIN
SC2441A
VCC
PGND1
1
R2
21
R6
24
Maximum Duty-cycle Consideration
C8
The top MOSFET turns off for at least 200ns every cycle
regardless of the switching frequency. This places an
upper bound on the voltage conversion ratio at a given
switching frequency.
If the desired output voltage requires high operating dutycycle, then operating frequency will have to be lowered
to allow modulating headroom.
RC Filtering network for VCC and VIN pins
A RC filtering network is recommended for the SC2441A
VCC and VIN pin connections. As shown in Figure 1, R6 plus
C8 and R2 plus C2 are the filtering networks for VCC pin
and VIN pin respectively. The value of the R6 and R2 ranges
from 3.3Ω to 5.11Ω. C8 and C2 should be larger than
1µF.
C8 and C2 are the decoupling capacitors for the VCC pin
and VIN pin. They should be placed as close as possible
to the pins of the SC2441A to achieve the best
decoupling performance. Due to the different
functionalities of the VCC pin and VIN pin, C2 should be
placed between the VIN pin and the signal ground of the
SC2441A. And C8 should be placed between the VCC pin
and the power ground of the SC2441A. The
recommended connections for the VCC pin and VIN pin are
illustrated in Figure 8.
2006 Semtech Corp.
Figure 8. RC Network Connections for VIN and VCC pins
Step-Up Converter
The SC2441A features a step-up regulator and two stepdown controllers.
The boost section of the SC2441A comprises of pins 7,
8, 26 and 27. Pin 26 is the independent power ground
for the boost converter section, which should be
separated from the step-down section power ground pin
24 in layout to minimize the noise influence. The boost
section in SC2441A has an internal reference set at
1.25V. The output of the boost section can be
programmed with external resistors R1 and R4 as shown
in Figure 1.
VBOOST = 1.25V ´
R1 + R 4
R4
SC2441A utilizes a transconductance error amplifier for
the step-up controller and it can be compensated with
C3, R5 and C5 as shown in Figure 1. The step-up controller
in the SC2441A employs cycle-by-cycle peak current limit
to protect the internal switching transistor. Current limit
threshold is typically 0.8A.
In the applications where only low input voltage is
available, the step-up converter in the SC2441A is very
useful for generating an auxiliary output to power the
gate drive of the step-down controllers.
21
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
Assuming that the efficiency of the boost converter is η
and the boost converter is running in CCM with duty ratio
D. The peak inductor current is
VIN
IL1PEAK =
L1
SW3
27
Small
Loop
SC2441A
24
D1
Vo3 × Io3 Vin
1
+
×D × T ×
Vin × h
L1
2
The saturation current rating of the selected inductor
should be at least 1.2 times of the calculated peak
current value.
Step-up Converter Capacitor Selection
PGND1
PGND2
26
C1
VCC
21
C2
R1
Figure 9. Step-Up Section Layout Illustration
As shown in Figure 9, to minimize the switching noise
generated by the step-up converter, the loop formed by
D1, C1, SW3 and PGND2 should be as small as possible.
And the PGND2 pin should be tied to PGND1 at one
spot close to the PGND1 pin.
Step-up Converter Inductor Selection
For a specified inductor current ripple ratio δ3 (peak-topeak current ripple v.s. actual input current IIN), the
inductor value is
L1 =
Vin
V V
(1 - in ) in .
fs3 d3Io3
Vo3 Vo3
Input capacitor:: The input capacitance should be large
such that the input transients due to both the step-up
and the step-down converters do not trip the UVLO
threshold 1.71V. Since the SC2441A controls a 2-phase
low input voltage step-down converter, the input
capacitance is sized to handle the input ripple current of
the buck converter. This is usually sufficient for the
auxiliary boost converter because the input current in a
boost converter is continuous.
Output capacitor: Unlike buck converter, pulse current
is delivered to the output of a boost converter. To reduce
the output ripple voltage, low ESR capacitors should be
used. The output capacitor should also be able handle
the output ripple current. The SC2441A is designed to
use multi-layer ceramic capacitor as the sole output
capacitor.
Maximum Output Current of the Step-up Converter
Figure 3 shows that the boost switch current is sensed
with an internal sense resistor Rs and it is internally
limited at 0.6A. So the maximum output current can be
given as (η is the efficiency of the step-up section):
Io3,max = (0.6A -
Typically, select δ3 <2 for a Continous Conduction Mode
(CCM) operation.
d3
2
)×
Vin × h
Vo3
If Vin = 3.3V, Vo3 = 5V and Io3 = 100mA with δ3 = 1.6 and
fs3 = 1MHz, then, L1 = 4.7µH.
2006 Semtech Corp.
22
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
Loop Compensation for the Step-Up Converter
Soft-Starting the Step-Down Controllers
A simple small signal model for current-mode boost
converter in continuous-conduction mode is shown in
Figure 10.
The soft-start of the two step-down converters are
independently controlled through SS1 pin and SS2 pin.
As lillustrated in Figure 4, if VCC is below 4.5V, Q1 will be
on, keeping CSS discharged. When FAULT goes low, Q1 is
turned off, CSS gets charged via RSS from VCC. Values of
RSS and CSS set different start-up times.
a
b
As shown in Figure 4, if the output falls below 70% of its
setpoint, the Css will be discharged with a 10µA current
sink. RSS must be large enough to allow the soft-start
capacitor to be discharged below 0.5V. Soft-start process
should be long enough to allow the output to reach 70%
of its final value before hiccup is armed.
Coincident Soft-Start
The step-down controllers can be made to start
coincidently. The method is shown in Figure 11.
VCC
RSS1
SS1/EN1
Figure 10. Small signal model of Boost converter.
3
D1
CSS1
SC2441A
In Figure 10, Co3 and Resr3 are the capacitance and the
ESR of the output capacitor, gm3 is the error amplifier
transconductance and k3 is the current loop gain. If one
specifies the loop crossover frequency f c , the
compensation component values are readily calculated
as
CSS
VCC
RSS2
R esr 3
R
f
1
,
C 4 = h 3 gm3k 3 (1 - D 3 ) o3 | 1 - c |
2
fz1 2pfc R esr 3 + 0.5R o3
R4 =
SS2/EN2
17
CSS2
1
R
Co3 (R esr 3 + o3 )
C4
2
and
Figure 11. Coincident Soft-Start for Step-Down
Converters
2R esr 3
C5 = C 4
Ro3
(1 - D 3 )2 R o3
f z1 =
.
2 pL 3
h3 =
2006 Semtech Corp.
D2
The capacitance of C , as shown above, should be more
SS
than 3 times of the capacitance of the C and C .
SS1
SS2
Rb
Ra + Rb
23
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
DCR Current Sensing
V
Voltage on C 1 --- VC1(t)
Either precision sense resistor or inductor DCR can be
used as the inductor current sensing element.
VC1.PEAK
R1IL1.PEAK
VIN
R1IO
VC1.VALLEY
SW1
L1
R1
Voltage Drop on R 1--- IL1(t)R1
0
VC1
+ -
R2
SW2
C1
+
ICS+
COUT
R3
SC2441A
ICS-
Figure 12. Current Sensing Circuit.
In Figure 12 SW1 and SW2 represent the MOSFET
switches. CS is the current sense amplifier. ICS+ and ICSare the input bias currents of the CS. L1 is the output
inductor. R1 is the DC resistance of L1. R2, R3 and C 1
constitute the DCR current sensing network.
In Figure 12, R2 and R3 resistive divider attenuates the
sensed signals when I
. The time
constant resulting from L1 and its DCR R1 is:
Define REQU:
The time constant of the DCR sensing network is:
If τC1 = τL1
C1will be:
Assuming that CS input bias currents are zero and that
R3 is not used, if the time constant L1/R1 is made equal
to the time constant R2C1, then the voltage across the
inductor DCR, R1, will be replicated across C1 in the steady
state (see Figure 13). The following equations apply:
IL1 .PEAK = IO + D IL 1 /2
IL1 . VALLEY = IO - D IL 1 /2
VC1 (t) = IL1 (t) × R 1
where, IO is the output current and DIL 1 is the peak-topeak L1 current ripple. The inductor current can therefore
be sensed by monitoring C1 voltage. L should be selected
so that the
,
then the peak and valley voltages across
VC1×VALLEY = ICS+ × REQU +
R3 × R1 æ
DI ö
× ç IO - L1 ÷
(R2 + R3 ) è
2 ø
ICS+ therefore introduces an offset error to the sensed
voltage. To reduce this error, REQU must be minimized.
Suppose V IN =5V; V OUT =2.5V; D=50%; I OUT =20A;
FSW=500KHz; L1=0.5µH; R1=2mΩ; ICS+=1µA. The output
current limit is set at 28A. The time constant formed by
L1 and R1 is
tL1 = L1
is between 25% to 33% of the IO.
R1
= 0.25ms =
R ×R
2 3 ×C
1
R +R
2
3
DIL 1 = 5A
However CS input bias currents are not zero. ICS+ and ICSare typically 0.4µA and 40µA respectively (see electrical
characteristics) and can not be ignored.
2006 Semtech Corp.
t
Figure 13. Voltage Waveform C1 and R1
RLOAD
CS
-
R1IL1.VALLEY
VC1×PEAK = ICS+ × REQU +
24
R3 × R1 æ
DI ö
× ç 28A + L1 ÷ = 25mV
(R2 + R3 ) è
2 ø
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
R ×R
2 3 × C = 0.25ms
1
R +R
2
3
1µ A ×
R3 × R2
R 3 × R1 æ
5A ö
+
× ç 28A +
÷ = 25mV
2 ø
(R 2 + R 3 ) (R 2 + R 3 ) è
With an arbitrary selection of
R ×R
2 3 = 3.01KW , we can
R +R
2
3
get C1=83nF. Since 83nF is not a standard capacitance
value, we use 100nF capacitor for C1. Consequently,
R ×R
2 3 = 2.5KW
. And we can also derive:
R +R
2
3
1µA × 2.5KW +
R2 = 6.80K W
R3 = 3.92KW
Pre-biased Start Up
Sometimes the step-down converter is to start into a
pre-biased output load. The pre-biased voltage is normally
lower than the output setpoint of the step-down
converter.
As described earlier, pre-bias startup process with the
SC2441A is seamless. The testing setup of the pre-biased
start-up is shown as in Figure 14.
Module
under
Test
D1
Blocking Diode
RLOAD
-
External
Voltage
Source
Free-running Operation
The internal oscillator of the SC2441A can either freerun or it can be phase-locked to an external clock.
In free-running mode, the internal phase-locked loop is
disabled by tying an external resistor from the PLLF pin
to V IN. The external resistor ROSC (see figure 5(a))
programs the channel frequency. The PLLF pull-up resistor
should be carefully selected so that the voltage at the
PLLF pin is above 1V. A value between 20KΩ to 50KΩ is
recommended.
R1
5A ö
æ
× 2.5KWç 28A +
÷ = 25mV
R2
2 ø
è
+ VO
In Figure 14, VS is the external power supply pre-biasing
VO. D1 blocks the output of the power module under test
from VS during soft-start. RLOAD is the resistive load of the
module under test. Before power-up the module, monitor
VO to ensure that it is the desired pre-biased output
voltage. Then power-up the module. V O should rise
smoothly.
Vs
Pull-up resistor can also be tied to VCC if VCC is present
before the SC2441A starts to switch. The advantage tying
the pull-up resistor to VCC is because that the VCC is a
regulated output from either a boost converter or a sepic
converter. The resistor from the PLLF pin can be tied to
VCC if VCC is from a boost converter output. The reason is
that the VCC will be powered up from the input VIN before
output of the boost converter reaches the setpoint.
However, in some applications, a SEPIC converter is
employed to get stable VCC due to the wide input voltage
range. In this case, the resistor from the PLLF pin should
not be connected to the VCC due to the presence of a DC
blocking capacitor in the converter. The SC2441A will not
switch if the PLLF pin is at zero volt.
Applying more than 2.1V at the PLLF pin activates the
diode clamp circuit (see Figure 5(a)). The filtering
components (R1,R 2, C1 and C2 in Figure 5(a)) are not
needed while free-running. The clamp activation will have
no effect on the PLL if VPLLF >1V.
The internal clock is brought out to the CKOUT pin. The
signal at CKOUT pin can be used as the synchronizing
clock for other SC2441As in a master-slave configuration.
Figure 14. Test Setup for Pre-biased Start Up
2006 Semtech Corp.
25
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
Master - Slave Mode Configuration
The configuration for SC2441A master-slave mode
operation is shown in Figure 15. The master is made
free running, the master clock frequency should be within
the synchronizing range of the slave.
In the Master-Slave mode, the SS2441A can be
synchronized to an external clock signal applied to the
SYNC pin. External filtering componets (R1, R2, C1 and C2)
on the PLLF pin are necessary for the slave SC2441A .
The PLLF pull-up resistor is not necessary for the slave
converter.
Phase shift between the master and the slave is the
phase lag measured between the sync input and the clock
output of the slave. Typical relationship between the phase
shift and the slave value of the resistor R2 is shown in
the “Typical Characteristics”.
For the SC2441A running at slave mode, its free-runing
frequency (internal switching frequency) set with ROSC
should be programmed 20% higher than the external
synchronization frequency.
VIN
As shown in Figure 15, the CKOUT signal of the master
SC2441A is the input sync signal for the slave SC2441A.
The R1, C1 and C2 constitute the filtering circuit stabilizing
the phase lock loop in the slave SC2441A. R2 (between
30kΩ and 150kΩ) determines the phase shift between
the slave CKOUT and its SYNC input.
PLL Frequency Compensation
Applying synchronizing clock with step change in frequency
adjust compensation components until overshoot and
ringing at PLLF pin is minimized.
Output Inductor and Ripple Current in Step-down
Sections
Both step-down controllers in the SC2441A operate in
synchronous continuous-conduction mode (CCM)
regardless of the output load. The output inductor
selection/design is based on the output DC and transient
requirements. Both output current and voltage ripples
are reduced with larger inductors but it takes longer to
change the inductor current during load transients.
Conversely smaller inductors results in lower DC copper
losses but the AC core losses (flux swing) and the winding
AC resistance losses are higher. A compromise is to
choose the inductance such that the peak to peak
inductor ripple current is 20% to 30% of the rated output
current.
Assume that the inductor current ripple (peak-to-peak)
is δ∗Ιο Then the inductance will be
SYNC
R4
PLLF
R3
Master
SC2441A
L=
Vo (1 - D)
.
dIo fs
The peak current in the inductor becomes (1+δ/2)*Io
and the RMS current is
CKOUT
IL,rms = Io 1 +
d2
.
12
SYNC
PLLF
Slave
SC2441A
CKOUT
R1
C2
R2
C1
Figure 15. Master-Slave Synchronization
2006 Semtech Corp.
The followings are to be considered when choosing
inductors.
a) Inductor core material: For high efficiency applications
above 350KHz, ferrite, Kool-Mu and polypermalloy
materials should be used. Low-cost powdered iron cores
can be used for cost sensitive-applications below 350KHz
but with attendant higher core losses.
26
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The
designer can choose the adjacent (larger) standard
inductance value. The inductance varies with
temperature and DC current. It is a good engineering
practice to re-evaluate the resultant current ripple at
the rated DC output current.
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
Output Capacitor (Co) and V out Ripple in Step-down
Sections
The output capacitor provides output current filtering in
steady state and serves as a reservoir during load
transient. The output capacitor can be modeled as an
ideal capacitor in series with its parasitic ESR (Resr) and
ESL (Lesl) (Figure 16).
Since the inductor current is a triangular waveform with
peak-to-peak value δ * Io, the ripple-voltage caused by
inductor current ripples is
Dv C »
dIo
.
8Co fs
The ripple-voltage due to ESL is
Dv ESL = L esl fs
dIo
D
and the ESR ripple-voltage is
Dv ESR = R esr dIo .
Aluminum capacitors (e.g. electrolytic, solid OS-CON,
POSCAP, tantalum) have high capacitances and low
ESL’s. The ESR has the dominant effect on the output
ripple voltage. It is therefore very important to minimize
the ESR.
Co
ib(t)
Lesl
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To keep the steady state output ripple-voltage
< ∆Vo, the ESR should satisfy
R esr1 <
DVo
.
dIo
Resr
Figure 16. Co equivalent circuit
If the current through the branch is ib(t), the voltage
across the terminals will then be
To limit the dynamic output voltage overshoot/
undershoot within α (say 3%) of the steady state output
voltage) under 0 to full load current swing, the ESR value
should be
R esr 2 <
t
v o ( t ) = Vo +
di ( t )
1
ib ( t )dt + L esl b + R esr ib ( t ).
dt
Co 0
ò
The required ESR value of the output capacitors should
be
This basic equation illustrates the effects of ESR, ESL
and Co on the output voltage.
The first term is the DC voltage across Co at time t=0.
The second term is the ripple-voltage caused by the
inductor ripple-current. The third term is the voltage ripple
due to ESL and the fourth term is the voltage ripple due
to ESR. The total output voltage ripple is then a vector
sum of the last three terms.
2006 Semtech Corp.
a Vo
.
Io
Resr = min{Resr1,Resr2 }.
In the aluminum capacitor selection, the working voltage
rating is normally suggested to be greater than 1.5Vo.
The allowable current ripple (RMS) should be greater than
27
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
2
dIo
2 3
.
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement.
The voltage ripple cause by the capacitor charge/
discharge should be an order of magnitude smaller than
the voltage ripple caused by the ESR. To guarantee this,
the capacitance should satisfy
Co >
R eq (w ) :=
Remark 1: High frequency ceramic capacitors may not
carry most of the ripple current. It also depends on the
capacitor value. Only when the capacitor value is set
properly, the effect of ceramic capacitor low ESR starts
to be significant.
For example, if a 10µF, 4mΩ ceramic capacitor is
connected in parallel with 2x1500µF, 90mΩ electrolytic
capacitors, the ripple current in the ceramic capacitor is
only about 42% of the current in the electrolytic
capacitors at the ripple frequency. If a 100µF, 2mΩ
ceramic capacitor is used, the ripple current in the
ceramic capacitor will be about 4.2 times of that in the
electrolytic capacitors. When two 100µF, 2mΩ ceramic
capacitors are used, the current ratio increases to 8.3.
In this case most of the ripple current flows in the
ceramic decoupling capacitor. The ESR of the ceramic
capacitors will then determine the output ripple-voltage.
2
2
2
2
(R1a + R1b )2 w 2 C1a C1b + (C1a + C1b )2
where R 1a and C 1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors respectively
(Figure 17).
10
.
2pfsR esr
In many application circuits, several low ESR ceramic
capacitors are added in parallel with the aluminum
capacitors to further reduce ESR and improve high
frequency decoupling. Since the capacitances and the
ESR’s of ceramic and aluminum capacitors are different,
the following remarks are made to clarify some practical
issues.
2
R1aR1b (R1a + R1b )w 2C1a C1b + (R1b C1b + R1a C1a )
C1a
R1a
C1b
Ceq
R1b
Req
Figure 17. Equivalent RC branch.
Req and Ceq are both functions of frequency. For rigorous
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b
= R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and
Req = 1/2 R1 and Ceq = 2C1.
Input Capacitor (Cin) in Step-down Sections
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 18.
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESR’s either. Instead
they should be calculated using the following formulae.
2
C eq (w ) :=
Figure 18. Buck converter input model
2
(R1a + R1b )2 w 2C1a C1b + (C1a + C1b )2
2
2
(R1a C1a + R1b C1b )w 2 C1a C1b + (C1a + C1b )
2006 Semtech Corp.
As shown in Fig. 18, the internal DC input voltage source
28
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
impedance is Rin and the input capacitor Cin has an ESR
denoted as Resr. MOSFET and input capacitor current
waveforms, ESR voltage ripple and input voltage ripple
are shown in Figure 19.
d
Dv ESR = R esr (1 + )Io .
2
The peak-to-peak input voltage ripple due to the capacitor
is
Dv C »
DIo
.
Cin fs
From these two expressions, Cin can be found to meet
the input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce
ripple. The two step-down channels of the SC2441A
operate at 180 degrees from each other. If both stepdown channels in the SC2441A are connected in parallel,
both the input and the output RMS currents will be
reduced.
Figure 19. Typical waveforms at the input of a
buck converter.
It can be seen that the current in the input capacitor
pulses with high di/dt. Capacitors with low ESL should be
used. It is also important to place the input capacitor
close to the MOSFET’s on the PC board to reduce trace
inductances around the pulse current loop.
The RMS value of the capacitor current is approximately
ICin = Io D[(1 +
d2
D
D
)(1 - )2 + 2 (1 - D) ].
12
h
h
The power losses at the input capacitors is then
PCin = ICin2Resr.
For reliable operation, the maximum power dissipation
in the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS) rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be high
enough to handle the ripple current. For higher power
applications, multiple capacitors are placed in parallel to
increase the ripple current handling capability.
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input voltage
ripple due to the ESR is
2006 Semtech Corp.
Ripple cancellation effect of interleaving allows the use
of smaller input capacitors. When converter outputs are
connected in parallel and interleaved, smaller inductors
and capacitors can be used for each channel. The total
output ripple-voltage remains unchanged. Smaller
inductors speeds up output load transient.
When two channels with a common input are interleaved,
the total DC input current is simply the sum of the
individual DC input currents. The combined input current
waveform depends on duty ratio and the output current
waveform. Assuming that the output current ripple is
small, the following formula can be used to estimate the
RMS value of the ripple current in the input capacitor.
Let the duty ratios and output currents of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2 respectively.
If D1<0.5 and D2<0.5, then
2
2
ICin » D1Io1 + D 2Io2 .
If D1>0.5 and (D1-0.5) < D2<0.5, then
2
2
ICin » 0.5Io1 + (D1 - 0.5)(Io1 + Io 2 )2 + (D 2 - D1 + 0.5)Io 2 .
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
2
2
ICin » 0.5Io1 + D 2 (Io1 + Io 2 )2 + (D1 - D 2 - 0.5 )Io 2 .
29
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
If D1>0.5 and D2 > 0.5, then
2
2
ICin » (D1 + D 2 - 1)(Io1 + Io 2 )2 + (1 - D 2 )Io1 + (1 - D1 )Io2 .
Power MOSFET Selection and Gate Drive
Main considerations in selecting the MOSFET’s are power
dissipation, cost and packaging. Switching losses and
conduction losses of the MOSFET’s are directly related
to the total gate charge (Cg) and channel on-resistance
(Rds(on)). In order to judge the performance of MOSFET’s,
the product of the total gate charge and on-resistance is
used as a figure of merit (FOM). Transistors with the same
FOM follow the same curve in Figure 20.
Gate Charge (nC)
50
40
Cg( 100 , Rds)
Cg( 200 , Rds)
Cg( 500 , Rds)
20
1
0
The losses in power MOSFET’s consist of
a) conduction loss due to the channel resistance Rds(on),
b) switching loss due to the switch rise time tr and fall
time tf and
c) the gate loss due to the gate resistance RG.
Top Switch:
The RMS value of the top switch current is
IQ1,rms = Io D(1 +
d2
12
).
Its conduction loss is then
Ptc = IQ1,rms2 Rds(on).
Rds(on) varies with temperature and gate-source voltage.
Curves showing R ds(on) variations can be found in
manufacturers’ data sheet. From the Si7882DP
datasheet, Rds(on) is less than 4.5mOhm when Vgs is greater
than 5V. However Rds(on) increases by nearly 40% as the
junction temperature increases from 25°C to 125°C.
The switching losses can be estimated using the simple
formula
0
5
15
20
1
Rds
On-resistance (mOhm)
10
20
FOM:100*10^{-12}
FOM:200*10^{-12}
FOM:500*10^{-12}
Figure 20. Figure of merit curves.
Pts = 21 ( t r + t f )(1 + 2d )Io Vin f s .
where tr is the rise time and tf is the fall time of the
switching process. To clarify these, we sketch the typical
MOSFET switching characteristics under clamped
inductive mode in Figure 21.
The closer the curve is to the origin, the lower is the FOM.
This means lower switching loss or lower conduction loss
or both. It is difficult to find MOSFET’s with both low Cg
and low Rds(on). Usually a trade-off between Rds(on) and Cg
has to be made.
MOSFET selection also depends on applications. In many
applications, either switching loss or conduction loss
dominates for a particular MOSFET. For synchronous buck
converters with high input to output voltage ratios, the
top MOSFET is hard switched but conducts with very low
duty cycle. The bottom switch conducts at high duty cycle
but switches at near zero voltage. For such applications,
MOSFET’s with low Cg are used for the top switch and
MOSFET’s with low Rds(on) are used for the bottom switch.
2006 Semtech Corp.
Figure 21. MOSFET switching characteristics
30
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
In Figure 21,
IQ 2,rms = Io (1 - D)(1 +
Qgs1 is the gate charge needed to bring the gate-to-source
voltage Vgs to the threshold Vgs_th,
Qgs2 is the additional gate charge required for the switch
current to reach its full-scale value Ids and
.
Qgd is the charge needed to charge gate-to-drain (Miller)
capacitance when Vds is falling.
Switching losses occur during the time interval [t1, t3].
Defining tr = t3-t1. tr can be approximated as
tr =
(Q gs 2 + Q gd )R gt
Vcc - Vgsp
.
where Rgt is the total resistance from the driver supply
rail to the gate of the MOSFET. It includes the gate driver
internal impedance Rgi, external resistance Rge and the
gate resistance Rg within the MOSFET i.e.
Pbc=IQ2,rms2 Rds(on),
where Rds(on) is the channel resistance of bottom MOSFET.
If the input voltage to output voltage ratio is high (e.g.
Vin=12V, Vo=1.5V), the duty ratio D will be small. Since
the bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the
bottom MOSFET. The bottom MOSFET switches on with
only a diode voltage between its drain and source
terminals. The switching loss
Pbs = 21 ( t r + t f )(1 + 2d )Io Vd fs
Vgsp is the Miller plateau voltage shown in Figure 21.
Similarly an approximate expression for tf is
tf =
Vgsp
Rg
R gt
is negligible due to near zero-voltage switching.
The gate loss is estimated as
Pbg =
.
Only a portion of the total losses Pg = QgVccfs is dissipated
in the MOSFET package. Here Qg is the total gate charge
specified in the datasheet. The power dissipated within
the MOSFET package is
Ptg =
).
The conduction loss is then
Rgt = Rgi+Rge+Rg.
(Qgs2 + Qgd )Rgt
d2
12
Q g Vcc fs .
The total power loss of the top switch is then
Pt = Ptc+Pts+Ptg.
If the input supply of the power converter varies over a
wide range, then it will be necessary to weigh the relative
importance of conduction and switching losses. This is
because conduction loss is inversely proportional to the
input voltage. Switching loss however increases with the
input voltage. The total power loss of MOSFET should be
calculated and compared for high-line and low-line cases.
The worst case is then used for thermal design.
Bottom Switch:
The RMS current in bottom switch can be calculated
Rg
R gt
Q g Vcc fs .
The total bottom switch loss is then
Pb=Pbc+Pbs+Pbg.
Once the power losses Ploss for the top (Pt) and bottom
(Pb) MOSFET’s are known, thermal and package design
at component and system level should be done to verify
that the maximum die junction temperature (Tj,max, usually
125oC) is not exceeded under the worst-case conditions.
The equivalent thermal impedance from junction to
ambient (θja) should satisfy
q ja £
Tj,max - Ta,max
Ploss
.
θja depends on the die to substrate bonding, packaging
material, the thermal contact surface, thermal compound
property, the available effective heat sink area and the
air flow condition (free or forced convection). Actual
temperature measurement of the prototype should be
carried out to verify the thermal design.
Integrated Power MOSFET Drivers
There are four internal MOSFET drivers in a dualchannel step-down converter.
2006 Semtech Corp.
31
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
Using low gate charge MOSFETs reduces switching loss.
It is possible to trade driver IC losses for MOSFET
switching losses by adjusting the gate resistance. Lower
gate resistance results in higher gate driving current and
faster MOSFET switching. However the driver incurs
higher losses. Conversely higher gate drive resistance
limits the gate drive current, thus lowering the driver
dissipation. MOSFET switching loss is higher.
To prevent shoot-through between the top and the
bottom MOSFETs during commutation, one MOSFET
should be completely turned off before the other is turned
on. The SC2441A uses adaptive non-overlapping timing
to prevent shoot-through.
Once either R o1 or R o2 is chosen, the other can be
calculated for the desired output voltage Vo. Since the
number of standard resistance values is limited, the
calculated resistance may not be available as a standard
value resistor. As a result, there will be a set error in the
converter output voltage. This non-random error is
The following table lists a few standard resistor
combinations for realizing some commonly used output
voltages.
Vo (V)
0.6
0.9
1.2
1.5
1.8
2.5
3.3
(1- h)/h
0.2
0.8
1.4
2
2.6
4
5.6
Ro1 (Ohm) 200
806
1.4K
2K
2.61K 4.02K 5.62K
Ro2 (Ohm) 1K
1K
1K
1K
1K
Optimize MOSFET Driving Voltage
The on-state DC resistance of a MOSFET, R DS_ON, is
determined by its gate to source voltage. The higher the
VGS, the lower the RDS_ON will be. Once the gate-source
voltage exceeds a certain level, the RDS_ON becomes
relatively constant. There is no benefit except higher
dissipation if you further increase the MOSFET gate drive
voltage. It is recommended to select gate drive voltage
(VCC pin) of the SC2441A in between 5V to 7V.
Setting the Output Voltage of the Step-down Section
The non-inverting inputs of the error amplifiers are
internally biased to 0.5V voltage reference. A simple
voltage divider (Ro1 at top and Ro2 at bottom) sets the
converter output voltage. Ro2 can be expressed as a
function of the voltage feedback gain h=0.5/Vo and Ro1
Ro2 =
h
R o1.
1- h
caused by the feedback voltage divider ratio. It cannot
be corrected by the feedback loop.
2006 Semtech Corp.
1K
1K
Only the voltages in boldface can be precisely set with
standard 1% resistors.
The input bias current of the error amplifier also causes
an error in the output voltage. The inverting input bias
currents of error amplifiers 1 and 2 are –60nA and
–280nA respectively. Since the non-inverting input is
biased to 0.5V, the percentage error in the second output
/[0.5 ·
voltage will be –100% · (0.28 µ A) · R R
o1 o2
(R +R )]. To keep this error below 0.2%, R
< 4kΩ.
o1 o2
o2
Loop Compensation in Step-down Section
The SC2441A uses current-mode control for both stepdown channels. Current-mode control is a dual-loop
control system in which the inductor peak current is
loosely controlled by the inner current-loop. The higher
gain outer loop regulates the output voltage. Since the
current loop makes the inductor appear as a current
source, the complex high-Q poles of the output LC
networks is split into a dominant pole determined by the
output capacitor and the load resistance and a high
frequency pole. This pole-splitting property of currentmode control greatly simplifies loop compensation.
32
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
The inner current-loop is unstable (sub-harmonic
oscillation) unless the inductor current up-slope is steeper
than the inductor current down-slope. For stable
operation above 50% duty-cycle, a compensation ramp
is added to the sensed-current. In the SC2441A the
compensation ramp is made duty-ratio dependent. The
compensation ramp is approximately
CS+
CS-
x 29
+
-
+
+
Slope Compensation
Voltage
Comp
VSLOPE (D) = 230mV × D × e 0.734×D
D is the duty ratio.
FB
0.5V
The slope compensation voltage vs duty ratio is as shown
in Figure 22.
-
EA
+
+
PWM
VBE+1.13V
+ Compensation
Network
Slope Compensation Voltage (V)
0.5
0.4
Figure 23. Control Flow Chart with Slope
Compensation
0.3
0.2
0.1
0.0
0.0
0.2
0.4
0.6
0.8
1.0
Duty Ratio (D)
k
Figure 22. Slope Compensation Voltage Waveform
Illustrated as the picture above, as the duty ratio
increases, the slope compensation voltage added into
the control loop increases too. And the control loop
including the slope compensation is shown in Figure 23.
The voltage transconductance error amplifier (shown in
Figure 24. A simple model of current-mode buck
converter
Figure 24) has a gm of 315µA/V. C , C and R construct
2 3
2
the compensation network for stable operation with
optimized load transient response.
The feedback gain h and the resistor values are
determined using the equations given in the “Setting the
Output Voltage” section with
h=
2006 Semtech Corp.
0.5
.
Vo
For the rated output current Io, the first-order gain k is
determined as
k=
DIo
.
DVc
k is the product of equivalent current sensing Rs and
current amplifier gain Gca=29. Furthermore the transfer
33
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
function from the voltage error amplifier output vc to
the converter output vo can be derived from Figure 24.
s
1+
Vo (s)
s z1
:= Gvc (s) = kR o
,
s
Vc (s)
1+
sp1
P2 is a pole for suppressing high-frequency switching
noise. So P2 >> Z2. To simplify design, one usually assumes
that C3<<C2, Roesr<<Ro, Sp1=Sz2 and specifies the loop
crossover frequency fc. The loop crossover frequency
determines the converter dynamic response. With these
assumptions, the controller parameters are determined
as follows
where the single dominant-pole is
sp1 =
C2 =
1
(R o + R oesr )Co
and the zero associated with the output capacitor ESR
is
s z1 =
1
R oesr C o
gm h
C(s) =
s(C 2 + C 3 )
R2 =
s
sz2
,
s
1+
sp 2
C3 =
Ro =
1+
h=
and
sp 2 =
1
.
C 2C 3
R2
C 2 + C3
The loop transfer function is then
T(s)=Gvc(s)C(s).
Vo
= 300m W,
Io
0.5
= 0.42
Vo
and
k=
1
R 2C 2
R oesr C o
.
R2
For example, if Vin=3.3V, V o=1.2V, I o=4A, f s=500kHz,
Co=390µF, Roesr=16mΩ, one can calculate that
where
sz2 =
R oCo
C2
and
.
The dominant-pole changes with the converter output
load.
The controller transfer function (from the converter
output vo to the voltage error amplifier output vc) is
gmhkR o
,
2p fc
DIo
= 2.60.
DVc
If the converter crossover frequency is set around 1/10
of the switching frequency, f c=50kHz, the controller
parameters then can be calculated.
C2 =
gmhkR o
» 0.326nF,
2pfc
use C2=0.33nF.
R2 =
R o Co
» 354.5kW,
C2
use R2=357kΩ.
It is further calculated that
C3 =
R oesr Co
» 17.48pF,
R2
use C3=22pF. The Bode plots of the loop transfer function
(magnitude and phase) are shown in Fig. 25.
2006 Semtech Corp.
34
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
PC Board Layout Issues
73.323
100
Circuit board layout is very important for the proper
operation of high frequency switching power converters.
A power ground plane is required to reduce ground
bounces. The followings are suggested for proper layout.
50
(
20× log G vc( f ) C( f )
)
0
Power Stage
- 17.588 50
10
10
100
3
1 .10
4
f
1 .10
5
1 .10
6
1 .10
5
3´10
f
- 90.001
90
2) Minimize the size of pulse current loop. Place the top
MOSFET, the bottom MOSFET and the input capacitors
close to each other with short and wide traces. In addition
to the aluminum energy storage capacitors, add multilayer ceramic (MLC) capacitors from the input to the power
ground to improve high frequency bypass.
92
(
)
arg G vc( f ) × C( f ) ×
1) Separate the power ground from the signal ground. In
SC2441A the power ground PGND1 should be tied to
the source terminal of lower MOSFETs. The signal ground
AGND should be tied to the negative terminal of the
output capacitor (output return terminal).
180
p
94
- 94.713 96
10
10
100
3
1 .10
4
f
1 .10
5
1 .10
6
1 .10
5
3´10
Figure 25. Bode plots of the loop response.
The resulting crossover frequency is about 49.2kHz with
phase margin 90o.
If the circuit noise makes the converter jitter, a larger C3
than the calculated value can be used. Effectively the
converter bandwidth is reduced to reject high frequency
noises. The final circuit should be checked for stability
under load transients at different line voltages. The load
transient also needs to be measured to ensure that the
output voltage is within the specification window.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFETs to
reduce stray inductances. Add a small RC snubber if
necessary to reduce the high frequency ringing at the
phase node. Sometimes slowing down the gate drive
signal also helps in reducing the high frequency ringing at
the phase node.
4) Shorten the gate driver path. Integrity of the gate drive
(voltage level, leading and falling edges) is important for
circuit operation and efficiency. Short and wide gate drive
traces reduce trace inductances. Bond wire inductance
is about 2~3nH. If the length of the PCB trace from the
gate driver to the MOSFET gate is 1 inch, the trace
inductance will be about 25nH. If the gate drive current
is 2A with 10ns rise and falling times, the voltage drops
across the bond wire and the PCB trace will be 0.6V and
5V respectively. This may slow down the switching
transient of the MOSFETs. These inductances may also
ring with the gate capacitance.
5) Put the decoupling capacitor for the gate drive power
supplies (BST and VCC) close to the IC and power ground.
2006 Semtech Corp.
35
www.semtech.com
SC2441A
POWER MANAGEMENT
Applications Information
Control Section
6) The frequency-setting resistor Rosc should be placed
close to Pin 10. Trace length from this resistor to the
analog ground should be minimized.
7) Solder the VCC decoupling capacitor next to the VCC
and power ground PGND pins.
8) Place the current-sensing components away from the
power circuit and close to the corresponding CS+ and
CS- pins. Use X7R type ceramic capacitors for current
sensing due to their thermal stability. The distance
between the two trace should be as close as possible to
minize the noise pick-up.
9) Use an isolated local ground plane for the controller
and tie it to the negative side of output capacitor bank.
10) A large copper area underneath the SC2441A IC is
nessary for heat sinking purpose. And multiple layers of
large copper area connected through vias can be used
for better thermal performance. The size of the vias as
the connection between multiple layers should not be
too large or solder may seep through the big vias to the
the bottom layer during the re-flow process.
2006 Semtech Corp.
36
www.semtech.com
SC2441A
POWER MANAGEMENT
Outline Drawing - TSSOP-28
A
D
e
N
2X E/2
DIM
E1
E
A
A1
A2
b
c
D
E1
E
e
F
H
L
L1
N
01
aaa
bbb
ccc
PIN 1
INDICATOR
ccc C
2X N/2 TIPS
1 2 3
e/2
B
D
aaa C
SEATING
PLANE
A2 A
C
A1
bxN
bbb
C A-B D
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
.047
.006
.000
.041
.031
.012
.007
.008
.003
.378 .382 .386
.169 .173 .177
.252 BSC
.026 BSC
.210 .216 .220
.112 .118 .122
.018 .024 .030
(.039)
28
0°
8°
.004
.004
.008
1.20
0.00
0.15
0.80
1.05
0.19
0.30
0.09
0.20
9.60 9.70 9.80
4.30 4.40 4.50
6.40 BSC
0.65 BSC
5.35 5.50 5.60
2.85 3.00 3.10
0.45 0.60 0.75
(1.0)
28
8°
0°
0.10
0.10
0.20
F
SEE DETAIL
SIDE VIEW
EXPOSED PAD
H
A
H
c
GAGE
PLANE
0.25
BOTTOM VIEW
L
(L1)
DETAIL
01
A
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B-
TO BE DETERMINED AT DATUM PLANE-H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AET.
Land Pattern - TSSOP-28
F
X
DIM
(C)
H
G
Y
P
Z
C
F
G
H
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.224
.161
.126
.026
.016
.061
.283
(5.65)
5.70
4.10
3.20
0.65
0.40
1.55
7.20
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012-8790
Phone: (805)498-2111 FAX (805)498-3804
2006 Semtech Corp.
37
www.semtech.com