SEMTECH SC4608MLTRT

SC4608
Low Input, MHz Operation,
High Efficiency Synchronous Buck
POWER MANAGEMENT
Description
Features
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The SC4608 drives external, N-channel MOSFETs with a ‹
The SC4608 is a voltage mode step down (buck) regulator controller that provides accurate high efficiency power
conversion from an input supply range of 2.7V to 5.5V. A
high level of integration reduces external component
count, and makes it suitable for low voltage applications
where cost, size and efficiency are critical. The SC4608
is capable of producing an output voltage as low as 0.5V.
It’s frequency of operation is programmable to 1MHz.
peak gate current of 1A. A non-overlap protection is provided for the gate drive signals to prevent shoot through
of the MOSFET pair. The SC4608 features lossless current sensing of the voltage drop across the drain to
source resistance of the high side MOSFET during its
conduction period.
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The quiescent supply current in sleep mode is typically
lower than 1µA. A external soft start is provided to prevent output voltage overshoot during start-up.
Asynchronous start up
Programmable switching frequency up to 1MHz
BiCMOS voltage mode PWM controller
2.7V to 5.5V input voltage range
Output voltage as low as 0.5V
+/-1% reference accuracy
Sleep mode (Icc = 1µA max)
Adjustable lossless short circuit current limiting
Combination pulse by pulse & hiccup mode
current limit
High efficiency synchronous switching
1A peak current driver
External soft start
Power good signal
16-pin MLP Lead-free package. This product is fully
WEEE and RoHS compliant
Applications
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The SC4608 is an ideal choice for converting 3.3V, 5V or ‹
other low input supply voltages. It’s available in 16 pin ‹
MLP package.
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Typical Application Circuit
Distributed power architecture
Servers/workstations
Local microprocessor core power supplies
DSP and I/O power supplies
Battery-powered applications
Telecommunications equipment
Data processing applications
Vin=3V – 3.6V
D2
R13
1
R3
SC4608
16
C3
1
1u
2
3
C16
4
5
560pF
C1
C2 2.2n
R2
10k
180p
R1
14.3k
Css
6
7
PVDD
BST
AVDD
DRVH
FSET
PHASE
1
DRVL
EN
PGND
PGOOD
AGND
SS
VSENSE
12
11
10
C14
22u
22u
R6
ISET
COMP
C13
220u
M11
15
13
C10
C17
1u
R5
L1
M2
1
1.8u
Vout= 0.5V / 12A
C6
C5
C4
C9
330u
22u
22u
4.7n
9
8
R7
10k
R8
200
22n
Revision: June 19, 2006
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SC4608
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Analog Supply Voltage (AVDD)
6
V
Power Supply Voltage (PVDD)
AVDD+/- 0.3
V
PGND
±0.3
V
Output Drivers (DRVH, DRVL) Currents
Continuous
P eak
±0.25
A
±1.00
A
-0.3 to AVDD +0.3
V
PVDD +6
V
-0.3 to PVDD +0.3
V
-2 to PVDD +1
V
TSTG
-65 to +150
°C
TJ
+150
°C
Peak IR Reflow Temperature, 10 - 40s
TPKG
260
°C
ESD Rating (Human Body Model)
ESD
2
kV
Inputs (VSENSE, COMP, FSET, ISET, SS)
BST
PHASE
PHASE Pulse tpulse < 50ns
Storage Temperature Range
Maximum Junction Temperature
All voltages with respect to AGND. Currents are positive into, negative out of the specified terminal.
Electrical Characteristics
Unless otherwise specified, AVDD = 3.3V, AVDD = PVDD , CT = 270pF, TA = -40°C to 85°C, TA=TJ
Parameter
Test C onditions
Min
Typ
Max
U nit
5.5
V
Overall
Supply Voltage
Supply C urrent, Sleep
Supply C urrent, Operati ng
AVDD Turn-on Threshold
E N = 0V
0.1
1
µA
AVDD = 5.5V
2
3.75
mA
2.7
V
mV
TA = -40°C to 85°C
AVDD Turn-off Hysteresi s
275
350
425
AVDD = 2.7V to 5.5V,
TA = -40°C to 85°C
0.49
0.5
0.51
AVDD = 2.7V to 5.5V, TA = 25°C
0.493
0.5
0.507
TA = -40°C to 85°C
0.492
0.5
0.508
TA = 25°C
0.495
0.5
0.505
Error Amplifier
FB Voltage
(Internal Reference)
VSENSE Bi as C urrent
Open Loop Gai n (1)
VSENSE = 0.5V
200
nA
VCOMP = 0.5 to 2.5V
90
dB
8
MHz
Uni ty Gai n Bandwi dth (1)
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SC4608
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, AVDD = 3.3V, AVDD = PVDD , CT = 270pF, TA = -40°C to 85°C, TA=TJ
Parameter
Test Conditions
Min
Typ
Max
Unit
Error Amplifier (Cont.)
Slew Rate (1)
VOUT High
ICOMP = -5.5mA
VOUT Low
ICOMP = 5.5mA
AVDD - 0.5
2.4
V/µs
AVDD - 0.3
V
0.3
0.45
575
625
kHz
TA = 25°C, AVDD = 2.7V to 5.5V
1
2.5
%/V
TA = -40°C to 85°C
0.02
Oscillator
Initial Accuracy
TA = 25°C
OSC Line Regulation
Temperature Coefficient
Minimum Operation Frequency (1)
525
%/°C
50
kHz
Maximum Operation Frequency (1)
1M
Hz
Ramp Peak to Valley
1
V
Ramp Peak Voltage
1.3
V
Ramp Valley Voltage
0.3
V
2
ms
Soft Start, Current Limit
Programmable Soft Start Time (1)
C = 22nF
Soft Start Charge Current
TA = 25°C
-4
-5.25
-6.5
µA
ISET Bias Current
TJ = 25°C
-45
-50
-55
µA
Temperature Coefficient of ISET
0.3
%/°C
Current Limit Blank Time (1)
130
ns
TA = 25°C
160
ns
Vgs = 3.3V, ISOURCE = 100mA
3.5
6
Ω
Vgs = 3.3V, ISINK = 100mA
3
5
Ω
Vgs = 3.3V, ISOURCE = 100mA
2.2
Peak Sink (DRVL)
Vgs = 3.3V, ISINK = 100mA
2
Output Rise Time
Vgs = 3.3V, COUT = 4.7nF
35
ns
Output Fall Time
Vgs = 3.3V, COUT = 4.7nF
27
ns
40
ns
Gate Drive
DRVH Minimum OFF Time (1)
Peak Source (DRVH)
Peak Sink (DRVH)
Peak Source (DRVL)
(1)
Minimum Non-Overlap (1)
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3
Ω
4
Ω
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SC4608
POWER MANAGEMENT
Electrical Characteristics
Unless otherwise specified, AVDD = 3.3V, AVDD = PVDD , CT = 270pF, TA = -40°C to 85°C, TA=TJ
Parameter
Test Conditions
Min
Typ
Max
Unit
0.15
0.3
V
1
µA
Pow er Good
PGOOD Voltage Low
PGOOD Leakage Current
IPGOOD = 1mA, AVDD = 5.5V
AVDD = 5.5V
PGOOD Upper Threshold
7.5
11.5
15.5
%
PGOOD Lower Threshold
-14.5
-10.5
-6.5
%
PGOOD Delay
14
ms
Enable
0.7 * AVDD
High Level Threshold
V
0.3 * AVDD
Low Level Threshold
EN Input Bias Current
V E N = 0V
-10
V
nA
Note: (1). Guaranteed by design.
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SC4608
POWER MANAGEMENT
Pin Configuration
Ordering Information
TOP VIEW
Part Number
Device(1)
SC4608MLTRT(2)
MLP-16
S C 4608E V B
Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
(16 Pin MLP)
Pin Descriptions
Pin #
Pin Name
1
AVDD
2
ISET
The ISET pin is used to limit current in the high side MOSFET. The SC4608 uses the
voltage across the VIN and ISET pins in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the VIN and PHASE pin.
3
COMP
This is the output of the voltage error amplifier. The voltage at this output is inverted
internally and connected to the non-inverting input of the PWM comparator. A lead-lag
network from the COMP pin to the VSENSE pin compensates for the two pole LC filter
characteristics inherent to voltage mode control. The lead-lag network is required in order
to optimize the dynamic performance of the voltage mode control loop.
4
FS E T
The FSET pin is used to sets the PWM oscillator frequency through an external timing
capacitor that is connected from the FSET pin to the GND pin. The SC4608 can be
operated in synchronous mode by placing a resistor in series between the timing capacitor
and ground. The other terminal of the timing capacitor will remain connected to the FSET
pin.
5
EN
The oscillator frequency of the SC4608 is set by FSET when EN is pulled and held above
0.7 * AVDD. Its shutdown mode is invoked if EN is pulled and held below 0.3 * AVDD.
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Pin Function
Power supply voltage for the analog section of the controller.
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SC4608
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Pin Descriptions (Cont.)
Pin #
Pin Name
6
PGOOD
7
SS
8
VSENSE
9
AGND
Analog ground.
10
PGND
Power ground.
11
DRVL
DRVL drives the gate of the low side (synchronous rectifier) MOSFET. The output drivers
are rated for 1A peak currents. The PWM circuitry provides complementary drive signals to
the output stages. The cross conduction of the external MOSFETs is prevented by
monitoring the voltage on the driver pins of the MOSFET pair in conjunction with a time
delay optimized for FET turn-off characteristics.
12
PHASE
13
DRVH
14
NC
No connection.
15
BST
This pin enables the converter to drive an N-Channel high side MOSFET. BST connects to
the external charge pump circuit. The charge pump circuit boosts the BST pin voltage to a
sufficient gate-to-source voltage level for driving the gate of the high side MOSFET.
16
PVD D
Thermal Pad
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Pin Function
Power good open drain output. Low when the output is below the power good threshold
level.
Soft start. A capacitor to ground sets the soft start time. The soft start time is independent
of switching frequency and is defined as SS = 0 . 09 • C . Where C is the external
capacitor in nF and SS is the soft start time in ms.
This pin is the inverting input of the voltage amplifier and serves as the output voltage
feedback point for the Buck converter. VSENSE is compared to an internal reference value
of 0.5V. VSENSE is hardwired to the output voltage when an output of 0.5V is desired.
For higher output voltages, a resistor divider network is necessary (R7 and R9 in the Typical
Application Circuit Diagram).
The PHASE pin is used to limit current in the high side MOSFET. The SC4608 uses the
voltage across the VIN and ISET pin in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the VIN and PHASE pin.
DRVH drives the gate of the high side (main switch) MOSFET. The output drivers are rated
for 1A peak currents. The PWM circuitry provides complementary drive signals to the
output stages. The cross conduction of the external MOSFETs is prevented by monitoring
the voltage on the driver pins of the MOSFET pair in conjunction with a time delay
optimized for FET turn-off characteristics.
Power supply voltage for low side MOSFET.
Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected
internally.
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SC4608
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Block Diagram
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SC4608
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Application Information
The maximum frequency of the external clock signal can
be higher than the natural switching frequency by about
10%.
Enable
The SC4608 is enabled by applying a voltage greater than
2.7 volts to the AVDD pin. The SC4608 is disabled when
AVDD falls below 2.35 volts or when sleep mode operation is invoked by clamping the EN pin to a voltage below
0.3*AVDD. 0.1µA is the typical current drawn through the
AVDD pin during sleep mode. During the sleep mode, the
high side and low side MOSFETs are turned off and the
internal soft start voltage is held low.
FSET
External
Clock
Signal
C
R
CFSET
A
1k
56pF
D
SC4608
RSYNC
100
Oscillator
Figure 1
The FSET pin is used to set the PWM oscillator frequency
through an external timing capacitor that is connected
from the FSET pin to the GND pin. The resulting ramp
waveform ion the FSET pin is a triangle at the PWM frequency with a peak voltage of 1.3V and a valley voltage
of 0.3V. 160ns minimum OFF time for the top switch
allows the bootstrap capacitor to be charged during each
cycle. The capacitor tolerance adds to the accuracy of
the oscillator frequency. The approximate operating frequency and soft start time are both determined by the
value of the external timing capacitor as shown in Table
1.
UVLO
When the EN pin is not pulled and held below 0.3*AVDD,
the voltage on the AVDD pin determines the operation of
the SC4608. As AVDD increases during start up, the UVLO
block senses AVDD and keeps the high side and low side
MOSFETs off and the internal soft start voltage low until
AVDD reaches 2.7V. If no faults are present, the SC4608
will initiate a soft start when AVDD exceeds 2.7V. A hysteresis (350mV) in the UVLO comparator provides noise immunity during its start up.
Power Good Indicator
External Timing
C apacitor Value (pF)
Frequency (kH z )
120
1000
270
575
470
350
560
295
The PGOOD pin is the open-drain output of the power
good comparators. These comparators are incorporated
with small amount of hysteresis. A pull-up resistor from
the PGOOD pin to the input supply or the output sets the
logic high level of the PGOOD signal. The VSENSE low-tohigh trip voltage of the power good comparator is 89%
of the final regulation voltage. The power good comparator output becomes valid provided that VO is within about
±11% of the programmed output voltage. In shutdown
mode the power good output is actively pulled low. The
PGOOD signal delay depends on its operating frequency
fs, for example, about 14ms@ fs=575kHz and 24ms @
fs=330kHz.
Table 1. Operating Frequency value Based on the
Value of the External Timing Capacitor Placed Across
the FSET and GND Pins
Synchronous mode operation is invoked by using a signal from an external clock. A low value resistor (100Ω
typical) must be inserted in series with the timing capacitor between the timing capacitor and the GND pin. The
other terminal of the timing capacitor will remain connected to the FSET pin. The transformed external clock
signal is then connected to the junction of the external
timing capacitor and the added resistor RSYNC as shown
in Figure 1.
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Soft Start
The soft start function is required for step down controllers to prevent excess inrush current through the DC bus
during start up. Generally this can be done by sourcing a
controlled current into a timing capacitor and then using
the voltage across this capacitor to slowly ramp up the
error amp reference. The closed loop creates narrow
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SC4608
POWER MANAGEMENT
Application Information (Cont.)
width driver pulses while the output voltage is low and
allows these pulses to increase to their steady state duty
cycle as the output voltage reaches its regulated value.
With this, the inrush current from the input side is controlled. The duration of the soft start in the SC4608 is
controlled by an external capacitor. SS, the start-up time
is defined as:
When the converter detects an over current condition
(I > IMAX) as shown in Figure 2, the first action the SC4608
takes is to enter the cycle by cycle protection mode (Point
B to Point C), which responds to minor over current cases.
Then the output voltage is monitored. If the over current
and low output voltage (set at 70% of nominal output
voltage) occur at the same time, the Hiccup mode operation (Point C to Point D) of the SC4608 is invoked
and the internal soft start capacitor is discharged. This is
like a typical soft start cycle:
SS = 0 . 09 • C
where, C is the value of the external capacitor in nF, and
SS is the start-up time in ms.
Figure 2. Over current protection characteristic of
SC4608
Over Current Protection
The SC4608 detects over current conditions by sensing
the voltage across the drain-to-source of the high side
MOSFET. The SC4608 determines the high side MOSFET current level by sensing the drain-to-source conduction voltage across the high side MOSFET via the Vin (see
the Typical Application Circuit on page 1) and PHASE pin
during the high side MOSFETs conduction period. This
voltage value is then compared internally to a user programmed current limit threshold. Note that user should
place Kelvin sensing connections directly from the high
side MOSFET source to the PHASE pin.
C
VO
D
IO
IMAX
Power MOSFET Drivers
The SC4608 has two drivers which are optimized for driving external power N-Channel MOSFETs. The driver block
consists two 1 Amp drivers. DRVH drives the high side
N-MOSFET (main switch), and DRVL drives the low side
N-MOSFET (synchronous rectifier transistor).
The output drivers also have gate drive non-overlap
mechanism that provides a dead time between DRVH
and DRVL transitions to avoid potential shoot through
problems in the external MOSFETs. By using the proper
design and the appropriate MOSFETs, the SC4608 is
capable of driving a converter with up to 12A of output
current. As shown in Figure 3, td1 the delay from the
,
top MOSFET off to the bottom MOSFET on is adaptive by
detecting the voltage of the phase node. td2, the delay
from the bottom MOSFET off to the top MOSFET on is
fixed, is 40ns for the SC4608. This control scheme guarantees avoidance of cross conduction or shoot through
IMAX ⋅ R DS( ON)
50µA
The RDS(ON) sensing used in the SC4608 has an additional feature that enhances the performance of the over
current protection. Because the RDS(ON) has a positive
temperature coefficient, the 50µA current source has a
positive coefficient of about 0.3%/C° providing first order correction for current sensing vs temperature. This
compensation depends on the high amount of thermal
transferring that typically exists between the high side NMOSFET and the SC4608 due to the compact layout of
the power supply.
 2006 Semtech Corp.
B
0. 7
6 ⋅ VO − nom
The current limit threshold is programmed by the user
based on the RDS(on) of the high side MOSFET and the
value of the external set resistor RSET (where RSET is
represented by R3 in the applications schematics of this
document). The SC4608 uses an internal current source
to pull a 50µA current from the input voltage to the ISET
pin through external resistor RSET.
The current limit threshold resistor (RSET) value is calculated using the following equation:
R SET =
A
V O − nom
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SC4608
POWER MANAGEMENT
Application Information (Cont.)
must be able to handle the peak inductor current IPEAK
without saturation and produce low core loss during the
high frequency operation is:
between the upper and lower MOSFETs and also minimizes the conduction loss in the body diode of the bottom MOSFET for high efficiency applications.
IPEAK = IOMAX +
TOP MOSFET Gate Drive
Ground
td1
td2
PCOPPER = I2LRMS ⋅ R WINDING
Where:
ILRMS is the RMS current in the inductor. This current can
be calculated as follow is:
Figure 3. Timing Waveforms for Gate Drives and Phase
Node
Inductor Selection
ILRMS = IOMAX ⋅ 1 +
The factors for selecting the inductor include its cost,
efficiency, size and EMI. For a typical SC4608 application, the inductor selection is mainly based on its value,
saturation current and DC resistance. Increasing the inductor value will decrease the ripple level of the output
voltage while the output transient response will be degraded. Low value inductors offer small size and fast transient responses while they cause large ripple currents,
poor efficiencies and more output capacitance to smooth
out the large ripple currents. The inductor should be able
to handle the peak current without saturating and its
copper resistance in the winding should be as low as
possible to minimize its resistive power loss. A good tradeoff among its size, loss and cost is to set the inductor
ripple current to be within 15% to 30% of the maximum
output current.
The inductor value can be determined according to its
operating point and the switching frequency as follows:
L=
1
⋅ ∆I2
3
Output Capacitor Selection
Basically there are two major factors to consider in selecting the type and quantity of the output capacitors.
The first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes.
The second one is the required capacitance, which should
be high enough to hold up the output voltage. Before the
SC4608 regulates the inductor current to a new value
during a load transient, the output capacitor delivers all
the additional current needed by the load. The ESR and
ESL of the output capacitor, the loop parasitic inductance
between the output capacitor and the load combined
with inductor ripple current are all major contributors to
the output voltage ripple. Surface mount speciality polymer aluminum electrolytic chip capacitors in UE series
from Panasonic provide low ESR and reduce the total
capacitance required for a fast transient response.
POSCAP from Sanyo is a solid electrolytic chip capacitor
that has a low ESR and good performance for high frequency with a low profile and high capacitance. Above
mentioned capacitors are recommended to use in
SC4608 application.
VOUT ⋅ ( VIN − VOUT )
VIN ⋅ fs ⋅ ∆I ⋅ IOMAX
Where:
fs = switching frequency and
∆I = ratio of the peak to peak inductor current to the
maximum output load current.
The peak to peak inductor current is:
Input Capacitor Selection
Ip −p = ∆I • IOMAX
The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This
capacitor must be able to provide the ripple current by
the switching actions. For the continuous conduction
After the required inductor value is selected, the proper
selection of the core material is based on the peak inductor current and efficiency requirements. The core
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2
The power loss for the inductor includes its core loss and
copper loss. If possible, the winding resistance should
be minimized to reduce inductor’s copper loss. The core
loss can be found in the manufacturer’s datasheet. The
inductor’ copper loss can be estimated as follows:
BOTTOM MOSFET Gate Drive
Phase node
Ip −p
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SC4608
POWER MANAGEMENT
Application Information (Cont.)
Where:
IB = the boost current and
VD= discharge ripple voltage.
mode, the RMS value of the input capacitor can be calculated from:
VOUT ⋅ ( VIN − VOUT )
V 2IN
ICIN(RMS ) = IOMAX ⋅
With fs = 300kH, VD=0.3V and IB = 50mA, the required
capacitance for the boost capacitor is:
This current gives the capacitor’s power loss as follows:
Cboost =
PCIN = I2 CIN(RMS ) ⋅ R CIN(ESR )
This capacitor’s RMS loss can be a significant part of the
total loss in the converter and reduce the overall converter efficiency. The input ripple voltage mainly depends
on the input capacitor’s ESR and its capacitance for a
given load, input voltage and output voltage. Assuming
that the input current of the converter is constant, the
required input capacitance for a given voltage ripple can
be calculated by:
CIN = IOMAX ⋅
Power MOSFET Selection
The SC4608 can drive an N-MOSFET at the high side
and an N-MOSFET synchronous rectifier at the low side.
The use of the high side N-MOSFET will significantly reduce its conduction loss for high current. For the top
MOSFET, its total power loss includes its conduction loss,
switching loss, gate charge loss, output capacitance loss
and the loss related to the reverse recovery of the bottom diode, shown as follows:
D ⋅ (1 − D)
fs ⋅ ( ∆VI − IOMAX ⋅ R CIN(ESR ) )
Where:
D = VO/VI , duty ratio and
∆VI = the given input voltage ripple.
PTOP _ TOTAL = I2 TOP _ RMS ⋅ R TOP _ ON +
Where:
RG = gate drive resistor,
QGD = the gate to drain charge of the top MOSFET,
QGS2 = the gate to source charge of the top MOSFET,
QGT = the total gate charge of the top MOSFET,
QOSS = the output charge of the top MOSFET and
Qrr = the reverse recovery charge of the bottom diode.
Boost Capacitor Selection
The boost capacitor selection is based on its discharge
ripple voltage, worst case conduction time and boost
current. The worst case conduction time Tw can be estimated as follows:
For the top MOSFET, it experiences high current and high
voltage overlap during each on/off transition. But for the
bottom MOSFET, its switching voltage is the bottom
diode’s forward drop during its on/off transition. So the
switching loss for the bottom MOSFET is negligible. Its
total power loss can be determined by:
1
⋅ Dmax
fs
Where:
fs = the switching frequency and
Dmax = maximum duty ratio.
The required minimum capacitance for boost capacitor
will be:
Cboost =
 2006 Semtech Corp.
ITOP _ PEAK ⋅ VI ⋅ fs
⋅
VGATE
RG
(Q GD + Q GS 2 ) + Q GT ⋅ VGATE ⋅ fs + (Q OSS + Q rr ) ⋅ VI ⋅ fs
Because the input capacitor is exposed to the large surge
current, attention is needed for the input capacitor. If
tantalum capacitors are used at the input side of the
converter, one needs to ensure that the RMS and surge
ratings are not exceeded. For generic tantalum capacitors, it is wise to derate their voltage ratings at a ratio of
2 to protect these input capacitors.
Tw =
IB 1
0.05
1
⋅ ⋅ Dmax =
⋅
⋅ 0.95 = 528nF
VD fs
0.3 300k
PBOT _ TOTAL = I2 BOT _ RMS ⋅ R BOT _ ON + Q GB ⋅ VGATE ⋅ fs + ID _ AVG ⋅ VF
Where:
QGB = the total gate charge of the bottom MOSFET and
VF = the forward voltage drop of the bottom diode.
IB
⋅ TW
VD
11
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SC4608
POWER MANAGEMENT
Application Information (Cont.)
For a low voltage and high output current application such
as the 3.3V/1.5V@12A case, the conduction loss is often dominant and selecting low RDS(ON) MOSFETs will noticeably improve the efficiency of the converter even
though they give higher switching losses.
L1
V out
PHASE
COMP
C1
C2
The gate charge loss portion of the top/bottom MOSFET’s
total power loss is derived from the SC4608. This gate
charge loss is based on certain operating conditions (fs,
VGATE, and IO).
C9
C4
VSENSE
R1
R7
S C 4608
R
R8
R9
The thermal estimations have to be done for both
MOSFETs to make sure that their junction temperatures
do not exceed their thermal ratings according to their
total power losses PTOTAL, ambient temperature TA and their
thermal resistance RθJA as follows:
TJ(max) < TA +
Figure 4. Compensation network provides 3 poles and
2 zeros.
For voltage mode step down applications as shown in
Figure 4, the power stage transfer function is:
PTOTAL
R θJA
1+
Loop Compensation Design
G VD (s) = VI
For a DC/DC converter, it is usually required that the
converter has a loop gain of a high cross-over frequency
for fast load response, high DC and low frequency gain
for low steady state error, and enough phase margin for
its operating stability. Often one can not have all these
properties at the same time. The purpose of the loop
compensation is to arrange the poles and zeros of the
compensation network to meet the requirements for a
specific application.
The compensation network will have the characteristic
as follows:
s
s
1+
ω
ωZ1
ωZ 2
⋅
GCOMP (s) = I ⋅
s
s
s
1+
⋅1+
ωP1
ωP 2
1+
Where
R7
)
R9
ωI =
1
R 7 ⋅ ( C1 + C 2 )
ωZ1 =
ωZ 2 =
12
1
R1 ⋅ C 2
1
(R 7 + R 8 ) ⋅ C 9
ωP1 =
 2006 Semtech Corp.
L1
+ s 2L 1C 4
R
Where:
R = load resistance and
RC = C4’s ESR.
The SC4608 has an internal error amplifier and requires
the compensation network to connect among the COMP
pin and VSENSE pin, GND, and the output as shown in
Figure 4. The compensation network includes C1, C2,
R1, R7, R8 and C9. R9 is used to program the output
voltage according to:
VO = 0.5 ⋅ (1 +
1+ s
s
1
RC ⋅ C4
C1 + C 2
R 1 ⋅ C1 ⋅ C 2
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SC4608
POWER MANAGEMENT
Application Information (Cont.)
ωP 2 =
1
R 8 ⋅ C9
Layout Guidelines
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, special attention must be paid to the PCB layouts. The goal of layout optimization is to identify the high di/dt loops and
minimize them. The following guideline should be used to
ensure proper functions of the converters.
After the compensation, the converter will have the following loop gain:
s
1+
1
s
s
1
⋅ ωI ⋅ VI 1 +
1+
RC ⋅ C 4
ωZ1
ωZ 2
VM
⋅
⋅
⋅
T(s) = GPWM ⋅ GCOMP (s) ⋅ G VD (s) =
s
s
L
s
⋅1+
1+
1 + s 1 + s 2L1C
ωP1
ωP 2
R
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
3. The AVDD bypass capacitor should be placed next to
the AVDD and AGND pins.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components.
5. Minimize the traces between DRVH/DRVL and the
gates of the MOSFETs to reduce their impedance to
drive the MOSFETs.
6. Minimize the loop including input capacitors, top/bottom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
7. ISET and PHASE connections to the top MOSFET for
current sensing must use Kelvin connections.
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
Where:
GPWM = PWM gain
VM = 1.0V, ramp peak to valley voltage of SC4608
The design guidelines for the SC4608 applications are
as following:
1. Set the loop gain crossover corner frequency ω C
for given switching corner frequency ωS = 2πfs,
2. Place an integrator at the origin to increase DC
and low frequency gains.
3. Select ωZ1 and ωZ2 such that they are placed near
ωO to damp the peaking and the loop gain has a
-20dB/dec rate to go across the 0dB line for
obtaining a wide bandwidth.
4. Cancel the zero from C4’s ESR by a compensator
pole ωP1 (ωP1 = ωESR = 1/( RCC4)).
5. Place a high frequency compensator pole ωp2 (ωp2
= πfs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate
phase lag at ωC.
The compensated loop gain will be as given in Figure 5:
9. Connect the ground of the feedback divider and the
compensation components directly to the AGND pin
of the SC4608 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible
T
ωZ1
Loop gain
ωo
ωZ2
Gvd
0dB
ωc
ωp1
ωp2
Power stage
ωESR
-
Figure 5. Asymptotic diagrams of power stage and its
loop gain
 2006 Semtech Corp.
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SC4608
POWER MANAGEMENT
Application Information (Cont.)
Design Example 1. 3V to1.5V @10A application with SC4608
Vin=3V - 5.5V
D2
R13
1
R3
SC4608
16
C3
1
1u
2
3
C16
4
5
470pF
C1
C2 2.2n
R2
10k
1.8n
R1
14.3k
Css
6
7
PVDD
BST
AVDD
DRVH
PHASE
FSET
DRVL
0
EN
PGND
PGOOD
AGND
SS
VSENSE
12
11
10
C14
22u
22u
R6
ISET
COMP
C13
220u
M11
15
13
C10
C17
1u
R5
L1
M2
0
2.3u
Vout=1.5V/ 10A
C7
C5
C4
C9
330u
22u
22u
8.2n
9
8
R7
5.76k
R8
107
22n
R9
2.87k
 2006 Semtech Corp.
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SC4608
POWER MANAGEMENT
Bill of Materials
Item
Qty
R eference
Value
Part N o./Manufacturer
1
1
C1
1.8nF
2
1
C2
2.2nF
3
1
C 17
1uF
4
4
C 4,C 5, C 13, C 14
22uF, 1206
TD K P/N: C 3225X5R0J226M
5
1
C7
330uF, 2870
Sanyo P/N: 6TPB330ML
6
1
C9
8.2nF
7
1
C 16
470pF
8
1
D2
MBR0520LT1
ON Semi P/N: MBR0520LT1
9
1
L1
2.3uH
C ooper Electroni c
P/N: HC 1-2R3
10
2
M1, M2
Powerpack, SO-8
Vi shay P/N: Si 7882D P
11
1
R1
14.3K
12
1
R3
1.33K
13
1
R7
5.76K
14
1
R8
107
15
1
R9
2.87K
16
1
R13
1
17
1
C3
1uF, 0805
18
1
C 10
220uF, 2870
19
1
C ss
22nF
20
1
U1
S C 4608
21
1
R2
10k
Sanyo P/N: 6TPB220ML
Semtech P/N: SC 4608IMLTRT
Unless speci fi ed, all resi stors have 1% preci si on wi th 0603 package.
Resi stors are +/-1% and all capaci tors are +/-20%
 2006 Semtech Corp.
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SC4608
POWER MANAGEMENT
PCB Layout
COMPONENT SIDE (TOP)
COMPONENT SIDE (BOTTOM)
 2006 Semtech Corp.
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SC4608
POWER MANAGEMENT
PCB Layout (Cont.)
(BOTTOM)
(TOP)
(INTER LAYER 2)
(INTER LAYER 1)
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SC4608
POWER MANAGEMENT
Outline Drawing - MLP-16
A
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
D
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
B
PIN 1
INDICATOR
(LASER MARK)
E
A2
A
0.80
1.00
0.00
0.05
(0.20)
0.25 0.30 0.35
3.90 4.00 4.10
2.55 2.70 2.80
3.90 4.00 4.10
2.55 2.70 2.80
0.65 BSC
0.30 0.40 0.50
16
0.08
0.10
SEATING
PLANE
aaa C
A1
.040
.031
.002
.000
(.008)
.010 .012 .014
.153 .157 .161
.100 .106 .110
.153 .157 .161
.100 .106 .110
.026 BSC
.012 .016 .020
16
.003
.004
C
D1
e/2
LxN
E/2
E1
2
1
N
e
D/2
bxN
bbb
C A B
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
 2006 Semtech Corp.
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SC4608
POWER MANAGEMENT
Land Pattern - MLP-16
K
DIM
2x (C)
H
2x G
2x Z
Y
X
C
G
H
K
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.156)
.122
.106
.106
.026
.016
.033
.189
(3.95)
3.10
2.70
2.70
0.65
0.40
0.85
4.80
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
 2006 Semtech Corp.
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