SC4612 NOT RECOMMENDED FOR NEW DESIGN Wide Input Range High Performance Synchronous Buck Switching Controller POWER MANAGEMENT Description Features SC4612 is a high performance synchronous buck controller that can be configured for a wide range of applications. The SC4612 utilizes synchronous rectified buck topology where high efficiency is the primary consideration. SC4612 is optimized for applications requiring wide input supply range and low output voltages down to 500mV. Wide voltage range, VDD = 28V, VPWRIN = 40V Internally regulated DRV Output voltage as low as 0.5V 1.7A gate drive capability Asynchronous start up mode Low side RDS-ON sensing with hiccup mode current limit Programmable current limit Programmable frequency up to 1.2 MHz Available in MLPD-12 and SOIC-14 Lead-free packages. This product is fully WEEE and RoHS compliant N O FO T R R EC N O EW M M D EN ES D IG ED N SC4612 implements an asynchronous soft-start mode, which keeps the lower side MOSFET off during soft-start, a desired feature when a converter turns on into a preset external voltage or pre-biased output voltage. With the lower MOSFET off, the external bus is not discharged, preventing any disturbances in the start up slope and any latch-up of modern day ASIC circuits. Applications SC4612 comes with a rich set of features such as regulated DRV supply, programmable soft-start, high current gate drivers, internal bootstrapping for driving high side N-channel MOSFET, shoot through protection, RDS-ON sensing with hiccup over current protection, and asynchronous start up with over current protection. Distributed power architectures Telecommunication equipment Servers/work stations Mixed signal applications Base station power management Point of use low voltage high current applications Typical Application Circuit R1 1 C2 R3 C3 C9 2 3 4 ILIM PHASE OSC DH SS/EN BST EAO DRV 12 11 D1 10 Q1 9 6 FB DL VDD GND C8 L1 C7 C4 5 Vin _ U1 SC4612MLP R2 C1 + + 8 Q2 7 C5 C10 Vout _ R5 R4 C6 Revision: January 31, 2007 R6 1 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units VD D -0.3 to 30 V -0.3 to 10 V 100 mA ILIM, to GND -0.3 to 10 V EAO, SS/EN, FB, OSC to GND -0.3 to +5 V DL to GND -0.3 to +10 V -0.3 to +10 V -2 to +40 V -0.3 to +10 V Bias Supply Voltage to GND DRV to GND BST to PHASE PHASE to GND DH to PHASE N O FO T R R EC N O EW M M D EN ES D IG ED N DRV Source Current (peak) VIN Thermal Resistance Junction to Ambient (MLPD) (1) θJA 45.3 °C/W Thermal Resistance Junction to Case (MLPD) θJ C 11 °C/W Thermal Resistance Junction to Ambient (SOIC) θ JA 115 °C/W Thermal Resistance Junction to Case (SOIC) θJ C 45 °C/W Operating Junction Temperature Range TJ -40 to +125 °C TSTG -65 to +150 °C TIR Reflow 260 °C Lead Temperature (10s), (SOIC-14) TLEAD 300 °C ESD Rating (Human Body Model) ESD 2 kV Storage Temperature Range Peak IR Reflow Temperature (10-40s) All voltages with respect to GND. Positive currents are into, and negative currents are out of the specified terminal. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500ns. Consult Packaging Section of Data sheet for thermal limitations and considerations of packages. Note: (1). 1 sq. inch of FR-4, double-sided, 1 oz copper weight. 2007 Semtech Corp. 2 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Electrical Characteristics Unless otherwise specified: VIN = VDD = 12V, FOSC = 600kHz, TA = TJ = -40°C to 125°C. Parameter Test Conditions Min Typ Max Units 28 V 5 7 mA 4.50 4.75 V Bias Supply VD D VDD = 28V, No load, SS/EN = 0 Quiescent Current VDD Undervoltage Lockout Start Threshold 4.20 N O FO T R R EC N O EW M M D EN ES D IG ED N UVLO Hysteresis Drive Regulator 10V ≤ VDD ≤ 28V, IOUT ≤ 1mA DRV 7.3 400 7.8 1mA ≤ IO ≤ 100mA Load Regulation Oscillator Operation Frequency Range Initial Accuracy (1) 100 COSC = 160pF (Ref only) Maximum Duty Cycle(2) 540 600 mV 8.3 V 100 mV 1200 kHz 660 kHz 85 Ramp Peak to Valley (1) Oscillator Charge Current % 850 90 mV 110 µA Current Limit (Low Side Rdson) Current Limit Threshold Voltage Error Amplifier Feedback Voltage Input Bias Current Open Loop Gain VOUT = 500mV, 3.3V, 5V 0.495 0.500 0.505 V TJ = -40 to +85°C 0.492 0.500 0.508 V TJ = -40 to +125°C 0.488 0.500 0.512 V 200 nA FB = 0.5V 60 dB 10 MHz Open Loop, FB = 0V 900 µA Open Loop, FB = 0.6V 1100 µA 1 V/µs (1) Output Sink Current Output Source Current 7 (1) 2007 Semtech Corp. mV TJ = 0 to +70°C Unity Gain Bandwidth (1) Slew Rate 100 3 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified: VIN = VDD = 12V, FOSC = 600kHz, TA = TJ = -40°C to 125°C. Parameter Test Conditions Min Typ Max Units 500 mV SS/EN Disable Threshold Voltage Soft Start Charge Current 25 µA 1 µA 50 ns CSS = 0.1, current limit condition 1 % Gate Drive On-Resistance (H)(2) ISOURCE = 100mA 3 4 Ω Gate Drive On-Resistance (L)(2) ISINK = 100mA 3 4 Ω DL Source/Sink Peak Current(2) COUT = 2000pF ±1.4 1.7 A DH Source/Sink Peak Current(2) COUT = 2000pF ±1.4 1.7 A Output Rise Time COUT = 2000pF 20 ns COUT = 2000pF 20 ns 30 ns Soft Start Discharge Current (1) Hiccup Hiccup duty cycle Gate Drive Output Fall Time N O FO T R R EC N O EW M M D EN ES D IG ED N Disable Low to Shut Down (1) Minimum Non-Overlap (1) Minimum On Time(2) 110 ns Notes: (1) Guaranteed by design. (2) Guaranteed by characterization. 2007 Semtech Corp. 4 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC4612 POWER MANAGEMENT Timing Diagrams No fault start up sequence VCC Vcc UVLO 4.58V SS/EN 2.75V 1.3V N O FO T R R EC N O EW M M D EN ES D IG ED N 0.8V 0.5V EAO DH Soft Start Duration Asynchronous Operation DL Over current fault at Asynchronous start up sequence Vcc UVLO 4.58V 2.75V Fault occur Fault removed, normal operation resumed VCC SS/EN 1.3V 0.8V 0.5V EAO EOA<FB+0.7V DH Soft Start Duration Fault present for 10 cycles 2007 Semtech Corp. Asynchronous Operation 5 DL www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Pin Configurations Ordering Information TOP VIEW Part Number(3) Package(2) SC4612MLTRT MLPD-12 SOIC-14 ILIM 1 12 PHASE SC4612STRT OSC 2 11 DH SC4612EVB(1) SS/EN 3 10 BST EAO 4 9 DRV FB 5 8 DL VDD 6 7 GND Temp. Range (TJ) -40°C to +125°C EVALUATION BOARD N O FO T R R EC N O EW M M D EN ES D IG ED N Notes: (1) When ordering please specify MLPD or SOIC package. (2) Only available in tape and reel packaging. A reel contains 3000 devices for MLPD package and 2500 for SOIC package.. (3) Lead-free product. This product is fully WEEE and RoHS compliant. (12 Pin MLPD) TOP VIEW NC 1 14 PHASE ILIM 2 13 DH OSC 3 12 BST SS/EN 4 11 DRV EAO 5 10 DL VDD 6 9 GND NC 7 8 FB (14 Pin SOIC) Marking Information - MLPD Marking Information - SOIC Top Mark Top Mark SC4612 yyww xxxxxxxxx 4612 yyww xxxxx nnnn yyww xxxxx nnnnnn = Part Number (Example: SC4612) yyww = Date Code (Example: 0552) xxxxxxxxx = Semtech Lot No. (Example: A01E90101) = Part Number (Example: 1531) = Date Code (Example: 0012) = Semtech Lot No. (Example:E9010) 2007 Semtech Corp. 6 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC4612 POWER MANAGEMENT Pin Descriptions Pin# SOIC Pin Name Pin Function 1, 7 NC No connection. 1 2 ILIM The current limit programing resistors (R2 & R3) in conjunction with an internal current s o urc e , p ro g ra m the c urre nt li mi t thre s ho ld fo r the lo w s i d e MOS F E T RD S -ON sensing. Once the voltage drop across the Low side MOSFET is larger than the drop across the programmed value, current limit condition occurs, and the hiccup current limit protection is activated. 2 3 OSC Oscillator Frequency set pin. An external capacitor to GND will program the oscillator fre q ue nc y. S e e Ta b le " F re q ue nc y vs . C OS C " o n p a g e 1 4 to d e te rmi ne o s c i lla to r frequency. 3 4 N O FO T R R EC N O EW M M D EN ES D IG ED N Pin # MLPD SS/EN Soft start pin. Internal current source connected to a single external capacitor will determine the soft-start duration for the output. Inhibits the chip if pulled down. TSS ≈ 4 5 5 8 6 6 7 9 8 10 9 11 10 12 11 EAO FB CSS X 1.2 ISS Error Amplifier output. A compensation network is connected from this pin to FB. The i nverti ng i nput of the error ampli fi er. Feedback pi n i s used to sense the output voltage via a resistive divider. VD D Bias supply ranging from 4.5V to 28V, VDD pin is initially used to provide the base drive to the internal pass transistor to regulate the DRV. GND Ground. DL DL signal (Drive Low). Gate drive for bottom MOSFET. DRV DRV supplies the output MOSFETs gate drive, and the chip analog circuitry. This pin should be bypassed with a 2.2µF ceramic capacitor to GND. DRV is internally regulated from the external supply connected to VDD. If VDD is below 10V , the supply could be directly connected to the DRV pin. BST BST signal. Supply for high side driver; can be directly connected to an external supply or to a bootstrap circuit. 13 DH DH signal (Drive High). Gate drive for top MOSFET. 12 14 PHASE X - THERMAL PAD (GND) 2007 Semtech Corp. The return path for the high side gate drive, also used to sense the voltage at the phase node for adaptive gate drive protection, and the low-side RDS-ON voltage sensing. Pad for heatsinking purposes. Connect to ground plane using multiple vias. 7 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Block Diagram VDD DRV BST TOP Side Gate Driver INTERNAL REGULATOR & BANDGAP GENERATOR BST PWM DH DH OVP GND PHASE OVP PWM Control EN Oscillator OCP OCP SYNC N O FO T R R EC N O EW M M D EN ES D IG ED N 900mV OSC PWM - + Synchronous Mode Error Amp. ILIM SS/EN PHASE Low Side Gate Driver Q S R Current Limit VCC GND + SOFT START SS & Enable SS DL DL FB FB REF EAO Over Voltage Protection FB 600mV 20% OVP + - OCP @ Asynchronous Start up S R Low Side 100% on Q Top Side off PWM Enable EAO > FB + 0.7 for more than 10 cycles Soft Start Cycle True Vcc UVLO PWM Enable SS Vcc UVLO 800mV + - False Allow Synchronous mode PWM Disable Synchronous Mode FB Vref + - S R Low Side Rdson OCP S R Q Q PWM Enable PWM Enable PWM Disable SS Vref+0.5 2007 Semtech Corp. + - 8 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC4612 POWER MANAGEMENT Applications Information INTRODUCTION START UP SEQUENCE The SC4612 is a versatile voltage mode synchronous rectified buck PWM convertor, with an input supply (VIN) ranging from 4.5V to 28V designed to control and drive N-channel MOSFETs. The power dissipation is controlled using a novel low voltage supply technique, allowing high speed and integration with the high drive currents to ensure low MOSFET switching loss. The synchronous buck configuration also allows converter sinking current from load without losing output regulation. Start up is inhibited until VDD input reaches its UVLO threshold. The UVLO limit is 4.5V (TYP). Meanwhile, the high side and low side gate drivers DH, and DL, are kept low. Once VDD exceeds the UVLO threshold, the external soft-start capacitor starts to be charged by a 25µA current source. If an over current condition occurs, the SS/EN pin will discharge to 500mV by an internal switch. During this time, both DH and DL will be turned off. When the SS pin reaches 0.8V, the converter will start switching. The reference input of the error amplifier is ramped up with the soft-start signal. Initially only the high side driver is enabled. Keeping the low side MOSFET off during start up is useful where multiple convertors are operating in parallel. It prevents forward conduction in the freewheeling MOSFET which might otherwise cause a dip in the common output bus. N O FO T R R EC N O EW M M D EN ES D IG ED N The internal reference is trimmed to 500mV with ± 1% accuracy, and the output voltage can be adjusted by two external resistors. A fixed oscillator frequency (up to 1.2MHz) can be programmed by an external capacitor for an optimized design. During the Asynchronous start up, the SC4612 provides a top MOSFET shut down over current protection, while under normal operating conditions a low side MOSFET RDS-ON current sensing with hiccup mode over current protection, minimizes power dissipation and provides further protection. Other features of the SC4612 include: In case of over current condition which is longer than 10 cycles during the asynchronous start up, SC4612 will turn off the high side MOSFET gate drive, and the soft-start sequence will repeat. When the SS pin reaches 1.3V, the low side MOSFET will begin to switch and the convertor is fully operational in the synchronous mode. The soft-start duration is controlled by the value of the SS cap. If the SS pin is pulled below 0.5V, the SC4612 is disabled and draws a typical quiescent current of 5mA. Wide input power voltage range (from 4.5V to 28V), low output voltages down to 500mV, externally programmable soft-start, hiccup over current protection, wide duty cycle range, thermal shutdown, asynchronous start-up protection, and a -40 to 125°C junction operating temperature range. Bias Generation SUPPLIES A 4.5V to 10V (MAX) supply voltage is required to power up the SC4612. This voltage could be provided by an external power supply or derived from VDD (VDD >10V) through an internal pass transistor. Two pins (VDD and DRV) are used to power up the SC4612. If input supply (VDD) is less than 10V (MAX), tie DRV and VDD together. The internal pass transistor will regulate the DRV from an external supply >10V connected to VDD to produce 7.8V (TYP) at the DRV pin. THEORY OF OPERATION This supply should be bypassed with a low ESR 2.2uF (or greater) ceramic capacitor directly at the DRV to GND pins of the SC4612. Soft start / Shut down An external capacitor at the SS/EN pin is used to set up the soft-start duration. The capacitor value in conjunction with the internal current source, controls the duration of soft-start time. If the SS/EN pin is pulled down to GND, the SC4612 is disabled. The soft-start pin is charged by a 25µA current source and discharged by an internal switch. When SS/EN is released it charges up to 0.5V as the control circuit starts up. The DRV supply also provides the bias for the low and the high side MOSFET gate drive. The maximum rating for DRV supply is 10V and for applications where input supply is below 10V, it may be connected directly to VDD. 2007 Semtech Corp. 9 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC4612 POWER MANAGEMENT Applications Information (Cont.) The reference input of the error amplifier is effectively ramped up with the soft-start signal. The error amp output will vary between 100mV and 1.2V, depending on the duty cycle. The error amp will be off until SS/EN reaches 0.7V (TYP) and will move the output up to its desired voltage by the time SS/EN reaches 1.3V. The gate drivers will be in asynchronous mode until the FB pin reaches 500mV. OVERCURRENT PROTECTION SC4612 features low side MOSFET on-state Rds current sensing and hiccup mode over current protection. ILIM pin would be connected to DRV or PHASE via programming resistors to adjust the over current trip point to meet different customer requirements. The sampling of the current thru the bottom FET is set at ~150ns after the bottom FET drive comes ON. It is done to prevent a false tripping of the current limit circuit due to the ringing at the phase node when the top FET is turned OFF. Internally overcurrent threshold is set to 100mV_typ. If voltage magnitude at the phase node during sampling is such that the current comparator meets this condition then the OCP occurs. Connecting a resistor from external voltage source such as VDD, DRV, etc. to ILIM increases the current limit. Connecting a resistor from ILIM to PHASE lowers the current limit (see the block diagram in page 9). Internal current source at ILIM node is ~20µA. External programming resistors add to or subtract from that source and hence vary the threshold. The tolerance of the collective current sink at ILIM node is fairly loose when combined with variations of the FET’s Rds(on). Therefore when setting current limit some iteration might be required to get to the wanted trip point. Nonetheless, this circuit does serve the purpose of a hard fault protection of the power switches. When choosing the current limit one should consider the cumulative effect of the load and inductor ripple current. As a rule of thumb, the limit should be set at least x10 greater then the pk-pk ripple current. Whenever a high current peak is detected, SC4612 would first block the driving of the high side and low side MOSFET, and then discharge the soft-start capacitor. Discharge rate of the SS capacitor is 1/25 of the charge rate. N O FO T R R EC N O EW M M D EN ES D IG ED N The intention for the asynchronous start up is to keep the low side MOSFET from being switched on which forces the low side MOSFETs body diode or the parallel Schottky diode to conduct. The conduction by the diode prevents any dips in an existing output voltage that might be present, allowing for a glitch free start up in applications that are sensitive to any bus disturbances. During the asynchronous start up SC4612 monitors the output and if within 10 cycles the FB has not reached the internal soft start ramp level, the device switches to synchronous mode. This provides an added protection in case of short circuit at the output during the asynchronous start when the bottom MOSFET is not being switched to provide the RDS-ON sensing current limit protection. In case of a current limit, the gate drives will be held off until the soft-start is initiated. The soft-start cycle defined by the SS cap being charged from 800mV to 1.3V and slowly discharged to achieve an approximate hiccup duty cycle of 1% to minimize excessive power dissipation. The part will try to restart on the next softstart cycle. If the fault has cleared, the outputs will start . If the fault still remains, the part will repeat the soft-start cycle above indefinitely until the fault has been removed. The soft-start time is determined by the value of the softstart capacitor (see formula below). TSS ≈ CSS X 1.2 ISS Oscillator Frequency Selection Under Voltage Lock Out The internal oscillator sawtooth signal is generated by charging an external capacitor with a current source of 100µA charge current. Under Voltage Lock Out (UVLO) circuitry senses the VDD through a voltage divider. If this signal falls below 4.5V (typical) with a 400mV hysteresis (typical), the output drivers are disabled . During the thermal shutdown, the output drivers are disabled. See Table 1 “Frequency vs. COSC” on page 14 to determine oscillator frequency. 2007 Semtech Corp. 10 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Applications Information (Cont.) Below are examples of calculating the OCP trip voltages. Low Side RDS_ON Current Limit SC4612 2.75V DRV pin Vin R3 130k Ra R4 260k R1 2k N O FO T R R EC N O EW M M D EN ES D IG ED N ILIM pin COMP Rb R2 L OCP +100mV 10k PHASE pin R load Iload@Toff C1 2pF R5 10k C2 5pF 1. Ra, Rb - Not installed: 2.75 V − 100mV 100mV − Vphase = R3 R2 solving for: VPHASE = -100mV, therefore the circuit will trip @ RDS_ON x ILOAD = 100mV 2. To lower trip voltage - install Rb. For example: Rb = 13k 2.75 V − 100mV 100mV − Vphase = R3 R2 || (Rb + R1) solving for: VPHASE = -20mV, obviously more sensitive! RDS_ON x ILOAD = 20mV 3. To increase trip voltage - install Ra. For example: Ra = 800k; VDRIVE = 7.8V typ. 2.75 V − 100mV Vdrive 100mV − Vphase + = R3 Ra + R1 R2 solving for: VPHASE = -200mV. Current limit has doubled compared to original conditions. NOTE! Allow for tempco and RDS_ON variation of the MOSFET - see “overcurrent protection” information on page 11 in the datasheet. 2007 Semtech Corp. 11 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Applications Information (Cont.) Gate Drive/Control where, The SC4612 also provides integrated high current gate drives for fast switching of large MOSFETs. The high side and low side MOSFET gates could be switched with a peak gate current of 1.7A. The higher gate current will reduce switching losses of the larger MOSFETs. VIN – Input voltage RL – Load resistance L – Output inductance C – Output capacitance ESRC – Output capacitor ESR VS – Peak to peak ramp voltage The low side gate drives are supplied directly from the DRV. The high side gate drives could be provided with the classical bootstrapping technique from DRV. The classical Type III compensation network can be built around the error amplifier as shown below: N O FO T R R EC N O EW M M D EN ES D IG ED N Cross conduction prevention circuitry ensures a non overlapping (30ns typical) gate drive between the top and bottom MOSFETs. This prevents shoot through losses which provides higher efficiency. Typical total minimum off time for the SC4612 is about 30ns which will cause the maximum duty cycle at higher frequencies to be limited to lower than 100%. C2 R3 R2 C1 R1 OVERVOLTAGE PROTECTION + Vref If the FB pin ever exceeds 600mV, the top side driver is latched OFF, and the low side driver is latched ON. This mode can only be reset by power supply cycling. Figure 1. Voltage mode buck converter compensation network ERROR AMPLIFIER DESIGN The SC4612 is a voltage mode buck controller that utilizes an externally compensated high bandwidth error amplifier to regulate output voltage. The power stage of the synchronous rectified buck converter control-to-output transfer function is as shown below: The transfer function of the compensation network is as follows: s )(1 + ω ωZ1 GCOMP (s) = I ⋅ s (1 + s )(1 + ωP1 + 1 sESR C V C IN × G ( s) = VD L V + s2LC S 1+ s R L (1 + s ) ωZ 2 s ) ωP 2 where, ωZ1 = ωI = 2007 Semtech Corp. C3 12 1 1 1 , ωZ 2 = , ωo = R 2C1 (R1 + R 3 )C2 Lout × Cout 1 , R1(C1 + C3 ) ωP1 = 1 , R3C2 ωP 2 = 1 C1C3 R2 C1 + C3 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) The design guidelines are as following: T 1. Set the loop gain crossover frequency wC for given switching frequency. ω Z1 Loop gain T(s) ωo ω Z2 2. Place an integrator at the origin to increase DC and low frequency gains. Gd ωc 0dB 3. Select wZ1 and wZ2 such that they are placed near wO to dampen peaking; the loop gain should cross 0dB at a rate of -20dB/dec. ω p1 ω p2 4. Cancel wESR with compensation pole wP1 (wP1 = wESR ). ω ESR N O FO T R R EC N O EW M M D EN ES D IG ED N 5. Place a high frequency compensation pole wP2 at half the switching frequency to get the maximum attenuation of the switching ripple and the high frequency noise with adequate phase lag at wC. Figure 2. Simplified asymptotic diagram of buck power stage and its compensated loop gain. Switching Frequency, FSW vs. COSC. 1200 1100 1000 900 Cosc, (pF) 800 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 Frequency, (kHz) Table 1 2007 Semtech Corp. 13 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) PCB LAYOUT GUIDELINES Careful attention to layout is necessary for successful implementation of the SC4612 PWM controller. High switching currents are present in the application and their effect on ground plane voltage differentials must be understood and minimized. VIN I (Input Capacitor) Ids (Top Fet) 1) The high power section of the circuit should be laid out first. A ground plane should be used. The number and position of ground plane interruptions should not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas; for example, the input capacitor and bottom FET ground. I (Inductor) Vout Vphase + N O FO T R R EC N O EW M M D EN ES D IG ED N Vout 2) The loop formed by the Input Capacitor(s) (Cin), the Top FET (M1), and the Bottom FET (M2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. I (Output Capacitor) + Ids (Bottom Fet) Voltage and current waveforms of buck power stage . 3) The connection between the junction of M1, M2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short. Top FET gate charge currents flow in this trace. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only, and therefore, connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC4612 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin, M1, M2 loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, M1, M2 loop. Under no circumstances should GND be returned to a ground inside the Cin, M1, M2 loop. 6) Allow adequate heat sinking area for the power components. If multiple layers will be used, provide sufficent vias for heat transfer 2007 Semtech Corp. 14 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) The maximum inductor value may be calculated from: COMPONENT SELECTION: L ≤ SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from: Vt It The calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from: N O FO T R R EC N O EW M M D EN ES D IG ED N R ESR ≤ Where Vt = Maximum transient voltage excursion ILRIPPLE = I t = Transient current step Each Capacitor C (uF) ESR (mΩ) Low ESR Tantalum 330 60 OS-CON 330 Low ESR Aluminum 1500 POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. Total Qty Rqd. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. C (uF) ESR (mΩ) 6 2000 10 25 3 990 8.3 PCOND = IO2 ⋅ RDS( on ) ⋅ D 44 5 7500 8.8 where a) Conduction losses are simply calculated as: D = duty cycle ≈ The choice of which to use is simply a cost/performance issue, with low ESR Aluminum being the cheapest, but taking up the most space. VO VIN b) Switching losses can be estimated by assuming a switching time, If we assume 100ns then: INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. 2007 Semtech Corp. VIN 4 ⋅ L ⋅ fOSC Ripple current allowance will define the minimum permitted inductor value. For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10mΩ. To meet this kind of ESR level, there are three available capacitor technologies. Technology R ESR C (VIN − V O ) It PSW = IO ⋅ VIN ⋅ 100ns TSW or more generally, IO ⋅ VIN ⋅ ( t r + t f ) ⋅ fOSC 2 c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume PSW = 15 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC4612 POWER MANAGEMENT Application Information (Cont.) mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of 40oC/W for the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below: that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be: P RR = Q RR ⋅ V IN ⋅ f OSC Temperature rise ( 0C) To a first order approximation, it is convenient to only consider conduction losses to determine FET suitability. For a 5V in, 2.8V out at 14.2A requirement, typical FET losses would be: RDS(on) (mΩ) IRL3402S 15 IRL2203 10.5 Si4410 20 PD(W) Package Top FET Bottom FET IRL3402S 67.6 53.2 IRL2203 47.6 37.2 Si4410 180.8 141.6 N O FO T R R EC N O EW M M D EN ES D IG ED N FET Type FET Type 1.69 D2PAK 1.19 D2PAK 2.26 SO-8 It is apparent that single SO-8 Si4410 are not adequate for this application, By using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. Using 1.5X Room temp RDS(ON) to allow for temperature rise. INPUT CAPACITORS - Since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it resulting in very low switching losses. Conduction losses for the FET can be determined by: PCOND = I2O ⋅ RDS( on ) ⋅ (1 − D) For the example above: FET Type RDS(on) (mΩ) PD(W) Package IRL3402S 15 1.33 D2PAK IRL2203 10.5 0.93 D2PAK Si4410 20 1.77 SO-8 Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the surface 2007 Semtech Corp. 16 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) Application Circuit 1: Vin = 36V; Vout = 5V @ 20A, Fsw = 250kHz. + C14 A 330/50V_AL R1 560k 1 2 R3 10k C5 1.3n 3 4 5 ILIM PHASE OSC DH SS/EN BST 12 11 D1 MBR0 540 10 N O FO T R R EC N O EW M M D EN ES D IG ED N C3 0. 1 EAO DRV FB DL Q1 HAT 2172H 9 C10 0. 1 L1 4.7u H@ 22 A Q2 HAT 2172H 8 + C8 2.2/10V R4* 6 Z1* VDD Vin=36V _ U1 SC4612MLP C2 430 p C4 9.1n C14B 330/50V_AL GND 7 C12 A C12B C13 A 330 /6.3V 330 /6.3V 330 /6.3V C9 10/50V_cer C13B 10/6.3V_cer C6 1_cer Vout=5@20A _ R6 48.7 k R5 5.36 k Fsw =250k Hz C7 1.3n R7 910 R4*: if Vin > 28V, then R4 & Z1 provide VDD clamping Efficiency: Efficiency SC4612: 36Vin, 5Vout @ 20A 100% 98% 96% 94% 92% 90% 88% 86% 84% 82% 80% 0 2 4 6 8 10 12 14 16 18 20 22 Current, (A) 2007 Semtech Corp. 17 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) Application Circuit 2: Vin = 24V; Vout = 3.3V @ 20A, Fsw = 500kHz. + Vin=24V C14A 470/35V_AL R1 560k C14B 470/35V_AL U1 SC4612MLP 1 C3 0.1 C4 3.9n R3 10k C5 300p R4opt C6 1/16V 25V ILIM 2 3 4 5 6 PHASE OSC DH SS/EN BST 12 11 D1 MBR0540 10 N O FO T R R EC N O EW M M D EN ES D IG ED N C2 200p EAO DRV FB DL VDD GND _ R8 0 Q1 HAT2168H C8 R9 2.2/10V 0 Q2 HAT2165H 9 8 7 C10 0.1 L1 1.5uH@22A + C12A C12B C13A 180/4V_PosCap 180/4V 180/4V C9 22/25V_cer Vout=3.3@20A C13B 10/6.3V_cer _ R6 39.2k R5 6.98k C7 750p Efficiency: Fsw=500kHz R7 887 Efficiency SC4612: 24Vin, 3.3Vout @ 20A 100% 98% 96% 94% 92% 90% 88% 86% 84% 82% 80% 0 2 4 6 8 10 12 14 16 18 20 22 Current, (A) 2007 Semtech Corp. 18 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) Application Circuit 3: Vin = 12V; Vout = 2.5V @ 12A, Fsw = 800kHz + Vin=12V C14A 47/16V_AL R1 825k C14B 47/16V _AL _ U1 SC4612MLP C3 0.1 C4 3.3n R3 10k C5 300p R4opt 20 C6 1/16V 2 3 4 5 6 ILIM 12 PHASE OSC 11 DH D1 SD107WS 10 N O FO T R R EC N O EW M M D EN ES D IG ED N 1 C2 120p SS/EN BST EAO DRV FB 8 DL VDD R8 0 Q1 HAT2168H C8 R9 2.2/10V 0 Q2 HAT2165H 9 7 GND C10 0.1 L1 1.4uH@14A C12A C12B 220/4V _PosCap 220/4V C9 22/16V _cer + C13A N/A Vout=2.5@12A C13B 10/6.3V_cer _ R6 11.0k R5 2.74k C7 2.2n Efficiency: Fsw=800kHz R7 178 Efficiency SC4612: 12Vin, 2.5Vout @ 12A 100% 98% 96% 94% 92% 90% 88% 86% 84% 82% 80% 0 1 2 3 4 5 6 7 8 9 10 11 12 Current, (A) 2007 Semtech Corp. 19 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) Application Circuit 4: Vin = 5V; Vout = 1.35V @ 12A, Fsw = 1MHz. + Vin=5V R2 825k U1 SC4612MLP 1 R3 10k C4 1n C5 33p 2 3 4 5 6 C6 1 ILIM PHASE OSC DH _ 12 11 N O FO T R R EC N O EW M M D EN ES D IG ED N C2 82p C3 0.1 D1 SD107WS SS/EN BST EAO DRV FB DL VDD GND 10 C10 0.1 Q1 HAT2168H 9 L1 0.47uH@15A C8 2.2 8 7 Q2 HAT2168H C11 100/6.3_1210_cer C9 100/6.3_1210_cer + Vout=1.35@12A _ R6 13.3k R5 8.87k Fsw=1MHz C7 510p Efficiency: R7 649 Efficiency SC4612: 5Vin, 1.35Vout @ 12A 100% 98% 96% 94% 92% 90% 88% 86% 84% 82% 80% 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Current, (A) 2007 Semtech Corp. 20 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC4612 POWER MANAGEMENT Application Information (Cont.) Evaluation Board 1: N O FO T R R EC N O EW M M D EN ES D IG ED N Top layer and components view Bottom Layer: 2007 Semtech Corp. 21 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC4612 POWER MANAGEMENT Application Information (Cont.) N O FO T R R EC N O EW M M D EN ES D IG ED N Evaluation Board 2 (actual size): Top layer: 2007 Semtech Corp. Bottom layer: 22 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Outline Drawing - MLPD - 12 A D PIN1 INDICATOR (LASER MARK) B DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX E A2 A SEATING PLANE aaa C A A1 A2 b D D1 E E1 e L N aaa bbb .031 .035 .040 .000 .001 .002 - (.008) .007 .010 .012 .154 .157 .161 .124 .130 .134 .114 .118 .122 .061 .067 .071 .020 BSC .012 .016 .020 12 .003 .004 0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.90 4.00 4.10 3.15 3.30 3.40 2.90 3.00 3.10 1.55 1.70 1.80 0.50 BSC 0.30 0.40 0.50 12 0.08 0.10 C N O FO T R R EC N O EW M M D EN ES D IG ED N A1 D1 D1/2 1 2 E1/2 E1 LxN N bxN bbb e C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Land Pattern - MLPD - 12 DIMENSIONS DIM C G H K P X Y Z INCHES (.114) .087 .067 .138 .020 .012 .028 .142 MILLIMETERS (2.90) 2.20 1.70 3.50 0.50 0.30 0.70 3.60 NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2007 Semtech Corp. 23 www.semtech.com SC4612 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Outline Drawing - SOIC - 14 A 2X D e N DIM A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc E/2 E1 E ccc C 1 2X N/2 TIPS 2 3 B D DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .053 .069 .004 .010 .049 .065 .012 .020 .007 .010 .337 .341 .344 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 14 0° 8° .004 .010 .008 1.35 1.75 0.10 0.25 1.25 1.65 0.31 0.51 0.17 0.25 8.55 8.65 8.75 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 14 0° 8° 0.10 0.25 0.20 aaa C h N O FO T R R EC N O EW M M D EN ES D IG ED N A2 A SEATING PLANE C bxN bbb A1 h H C A-B D GAGE PLANE 0.25 SIDE VIEW SEE DETAIL L (L1) A DETAIL c 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AB. Land Pattern - SOIC - 14 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 302A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2007 Semtech Corp. 24 www.semtech.com