TI SN74LV594APWR

 SCLS413I − APRIL 1998 − REVISED APRIL 2005
D 2-V to 5.5-V VCC Operation
D Max tpd of 6.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
D
D
D
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QA
SER
RCLR
RCLK
SRCLK
SRCLR
QH′
SN54LV594A . . . FK PACKAGE
(TOP VIEW)
QD
QE
NC
QF
QG
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
QH
description/ordering information
4
The ’LV594A devices are 8-bit shift registers
designed for 2-V to 5.5-V VCC operation.
SER
RCLR
NC
RCLK
SRCLK
SRCLR
D
16
2
NC
VCC
QA
D
1
QC
QB
D
QB
QC
QD
QE
QF
QG
QH
GND
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation
on All Ports
8-Bit Serial-In, Parallel-Out Shift
Registers With Storage
Independent Direct Overriding Clears
on Shift and Storage Registers
Independent Clocks for Shift and
Storage Registers
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
GND
NC
Q H′
D
SN54LV594A . . . J OR W PACKAGE
SN74LV594A . . . D, DB, NS, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
These devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are
provided on the shift and storage registers. A serial output (QH′) is provided for cascading purposes.
ORDERING INFORMATION
SN74LV594AD
Reel of 2500
SN74LV594ADR
SOP − NS
Reel of 2000
SN74LV594ANSR
74LV594A
SSOP − DB
Reel of 2000
SN74LV594ADBR
LV594A
Tube of 90
SN74LV594APW
Reel of 2000
SN74LV594APWR
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tube of 40
SOIC − D
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV594A
LV594A
Reel of 250
SN74LV594APWT
CDIP − J
Tube of 25
SNJ54LV594AJ
SNJ54LV594AJ
CFP − W
Tube of 150
SNJ54LV594AW
SNJ54LV594AW
LCCC − FK
Tube of 55
SNJ54LV594AFK
SNJ54LV594AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2005, Texas Instruments Incorporated
!"#$% !%&% '
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SCLS413I − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
The shift-register (SRCLK) and storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied
together, the shift register always is one clock pulse ahead of the storage register.
FUNCTION TABLE
INPUTS
2
FUNCTION
SER
SRCLK
SRCLR
RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
L
↓
H
X
X
Shift register state is not changed.
X
X
X
X
L
Storage register is cleared.
X
X
X
↑
H
Shift register data is stored in the storage register.
X
X
X
↓
H
Storage register state is not changed.
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logic diagram (positive logic)
RCLR
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D Q
C1
R
2D Q
C2
R
2D Q
C2
R
R
3D Q
C3
15
R
3D Q
C3
1
R
3D Q
C3
2
R
3D Q
C3
2D Q
C2
R
R
3D Q
C3
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
3
4
R
3D Q
C3
5
R
3D Q
C3
6
R
3D Q
C3
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH′
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
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SCLS413I − APRIL 1998 − REVISED APRIL 2005
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
QA
QB
QC
QD
QE
QF
QG
QH
QH’
4
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SCLS413I − APRIL 1998 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance or
power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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SCLS413I − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 4)
SN54LV594A
VCC
VIH
Supply voltage
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
IOH
IOL
∆t/∆v
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
2
5.5
2
5.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
Output voltage
UNIT
V
V
0.5
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
0
0
0
VCC
−50
VCC = 2 V
VCC = 2.3 V to 2.7 V
V
VCC
−50
µA
0
V
−2
−6
−6
−12
−12
50
50
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
2
2
6
6
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
12
12
200
200
100
100
20
20
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
VCC × 0.3
5.5
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
Input transition rise or fall rate
MAX
1.5
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
MIN
1.5
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level output current
SN74LV594A
mA
µA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV594A
PARAMETER
VOH
VOL
TEST CONDITIONS
IOH = −50 µA
IOH = −2 mA
IOL = 6 mA
IOL = 12 mA
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
IO = 0
TYP
MIN
VCC−0.1
2
3V
2.48
2.48
4.5 V
3.8
TYP
MAX
UNIT
V
3.8
2 V to 5.5 V
0.1
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
V
0.55
0.55
0 to 5.5 V
±1
±1
µA
5.5 V
20
20
µA
0
5
5
µA
3.3 V
3.5
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6
SN74LV594A
MAX
VCC−0.1
2
2.3 V
IOL = 50 µA
IOL = 2 mA
VI = 5.5 V or GND
VI = VCC or GND,
MIN
2 V to 5.5 V
IOH = −6 mA
IOH = −12 mA
II
ICC
VCC
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3.5
pF
SCLS413I − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
Setup time
MIN
MAX
SN74LV594A
MIN
RCLK or SRCLK high or low
7
7.5
7.5
RCLR or SRCLR low
6
6.5
6.5
SER before SRCLK↑
5.5
5.5
5.5
SRCLK↑ before RCLK↑†
tsu
SN54LV594A
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
8
9
9
8.5
9.5
9.5
6
6.8
6.8
6.7
7.6
7.6
MAX
UNIT
ns
ns
th
Hold time
SER after SRCLK↑
1.5
1.5
1.5
ns
† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
RCLK or SRCLK high or low
tw
tsu
Pulse duration
Setup time
SN54LV594A
MIN
MAX
SN74LV594A
MIN
5.5
5.5
5.5
RCLR or SRCLR low
5
5
5
SER before SRCLK↑
3.5
3.5
3.5
SRCLK↑ before RCLK↑†
8
8.5
8.5
SRCLR low before RCLK↑
8
9
9
SRCLR high (inactive) before SRCLK↑
4.2
4.8
4.8
RCLR high (inactive) before RCLK↑
4.6
5.3
5.3
MAX
UNIT
ns
ns
th
Hold time
SER after SRCLK↑
1.5
1.5
1.5
ns
† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
RCLK or SRCLK high or low
tw
tsu
Pulse duration
Setup time
SN54LV594A
MIN
MAX
SN74LV594A
MIN
5
5
5
RCLR or SRCLR low
5.2
5.2
5.2
SER before SRCLK↑
3
3
3
SRCLK↑ before RCLK↑†
5
5
5
SRCLR low before RCLK↑
5
5
5
SRCLR high (inactive) before SRCLK↑
2.9
3.3
3.3
RCLR high (inactive) before RCLK↑
3.2
3.7
3.7
MAX
UNIT
ns
ns
th
Hold time
SER after SRCLK↑
2
2
2
ns
† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
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switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
RCLK
free-air
TA = 25°C
TYP
MAX
temperature
SN54LV594A
SN74LV594A
LOAD
CAPACITANCE
MIN
CL = 15 pF
65*
80*
45*
45
CL = 50 pF
60
70
40
40
QA−QH
MIN
6.4*
10.6*
1*
6.3*
10.4*
7.4*
12.1*
7.2*
MAX
MIN
MAX
11.1*
1
11.1
1*
11.1*
1
11.1
1*
12.8*
1
12.8
11.6*
1*
12.8*
1
12.8
QH′
H
RCLR
QA−QH
7.9*
12.7*
1*
13.6*
1
13.6
SRCLR
QH′
7.4*
11.9*
1*
13.1*
1
13.1
9.5
14.1
1
14.6
1
14.6
10.8
15.5
1
17.2
1
17.2
10.6
15.7
1
16.5
1
16.5
11.3
16.1
1
18.6
1
18.6
RCLK
QA−QH
SRCLK
QH′
H
RCLR
QA−QH
12.1
17.4
1
19
1
19
SRCLR
QH′
11.6
16.5
1
18.6
1
18.6
CL = 50 pF
UNIT
MHz
SRCLK
CL = 15 pF
range,
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
RCLK
QA−QH
tPLH
tPHL
SRCLK
QH′
H
RCLR
QA−QH
SRCLR
QH′
tPHL
TA = 25°C
TYP
MAX
temperature
SN54LV594A
MIN
CL = 15 pF
80*
120*
70*
70
CL = 50 pF
55
105
50
50
CL = 15 pF
MIN
MAX
MIN
MAX
4.6*
8*
1*
8.5*
1
8.5
4.9*
8.2*
1*
8.8*
1
8.8
5.4*
9.1*
1*
9.7*
1
9.7
5.5*
9.2*
1*
9.9*
1
9.9
6*
9.8*
1*
10.6*
1
10.6
5.6*
9.2*
1*
10*
1
10
6.9
10.5
1
11.1
1
11.1
8.1
11.9
1
13.1
1
13.1
7.7
11.7
1
12.4
1
12.4
8.4
12.5
1
13.9
1
13.9
QA−QH
tPLH
tPHL
SRCLK
QH′
H
RCLR
QA−QH
9.1
13.1
1
14.4
1
14.4
SRCLR
QH′
8.5
12.4
1
14
1
14
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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UNIT
MHz
RCLK
CL = 50 pF
range,
SN74LV594A
LOAD
CAPACITANCE
tPLH
tPHL
tPHL
8
free-air
ns
ns
SCLS413I − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
RCLK
TA = 25°C
TYP
MAX
temperature
SN54LV594A
MIN
CL = 15 pF
135*
170*
115*
115
CL = 50 pF
120
140
95
95
QA−QH
MIN
MAX
MIN
MAX
3.3*
6.2*
1*
6.5*
1
6.5
3.7*
6.5*
1*
6.9*
1
6.9
3.7*
6.8*
1*
7.2*
1
7.2
4.1*
7.2*
1*
7.6*
1
7.6
QH′
H
RCLR
QA−QH
4.5*
7.6*
1*
8.2*
1
8.2
SRCLR
QH′
4.1*
7.1*
1*
7.6*
1
7.6
4.9
7.8
1
8.3
1
8.3
5.8
8.9
1
9.7
1
9.7
5.5
8.6
1
9.1
1
9.1
6
9.2
1
10.1
1
10.1
6.6
10
1
10.7
1
10.7
6
9.2
1
10.1
1
10.1
RCLK
QA−QH
SRCLK
QH′
H
RCLR
QA−QH
SRCLR
QH′
CL = 50 pF
UNIT
MHz
SRCLK
CL = 15 pF
range,
SN74LV594A
LOAD
CAPACITANCE
fmax
tPLH
tPHL
free-air
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
SN74LV594A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.5
0.8
V
Quiet output, minimum dynamic VOL
−0.1
−0.8
V
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
2.8
High-level dynamic input voltage
V
2.31
V
VIL(D)
Low-level dynamic input voltage
NOTE 5: Characteristics are for surface-mount packages only.
0.99
V
TYP
UNIT
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
f = 10 MHz
VCC
3.3 V
93
5V
112
pF
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SCLS413I − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
tPLH
50% VCC
VOH
50% VCC
VOL
VCC
Output
Control
50% VCC
0V
tPZL
Output
Waveform 1
S1 at VCC
(see Note B)
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
tPLZ
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jul-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
SN74LV594AD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ADBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ADBRE4
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ADBRG4
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ADE4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ADG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ADRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ADRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594ANSR
ACTIVE
SO
NS
16
TBD
Call TI
Call TI
Purchase Samples
SN74LV594ANSRE4
ACTIVE
SO
NS
16
TBD
Call TI
Call TI
Purchase Samples
SN74LV594ANSRG4
ACTIVE
SO
NS
16
Call TI
Call TI
Purchase Samples
SN74LV594APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594APWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594APWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594APWRE4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594APWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
TBD
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Jul-2010
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
SN74LV594APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594APWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
SN74LV594APWTG4
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LV594ADBR
Package Package Pins
Type Drawing
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DB
16
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74LV594ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV594APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV594APWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV594ADBR
SSOP
DB
16
2000
346.0
346.0
33.0
SN74LV594ADR
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV594APWR
TSSOP
PW
16
2000
346.0
346.0
29.0
SN74LV594APWT
TSSOP
PW
16
250
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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