SN74LV595A-Q1 www.ti.com SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 8-BIT SHIFT REGISTER WITH 3-STATE OUTPUT REGISTERS Check for Samples: SN74LV595A-Q1 FEATURES 1 • • • • • • • • • Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Voltage Operation on All Ports 8-Bit Serial-In, Parallel-Out Shift Ioff Supports Partial-Power-Down Mode Operation Shift Register Has Direct Clear QB QC QD QE QF QG QH GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH′ DESCRIPTION The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V VCC operation. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH' are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) TA (1) (2) PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C TSSOP − PW Reel of 2000 SN74LV595AIPWRQ1 LV595AI –40°C to 125°C TSSOP − PW Reel of 2000 SN74LV595AQPWRQ1 LV595AQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2009, Texas Instruments Incorporated SN74LV595A-Q1 SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 www.ti.com Table 1. FUNCTION TABLE INPUTS 2 FUNCTION SER SRCLK SRCLR RCLK OE X X X X H Outputs QA−QH are disabled. X X X X L Outputs QA−QH are enabled. X X L X X Shift register is cleared. L ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored in the storage register. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 SN74LV595A-Q1 www.ti.com SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 LOGIC DIAGRAM (POSITIVE LOGIC) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q 15 2D Q C2 R 3D C3 Q 1 2D Q C2 R 3D C3 Q 2 2D Q C2 R 3D C3 Q 3 2D Q C2 R 3D C3 Q 4 2D Q C2 R 3D C3 Q 5 2D Q C2 R 3D C3 Q 6 2D Q C2 R 3D C3 Q 7 QA QB QC 9 QD QE QF QG QH QH′ Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 3 SN74LV595A-Q1 SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 www.ti.com TIMING DIAGRAM SRCLK SER RCLK SRCLR OE QA QB QC QD QE QF QG QH QH′ 4 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 SN74LV595A-Q1 www.ti.com SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range VI Input voltage range (2) −0.5 V to 7 V −0.5 V to 7 V (2) −0.5 V to 7 V VO Voltage range applied to any output in the high-impedance or power-off state VO Output voltage range applied in the high or low state (2) IIK Input clamp current (2) VI < 0 –20 mA IOK Output clamp current (2) VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±35 mA (3) −0.5 V to VCC + 0.5 V Continuous current through VCC or GND ±70 mA θJA Package thermal impedance (4) 108°C/W Tstg Storage temperature range ESD (1) (2) (3) (4) −65°C to 150°C Electrostatic discharge rating Human-body model (HBM) 2000 V Machine model (MM) 200 V Charged-device model (CDM) 1000 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 2 V VIH High-level input voltage MIN MAX 2 5.5 Low-level input voltage VI VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VO Output voltage 0.5 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC = 4.5 V to 5.5 V VCC × 0.3 0 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 2 V IOH High level output current –50 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V Δt/Δv Input transition rise/fall time –8 50 VCC = 2.3 V to 2.7 V 2 VCC = 3 V to 3.6 V 8 VCC = 4.5 V to 5.5 V 16 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V TA (1) Operating free-air temperature V V µA mA –16 VCC = 2 V Low level output current V –2 VCC = 4.5 V to 5.5 V IOL V VCC = 2.3 V to 2.7 V Input voltage V 1.5 VCC = 2 V VIL UNIT µA mA ns/V 20 SN74LV595AIPWRQ1 –40 85 SN74LV595AQPWRQ1 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 5 SN74LV595A-Q1 SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS IOH = −50 μA 2 V to 5.5 V IOH = −2 mA 2.3 V QH′ IOH = −6 mA QA−QH IOH = −8 mA QH′ IOH = −12 mA QA−QH IOH = −16 mA 3V 4.5 V IOL = 50 μA 2 V to 5.5 V IOH = 2 mA 2.3 V QH′ IOH = 6 mA QA−QH IOH = 8 mA QH′ IOH = 12 mA QA−QH IOH = 16 mA II VCC TA = −40°C TO 85°C MIN TYP TA = −40°C TO 125°C MAX VCC – 0.1 MIN TYP MAX UNIT VCC – 0.1 2 2 2.48 2.45 2.48 2.45 3.8 3.7 3.8 V 3.7 3V 4.5 V 0.1 0.1 0.4 0.45 0.44 0.5 0.44 0.5 0.55 0.65 0.55 0.65 V VI = 5.5 V or GND 0 V to 5.5 V ±1 ±1 nA VO = VCC or GND 5.5 V ±5 ±10 µA ICC VI = VCC or GND, IO = 0 5.5 V 20 40 µA Ioff VI or VO = 0 to 5.5 V 0 5 (1) 10 µA Ci VI = VCC or GND IOZ (1) 6 QA−QH 3.3 V 3.5 3.5 pF Ioff does not apply to pin 9. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 SN74LV595A-Q1 www.ti.com SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 TIMING REQUIREMENTS over operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) TA = 25°C MIN tw Pulse duration Setup time th Hold time MAX MIN 7 7.5 8.5 RCLK high or low 7 7.5 8.5 SRCLR low 6 6.5 7.5 5.5 5.5 6.5 8 9 10 8.5 9.5 10.5 SRCLK↑ before RCLK↑ (1) SRCLR low before RCLK↑ SRCLR high (inactive) before SRCLK↑ (1) MIN TA = −40°C TO 125°C SRCLK high or low SER before SRCLK↑ tsu MAX TA = −40°C TO 85°C SER after SRCLK↑ 4 4 5 1.5 1.5 2.5 UNIT MAX ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. TIMING REQUIREMENTS over operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) TA = 25°C MIN tw Pulse duration th Hold time MIN 5.5 6.5 RCLK high or low 5.5 5.5 6.5 5 5 6 3.5 3.5 4.5 SRCLK↑ before RCLK↑ (1) 8 8.5 9.5 SRCLR low before RCLK↑ 8 9 10 SRCLR high (inactive) before SRCLK↑ (1) MAX 5.5 SER before SRCLK↑ Setup time MIN TA = −40°C TO 125°C SRCLK high or low SRCLR low tsu MAX TA = −40°C TO 85°C SER after SRCLK↑ 3 3 4 1.5 1.5 2.5 UNIT MAX ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. TIMING REQUIREMENTS over operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) TA = 25°C MIN tw Pulse duration Setup time (1) Hold time MAX MIN 5 5 RCLK high or low 5 5 6 5.2 5.2 6.2 SER before SRCLK↑ 3 3 4 SRCLK↑ before RCLK↑ (1) 5 5 6 SRCLR low before RCLK↑ 5 5 6 2.5 2.5 3.5 2 2 3 SRCLR high (inactive) before SRCLK↑ th MIN TA = −40°C TO 125°C SRCLK high or low SRCLR low tsu MAX TA = −40°C TO 85°C SER after SRCLK↑ UNIT MAX 6 ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 7 SN74LV595A-Q1 SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, CL = 50 pF (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ MIN 60 RCLK QA−QH SRCLK QH' SRCLR QH' OE QA−QH OE TA = −40°C TO 85°C TA = 25°C QA−QH TYP MAX 70 MIN MAX 40 TA = −40°C TO 125°C MIN UNIT MAX 30 MHz 11.2 17.2 1 19.3 1 22.3 ns 11.2 17.2 1 19.3 1 22.3 ns 13.1 22.5 1 25.5 1 28.5 ns 13.1 22.5 1 25.5 1 28.5 ns 12.4 18.8 1 21.1 1 24.1 ns 10.8 17 1 18.3 1 21.3 ns 13.4 21 1 23 1 26 ns 12.2 18.3 1 19.5 1 22.5 ns 14 20.9 1 22.6 1 25.6 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ RCLK QA−QH SRCLK QH' SRCLR QH' OE QA−QH OE TA = −40°C TO 85°C TA = 25°C MIN TYP 55 105 QA−QH MAX MIN MAX 50 TA = −40°C TO 125°C MIN UNIT MAX 40 MHz 7.9 15.4 1 17 1 20 ns 7.9 15.4 1 17 1 20 ns 9.2 16.5 1 18.5 1 21.5 ns 9.2 16.5 1 18.5 1 21.5 ns 9 16.3 1 17.2 1 20.2 ns 7.8 15 1 17 1 20 ns 9.6 15 1 17 1 20 ns 8.1 15.7 1 16.2 1 19.2 ns 9.3 15.7 1 16.2 1 19.2 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ 8 RCLK QA−QH SRCLK QH' SRCLR QH' OE QA−QH OE QA−QH TA = −40°C TO 85°C TA = 25°C MIN TYP 95 140 MAX MIN MAX 85 TA = −40°C TO 125°C MIN UNIT MAX 75 MHz 5.6 9.4 1 10.5 1 13.5 ns 5.6 9.4 1 10.5 1 13.5 ns 6.4 10.2 1 11.4 1 14.4 ns 6.4 10.2 1 11.4 1 14.4 ns 6.4 10 1 11.1 1 14.1 ns 5.7 10.6 1 12 1 15 ns 6.8 10.6 1 12 1 15 ns 3.5 10.3 1 11 1 14 ns 3.4 10.3 1 11 1 14 ns Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 SN74LV595A-Q1 www.ti.com SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 NOISE CHARACTERISTICS (1) VCC = 3.3 V, CL = 50 pF, TA = 25°C PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.3 V VOL(V) Quiet output, minimum dynamic VOL –0.2 V VOH(V) Quiet output, minimum dynamic VOH 2.8 V VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 2.31 V 0.99 V TYP UNIT Characteristics are for surface-mount packages only. OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz VCC = 3.3 V 111 VCC = 5 V 114 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 pF 9 SN74LV595A-Q1 SCLS539D – AUGUST 2003 – REVISED OCTOBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test RL = 1 kΩ From Output Under Test S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL VCC Output Control 50% VCC 0V tPZL Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC VOH 50% VCC VOL 50% VCC tPLZ ≈VCC 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LV595A-Q1 PACKAGE OPTION ADDENDUM www.ti.com 23-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV595AIPWRG4Q1 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV595AIPWRQ1 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74LV595AQPWRQ1 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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