STMICROELECTRONICS 74LVQ245TTR

74LVQ245
LOW VOLTAGE CMOS OCTAL BUS
TRANSCEIVER WITH (3-STATE)
■
■
■
■
■
■
■
■
■
■
■
HIGH SPEED:
tPD = 5.7 ns (TYP.) at VCC = 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
ICC = 5 µA (MAX.) at TA=25°C
LOW NOISE:
VOLP = 0.5V (TYP.) at VCC = 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ245 is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low power
and low noise 3.3V applications.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
T&R
SOP
TSSOP
74LVQ245MTR
74LVQ245TTR
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Impedance
State must be held HIGH or LOW.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
1/12
74LVQ245
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL
1
2, 3, 4, 5, 6,
7, 8,9
18, 17, 16,
15, 14, 13,
12, 11
19
10
20
DIR
A1 to A8
Directional Control
Data Inputs/Outputs
B1 to B8
Data Inputs/Outputs
G
GND
VCC
NAME AND FUNCTION
Output Enable Input
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
INPUTS
FUNCTION
OUTPUT
G
DIR
A BUS
B BUS
L
L
H
L
H
X
OUTPUT
INPUT
Z
INPUT
OUTPUT
Z
A=B
B=A
Z
X : Don‘t Care
Z : High Impedance
Table 4: Absolute Maximum Ratings
Symbol
VCC
VI
VI/O
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
DC Bus I/O Voltage (DIR, G)
-0.5 to VCC + 0.5
V
DC Bus I/O Voltage
-0.5 to VCC + 0.5
± 20
mA
V
IIK
DC Input Diode Current
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 50
mA
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
± 400
mA
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
Parameter
Value
Unit
VCC
Supply Voltage (note 1)
2 to 3.6
V
VI
Input Voltage (DIR, G)
0 to VCC
V
VO
DC Bus I/O Voltage
Top
Operating Temperature
dt/dv
Input Rise and Fall Time VCC = 3.0V (note 2)
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
2/12
0 to VCC
V
-55 to 125
°C
0 to 10
ns/V
74LVQ245
Table 6: DC Specifications
Test Condition
Symbol
VIH
VIL
VOH
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
TA = 25°C
VCC
(V)
Min.
Typ.
Max.
2.0
3.0 to
3.6
3.0
Value
Low Level Output
Voltage
3.0
-55 to 125°C
Min.
Min.
0.8
IO=-50 µA
2.9
IO=-12 mA
2.58
2.99
2.9
2.9
2.48
2.2
IO=50 µA
0.002
0.1
IO=12 mA
0
0.36
IOZ
ICC
IOLD
IOHD
Input Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
V
0.8
2.48
Unit
Max.
2.0
0.8
IO=24 mA
II
Max.
2.0
IO=-24 mA
VOL
-40 to 85°C
V
V
2.2
0.1
0.1
0.44
0.44
0.55
0.55
V
3.6
VI = VCC or GND
± 0.1
±1
±1
µA
3.6
VI = VIH or VIL
VO = VCC or GND
± 0.3
±3
± 10
µA
3.6
VI = VCC or GND
4
40
40
µA
3.6
VOLD = 0.8 V max
36
25
mA
VOHD = 2 V min
-25
-25
mA
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
VOLP
VOLV
VIHD
VILD
Parameter
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
Value
TA = 25°C
VCC
(V)
Min.
3.3
-0.8
3.3
Typ.
Max.
0.5
0.8
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
V
-0.5
2
V
CL = 50 pF
3.3
0.8
V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
3/12
74LVQ245
Table 8: AC Electrical Characteristics (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time
tPZL tPZH Output Enable
Time
tPLZ tPHZ Output Disable
Time
tOSLH
tOSHL
Output To Output
Skew Time
(note1, 2)
Value
TA = 25°C
VCC
(V)
Min.
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Max.
2.7
6.7
11.0
13.0
15.0
3.3(*)
2.7
5.7
9.0
10.5
12.0
9.3
15.0
17.5
20.0
3.3(*)
7.5
12.0
14.0
16.0
2.7
7.5
12.0
14.0
16.0
3.3(*)
6.6
10.0
11.5
13.0
2.7
0.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
(*)
3.3
Unit
ns
ns
ns
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
Min.
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
CIN
Input Capacitance
3.3
5
pF
CI/O
I/O Capacitance
3.3
10
pF
CPD
Power Dissipation
Capacitance (note
1)
3.3
20
pF
fIN = 10MHz
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
4/12
74LVQ245
Figure 3: Test Circuit
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
2VCC
tPZH, tPHZ
Open
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
5/12
74LVQ245
Figure 5: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)
6/12
74LVQ245
SO-20 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
inch
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.30
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.60
13.00
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10.00
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
k
0°
8°
0°
8°
ddd
0.100
0.004
0016022D
7/12
74LVQ245
TSSOP20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0˚
L
0.45
A
0.0256 BSC
0.60
8˚
0˚
0.75
0.018
8˚
0.024
0.030
A2
A1
b
K
e
L
E
c
D
E1
PIN 1 IDENTIFICATION
1
0087225C
8/12
74LVQ245
Tape & Reel SO-20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
30.4
0.519
1.197
Ao
10.8
11
0.425
0.433
Bo
13.2
13.4
0.520
0.528
Ko
3.1
3.3
0.122
0.130
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
9/12
74LVQ245
Tape & Reel TSSOP20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
MAX.
MIN.
330
13.2
TYP.
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
10/12
TYP
0.504
22.4
0.519
0.882
Ao
6.8
7
0.268
0.276
Bo
6.9
7.1
0.272
0.280
Ko
1.7
1.9
0.067
0.075
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
74LVQ245
Table 10: Revision History
Date
Revision
29-Jul-2004
5
Description of Changes
Ordering Codes Revision - pag. 1.
11/12
74LVQ245
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2004 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
12/12