DSILC6-4xx ESD Protection for high speed interface Main applications I/O3 VCC Where transient over-voltage protection in ESD sensitive equipment is required, such as: ■ ■ ■ ■ ■ I/O4 I/O2 GND I/O1 Computers Printers Communication systems Cell phone handsets and accessories Video equipment SOT-666 DSILC6-4P6 Flip-Chip DSILC6-4F2 Functional diagram Description I/O4 I/O3 VCC The DSILC6-4xx is a monolithic application specific discrete dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet, display and camera serial interfaces (LVDS). I/O1 The device is ideal for applications where both reduced printed circuit board space and power absorption capability are required. SOT-666 Top-side view Diode array topology ■ ■ ■ ■ 4 line protection 5 V VCC protection Very low capacitance: 1 pF typ. Lead-free pacakge RoHS compliant ■ ■ ■ ■ Very low capacitance between lines to GND for optimized data integrity Low PCB space consumption: 2.9 mm² max for SOT-666 and 1.5 mm² max for Flip-Chip Cut-off frequency > 2 GHz High reliability offered by monolithic integration MDDI, SMIA, MIPI specification compliant I/O2 I/O4 GND I/O3 Flip-Chip Top-side view I/O1 VCC I/O2 I/O4 GND I/O3 Flip-Chip Top-side view Order Code Benefits ■ VCC I/O2 GND Features ■ I/O1 Part Number Marking DSILC6-4P6 G DSILC6-4F2 EI Complies with the following standards: IEC 61000-4-2 level 4: 8 kV (contact discharge) 15 kV (air discharge) MIL STD 883G-Method 3015-7: class 3B May 2007 Rev 3 1/11 www.st.com 11 Characteristics DSILC6-4xx 1 Characteristics Table 1. Absolute ratings Symbol Parameter Value Unit 8 15 kV IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge VPP Peak pulse voltage IPP Peak pulse current PPP Peak pulse power Tstg Storage temperature range SOT-666 5 Flip-Chip 7 A I/O to GND Pulse waveform = 8/20 µs SOT-666 90 Flip-Chip 120 W -55 to +150 °C Tj Maximum junction temperature 125 °C TL Lead solder temperature (10 seconds duration) 260 °C Table 2. Electrical characteristics (Tamb = 25° C) Symbol Parameter VRM Reverse stand-off voltage IRM Leakage current VBR Breakdown voltage VF Forward voltage VCL Clamping voltage IPP Peak pulse current Value Symbol Parameter Test Conditions Unit Min IRM Leakage current VBR Breakdown voltage I = 1 mA between VBUS and GND R VF Forward voltage Capacitance between Ci/o-GND I/O and GND Ci/o-i/o Capacitance between I/O Typ VRM = 5 V 0.5 6 VI/O = 1.65 V, VCC = 4.3 V, F = 1 MHz, VOSC = 400 mV VI/O = 0 V, F = 1 MHz, VOSC = 30 mV VI/O = 1.65 V, VCC = 4.3 V, F = 1 MHz, VOSC = 400 mV 1 SOT-666 2 2.5 Flip-Chip 2.5 3 SOT-666 1.5 1.8 Flip-Chip 1.8 2.0 SOT-666 1.0 1.25 Flip-Chip 1.25 1.5 SOT-666 0.75 0.9 Flip-Chip 0.9 1.20 ΔCi/o-GND VI/O = 0 V, F = 1 MHz, VOSC = 30 mV 0.06 ΔCi/o-i/o VI/O = 0 V, F = 1 MHz, VOSC = 30 mV 0.05 2/11 µA V IF = 10 mA VI/O = 0 V, F = 1 MHz, VOSC = 30 mV Max V pF DSILC6-4xx Figure 1. Characteristics Figure 2. Relative variation of leakage current versus junction temperature - SOT-666 (typical values) IRM[Tj] / IRM[Tj=25°C] 100 100 Relative variation of leakage current versus junction temperature Flip-Chip (typical values) IRM[Tj] / IRM[Tj=25°C] VR = 5V VR = 5V 10 10 Tj(°C) Tj(°C) 1 1 50 100 125 25 50 Remaining voltage after Figure 4. DSILC6-4P6 during ESD 15 kV positive surge (air discharge) 10 V/div Figure 3. 75 100 125 Remaining voltage after DSILC6-4F2 during ESD 15 kV positive surge (air discharge) 50 ns/div 50 ns/div Remaining voltage after DSILC6-4F2 during ESD 15 kV negative surge (air discharge) 5 V/div Remaining voltage after Figure 6. DSILC6-4P6 during ESD 15 kV negative surge (air discharge) 5 V/div Figure 5. 75 10 V/div 25 50 ns/div 50 ns/div 3/11 Characteristics Figure 7. DSILC6-4xx Frequency responses of all lines DSILC6-4P6 Figure 8. S21(dB) 0.00 0.00 Frequency response of all lines DSILC6-4F2 S21 (dB) - 5.00 - 5.00 - 10.00 - 10.00 - 15.00 - 15.00 - 20.00 F(Hz) F (Hz) - 25.00 - 20.00 100.0k 1.0M 10.0M 100.0M Line 1 Line 3 Figure 9. 1.0M 1.0G 3.0M 10.0M Crosstalk results for lines 1/2 and 1/3 DSILC6-4P6 S21(dB) 0.00 - 20.00 - 20.00 - 40.00 - 40.00 - 60.00 - 60.00 - 80.00 - 80.00 - 100.00 - 100.00 1.0G 3.0G Line 2 Line 4 S21 (dB) - 120.00 - 120.00 F (Hz) F(Hz) - 140.00 1.0M Xtalk 1/2 4/11 100.0M 300.0M Figure 10. Crosstalk results for lines 1/2 and 1/3 DSILC6-4F2 0.00 - 140.00 100.0k 30.0M Line 1 Line 3 Line 2 Line 4 10.0M 100.0M Xtalk 1/3 1.0G 1.0M Xtalk 3.0M 1/2 10.0M 30.0M 100.0M 300.0M Xtalk 1/3 1.0G 3.0G DSILC6-4xx Application examples 2 Application examples 2.1 MDDI Lower Clamshell Hinge Upper Clamshell Analog Earpiece Audio Power Power DSILC6-4xx MDDI Data (Host) Data+ DataStrobe+ Strobe- MDDI Strobe (Host) Base band IC GND GND 2.2 MDDI Client & LCD Controller Chip (With Frame Buffer) PRIMARY LCD SECONDARY LCD SMIA DSILC6-4xx DATA1+ DATA1- CLOCK+ CLOCK- SMIA device SCL SDA ESDALC6V1P3 5/11 Application examples 2.3 DSILC6-4xx Ethernet 1 Gb +5V SMP75-8 BI_DA+ BI_DA- SMP75-8 BI_DB+ BI_DBDSILC6-4xx +5V DATA TRANSCEIVER DSILC6-4xx SMP75-8 BI_DC+ BI_DC- SMP75-8 BI_DD+ BI_DD- 2.4 USB 2.0 + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 + 5V SW1 VBUS TX LS/FS + TX LS/FS - D+ DRS USBLC6-2SC6 GND RS RS RS RPD + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 TX LS/FS - RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - D+ D- TX LS/FS + USBLC6-2P6 RS GND RS Mode SW1 SW2 Low Speed LS Open Closed Full Speed FS Closed Open High Speed HS Closed then open Open GND TX LS/FS + DSILC6-4xx RS RPD 6/11 TX LS/FS - RPD VBUS RS GND TX LS/FS + USB connector SW1 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND HUBDOWNSTREAM TRANSCEIVER VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND Protecting Bus Switch USB connector RPD TX LS/FS - DSILC6-4xx 3 Ordering information scheme Ordering information scheme DSI LC 6 - 4 xx Product Designation Low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 4 = 4 lines Packages P6 = SOT-666 F2 = Flip-Chip 7/11 Package information 4 DSILC6-4xx Package information ● Epoxy meets UL94, V0 Table 3. SOT-666 Dimensions Dimensions b1 Ref. Millimeters Inches L1 Min. L3 Typ. Max. Min. Typ. Max. A 0.45 0.60 0.018 0.024 A3 0.08 0.18 0.003 0.007 b 0.17 0.34 0.007 0.013 b1 0.19 D 1.50 1.70 0.059 0.067 E 1.50 1.70 0.059 0.067 E1 1.10 1.30 0.043 0.051 b D E1 0.27 0.34 0.007 0.011 0.013 A L2 E A3 e 0.50 0.020 L1 0.19 0.007 L2 0.10 0.30 0.004 0.012 e L3 Figure 11. SOT-666 footprint 0.10 0.004 Figure 12. SOT-666 marking 0.50 0.62 0.99 0.30 8/11 2.60 G DSILC6-4xx Package information Figure 13. Flip-Chip Dimensions 650 µm ± 65 1.57 mm ± 50µm 500 µm ± 50 500 µm ± 50 315 µm ± 50 1.1 mm ± 50 µm Figure 14. Flip-Chip footprint Figure 15. Flip-Chip marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter : 220µm recommended Solder stencil opening : 330µm recommended E x x z y ww Solder mask opening recommendation : 300µm recommended Figure 16. Flip-Chip tape and reel specifications Dot identifying Pin A1 location 3.5 +/- 0.1 ST E xxz yww ST E xxz yww ST E All dimensions in mm xxz yww 8 +/- 0.3 0.73 +/- 0.05 1.75 +/- 0.1 Ø 1.5 +/- 0.1 4 +/- 0.1 4 +/- 0.1 User direction of unreeling In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 9/11 Ordering information 5 6 Ordering information Ordering code Marking Package Weight Base qty Delivery mode DSILC6-4P6 G SOT-666 2.9 mg 3000 Tape and reel DSILC6-4F2 EI Flip-Chip 2.22 mg 5000 Tape and reel Revision history Date Revision 10-Aug-2006 1 Initial release. 04-Jan-2007 2 Added Flip-Chip package. Added applications examples for SMIA, Ethernet 1 Gb, and USB. Updated Tj max to 150. Added VRM line in Table 2. Modified MDDI example figure. 3 Modified Functional diagram on page 1 to show Top side view instead of Bump side view of DSILC64F2. Removed VRM line in Table 2. Added characteristic curves specific to each package for ESD, Frequency response and Crosstalk 28-May-2007 10/11 DSILC6-4xx Description of Changes DSILC6-4xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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