ESDA14V2-2BF3 Quad bidirectional Transil™ array for ESD protection Features ■ 2 bidirectional Transil functions ■ ESD protection: IEC 61000-4-2 level 4 ■ Stand off voltage: 12 V Min. ■ Low leakage current ■ Very small PCB area < 1.5 mm2 ■ 400 microns pitch Flip Chip (4 bumps) Complies with the following standards ■ ■ IEC 61000-4-2 – 15 kV (air discharge) – 8 kV (contact discharge) Figure 1. Pin layout (bump side) 2 1 MIL STD 883E- Method 3015-7: class 3 – 25 kV (human body model) A Applications B Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems and cellular phones ■ Video equipment Figure 2. Configuration 1 2 A Description The ESDA14V2-2BF3 is a monolithic array designed to protect 2 lines against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required. B This device is particularly adapted to the protection of symmetrical signals. TM: Transil is ASD a trademark of STMicroelectronics. April 2008 Rev 3 1/9 www.st.com Characteristics 1 ESDA14V2-2BF3 Characteristics Table 1. Absolute ratings (limiting values) Symbol Parameter ± 25 ± 15 ±8 kV MIL STD 883E - Method 3015-7 IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge ESD discharge PPP Peak pulse power (8/20µs) 50 W Junction temperature 125 °C -55 to +150 °C 260 °C -40 to +125 °C Tstg Storage temperature range TL Lead solder temperature (10 seconds duration) Top Operating temperature range Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current αT Voltage temperature coefficient C Capacitance I VCL VBR VRM Order code ESDA14V2-2BF3 V Slope: 1 / Rd VBR @ IR IPP IRM @ VRM Rd αT typ.(1) max.(2) max. 0 V bias max V V mA µA V Ω 10-4/C pF 14.2 18 1 0.5 0.1 12 3 3.2 6.5 12 Δ VBR = αT* (Tamb -25 °C) * VBR (25 °C) max. C min. 1. Square pulse, Ipp = 3 A, tp = 2.5 µs. 2/9 Unit VPP Tj 2. Value ESDA14V2-2BF3 Figure 3. Characteristics Relative variation of peak pulse power versus intial junction temperature Figure 4. Peak pulse power versus exponential pulse duration Ppp(W) Ppp[Tj initial] / Ppp [Tj initial=25°C] 1000 1.1 Tj initial = 25°C 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 Tj(°C) tp(µs) 0.0 10 0 25 Figure 5. 10.0 50 75 100 125 150 Clamping voltage versus peak pulse current (typical values, rectangular waveform) 1 10 Figure 6. 100 Junction capacitance versus reverse applied voltage (typical values) C(pF) IPP(A) 14 13 12 tp=2.5µs Tj initial =25°C F=1MHz VOSC=30mVRMS Tj=25°C 11 10 9 8 1.0 7 6 5 4 3 2 1 0 VCL(V) 0.1 0 10 20 30 40 50 60 VR(V) 0 2 4 6 8 10 12 14 3/9 Characteristics Figure 7. ESDA14V2-2BF3 Relative variation of leakage current versus junction temperature (typical values) Figure 8. Analog crosstalk measurement db IR [Tj ] / IR [Tj =25 °C] 100 0.00 -30.00 10 -60.00 -90.00 T j(°C) f (Hz) 1 25 Figure 9. 4/9 50 75 100 125 -120.00 100.0k 1.0M ESD response to IEC 61000-4-2 (+15 kV air discharge) 10.0M 100.0M 1.0G ESDA14V2-2BF3 Characteristics Figure 10. ESD response to IEC 61000-4-2 (-15 kV air discharge) Figure 11. Digital crosstalk measurement 5/9 Application information 2 ESDA14V2-2BF3 Application information Figure 12. Aplac model Ls Rs Rs Ls A1 A2 MODEL = D01 MODEL = D01 bu l k1 MODEL = D02 B1 B2 Lg nd Rgnd aplacvar Ls 150 p aplacvar Rs 60 m aplacvar Lgnd 290 p aplacvar Rgnd 250 m 3 Rgnd Model D01 BV=1 IBV=1 CJO=12.5 M=0.33 RS=0.3 VJ=0.6 TT=100 Lgnd Model D02 BV=1 IBV=1 CJO=250 M=0.33 RS=80m VJ=0.6 TT=100 Ordering information scheme Figure 13. Ordering information scheme ESDA ESD Array Breakdown Voltage 14V2 = 14.2 Volts min. Number of line 2 = 2 lines Type B = Bidirectional Package F = Flip Chip x = 3: Lead-free, pitch = 400 µm, bump height = 255 µm 6/9 14V2 - 2 B F3 ESDA14V2-2BF3 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 14. Package dimensions 255 µm ± 40 400 µm ± 40 605 µm ± 55 770 µm ± 30 185 µm ± 10 185 µm ± 10 400 µm ± 40 4 Package information 770 µm ± 30 Figure 15. Footprint Copper pad Diameter: 220 µm recommended 260 µm maximum Figure 16. Marking Dot xx = marking z = manufacturing location yww = datecode (y = year ww = week) Solder mask opening: 300 µm minimum Solder stencil opening: 220 µm recommended x x z y ww 7/9 Ordering information ESDA14V2-2BF3 Figure 17. Flip Chip tape and reel specifications Dot identifying Pin A1 location 3.5 ± 0.1 xxz yww 0.87 xxz yww xxz yww 8 ± 0.3 0.87 0.71 ± 0.05 4 ± 0.1 User direction of unreeling All dimensions in mm Note: 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 More information is available in the application note: AN2348 :"400 µm Flip Chip: Package description and recommendations for use" AN1751 : EMI Filters: Recommendations and measurements 5 Ordering information Table 3. 6 Order code Marking Package Weight Base qty Delivery mode ESDA14V2-2BF3 EG Flip Chip 0.79 mg 5000 Tape and reel 7” Revision history Table 4. 8/9 Ordering information Document revision history Date Revision Changes 02-Dec-2005 1 Initial release. 15-Dec-2005 2 Ordering information changed. 29-Apr-2008 3 Updated ECOPACK statement. Updated Figure 13 and Figure 17. Reformatted to current standards. ESDA14V2-2BF3 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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