STMICROELECTRONICS ESDALC6V1C2

ESDALC6V1C2
Quad low capacitance TRANSIL™ array for ESD protection
Applications
Where transient overvoltage protection in ESD
sensitive equipment is required, such as:
■
Computers
■
Printers
■
Communication systems and cellular phones
■
Video equipment
This device is particularly adapted to the
protection of symmetrical signals
Coated lead free Flip-Chip
(5 bumps)
Functional diagram
A1
Features
■
4 unidirectional TRANSIL functions.
■
Breakdown voltage VBR = 6.1 V min.
– Low diode capacitance (12 pF @ 0 V)
– Low leakage current (< 500 nA @ 3 V)
– very small PCB area (1.33 mm2)
■
A3
C1
C3
B2
Coated lead free package
A B C
Benefits
1
■
High ESD protection level
■
High integration
2
■
Suitable for high density boards
3
Description
The ESDALC6V1C2 is a monolithic array
designed to protect up to 4 lines againast ESD
transients. The device is ideal for applications
where both reduced line capacitance and board
space saving are required.
Order code
Part number
Marking
ESDALC6V1C2
ED
Complies with the following standards:
IEC 61000-4-2
15 kV (air discharge)
8 kV (contact discharge)
TM: TRANSIL is a trademark of STMicroelectronics
MIL STD 883E - Method 3015-7: class 3
25 kV (Human body model)
August 2006
Rev 1
1/7
www.st.com
Characteristics
ESDALC6V1C2
1
Characteristics
Table 1.
Absolute maximum ratings (Tamb = 25° C)
Symbol
Parameter
IEC 61000-4-2 air discharge
IEC 61000-4-2 contact discharge
VPP
ESD discharge
PPP
Peak pulse power dissipation (8/20 µs. (1)
Tj initial = Tamb
Value
Unit
± 15
±8
kV
25
W
Tj
Junction temperature
125
°C
Tstg
Storage temperature
- 55 to +150
°C
260
°C
- 40 to + 125
°C
Value
Unit
150
°C/W
TL
TOP
Maximum lead temperature for soldering during 10 s at 5 mm for case
Operating temperature range
1. For a surge greater than the maximum values, the diode will fail in short-circuit
Table 2.
Thermal resistance
Synbol
Rth(j-a)
Table 3.
Parameter
Junction to ambient on printed circuit on recommended pad layout
Electrical characteristics
Symbol
Parameter
VRM
Stand-of voltage
VBR
Breakdown voltage
VCL
Clamping voltage
IRM
Leakage current @ VRM
IPP
Peak pulse current
αT
Voltage temperature coefficient
VF
Forward voltage drop
IRM @ VRM
VBR @ IR
RD
αT
C
Type
ESDALC6V1C2
2/7
µA max
V
Vmin
Vmax
mA
Typ
0.5
3
6.1
7.2
1
1
10-4/°C max pFtyp @0 V
5
12
ESDALC6V1C2
Figure 1.
Characteristics
Peak power dissipation versus
initial junction temperature
Figure 2.
PPP[T j initial] / PPP [T j initial=25°C]
PPP(W)
1000
1.1
Peak pulse power versus
exponential pulse duration
(Tj initial = 25°C)
1.0
0.9
0.8
0.7
0.6
100
0.5
0.4
0.3
0.2
0.1
tP(µs)
T j(°C)
0.0
10
0
25
Figure 3.
100.0
50
75
100
125
150
Clamping voltage versus peak
pulse current (Tj initial = 25°C),
rectangular waveform tp = 2.5 µs).
Figure 4.
IPP(A)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10.0
1.0
VCL(V)
0.1
0
5
Figure 5.
1.E+04
1
10
15
20
25
30
35
40
45
50
10
100
Capacitance versus reverse applied
voltage (typical values)
C(pF)
VR(V)
0
1
2
3
4
5
6
Relative variation of the leakage
current versus junction
temperature (typical values)
IR [T j] / IR [T j=25°C]
1.E+03
1.E+02
1.E+01
T j(°C)
1.E+00
25
50
75
100
125
3/7
Ordering information scheme
2
ESDALC6V1C2
Ordering information scheme
ESDA
LC
-
6V1
ESD Array
Low capacitance
VBR min = 6.1 V
Package
C = Coated Flip-Chip
2 = Leadfree Pitch = 500µm, Bump = 315µm
3
Package information
Figure 6.
Flip-Chip dimensions
500 µm ± 10
15
±
µm
0
50
0.95 mm ± 50µm
4/7
315 µm ± 50
1.32 mm ± 50µm
250 µm ± 10
695 µm ± 65
C2
ESDALC6V1C2
Ordering information
Figure 7.
Flip-Chip footprint
Figure 8.
Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year ww = week)
Copper pad Diameter :
250µm recommended , 300µm max
E
Solder stencil opening : 330µm
x x z
y ww
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
Figure 9.
Flip-Chip tape and reel specifications
Dot identifying Pin A1 location
Ø 1.5 ± 0.1
1.75 ± 0.1
ST E
ST E
ST E
xxz
yww
xxz
yww
xxz
yww
0.73 ± 0.05
3.5 ± 0.1
8 ± 0.3
4 ± 0.1
4 ± 0.1
User direction of unreeling
All dimensions in mm
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
4
Ordering information
Part number
Marking
Package
Weight
Base qty
Delivery mode
ESDALC6V1C2
ED
Flip-Chip
2.1 mg
5000
Tape and reel
5/7
Revision history
5
6/7
ESDALC6V1C2
Revision history
Date
Revision
07-Aug-2006
1
Changes
Initial release.
ESDALC6V1C2
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