ESDALC6V1F2 Quad low capacitance Transil™ array for ESD protection Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems and cellular phones ■ Video equipment This device is particularly adapted to the protection of symmetrical signals Lead free Flip-Chip (5 bumps) Figure 1. Functional diagram A1 A3 C1 C3 Features ■ 4 unidirectional Transil functions. ■ Breakdown voltage VBR = 6.1 V min. – Low diode capacitance (12 pF @ 0 V) – Low leakage current (< 500 nA @ 3 V) – very small PCB area (1.25 mm2) ■ B2 Lead free package A Benefits ■ High ESD protection level ■ High integration ■ Suitable for high density boards B C 1 2 3 Description The ESDALC6V1F2 is a monolithic array designed to protect up to 4 lines againast ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required. Table 1. Order code Part number Marking ESDALC6V1F2 ED Complies with the following standards: IEC 61000-4-2 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883E - Method 3015-7: class 3 TM: Transil is a trademark of STMicroelectronics July 2007 25 kV (Human body model) Rev 2 1/7 www.st.com Characteristics ESDALC6V1F2 1 Characteristics Table 2. Absolute maximum ratings (Tamb )= 25° C Symbol Parameter IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge VPP ESD discharge PPP Peak pulse power dissipation (8/20 µs). (1) Tj initial = Tamb Value Unit ± 15 ±8 kV 25 W Tj Junction temperature 125 °C Tstg Storage temperature - 55 to +150 °C 260 °C - 40 to + 125 °C Value Unit 150 °C/W TL TOP Maximum lead temperature for soldering during 10 s at 5 mm for case Operating temperature range 1. For a surge greater than the maximum values, the diode will fail in short-circuit Table 3. Thermal resistance Synbol Rth(j-a) Table 4. Parameter Junction to ambient on printed circuit on recommended pad layout Electrical characteristics Symbol Parameter VRM Stand-of voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current @ VRM IPP Peak pulse current αT Voltage temperature coefficient VF Forward voltage drop IRM @ VRM VBR @ IR RD αT C Type ESDALC6V1F2 2/7 µA max V Vmin Vmax mA Typ 0.5 3 6.1 7.2 1 1 10-4/°C max pFtyp @0 V 5 12 ESDALC6V1F2 Figure 2. Characteristics Peak power dissipation versus initial junction temperature Figure 3. PPP[T j initial] / PPP [T j initial=25°C] PPP(W) 1000 1.1 Peak pulse power versus exponential pulse duration (Tj initial = 25° C) 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 tP(µs) T j(°C) 0.0 10 0 25 Figure 4. 100.0 50 75 100 125 150 Clamping voltage versus peak pulse current (Tj initial = 25° C), rectangular waveform tp = 2.5 µs). Figure 5. IPP(A) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10.0 1.0 VCL(V) 0.1 0 5 Figure 6. 1.E+04 1 10 15 20 25 30 35 40 45 50 10 100 Capacitance versus reverse applied voltage (typical values) C(pF) VR(V) 0 1 2 3 4 5 6 Relative variation of the leakage current versus junction temperature (typical values) IR [T j] / IR [T j=25°C] 1.E+03 1.E+02 1.E+01 T j(°C) 1.E+00 25 50 75 100 125 3/7 Ordering information scheme 2 ESDALC6V1F2 Ordering information scheme Figure 7. Ordering information scheme ESDA ESD Array Low capacitance VBR min = 6.1 V Package F = Flip-Chip 2 = Leadfree Pitch = 500 µm, Bump = 315 µm 4/7 LC - 6V1 F2 ESDALC6V1F2 Package information Figure 8. Flip-Chip dimensions 500 µm ± 10 315 µm ± 50 650 µm ± 50 µm ± 15 1.32 mm ± 50 µm 250 µm ± 10 50 0 3 Package information 0.95 mm ± 50 µm Figure 9. Flip-Chip footprint Copper pad Diameter : 250µm recommended , 300µm max Solder stencil opening : 330µm Solder mask opening recommendation : 340µm min for 315µm copper pad diameter Figure 10. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) E x x z y ww 5/7 Ordering information ESDALC6V1F2 Figure 11. Flip-Chip tape and reel specifications Dot identifying Pin A1 location Ø 1.5 ± 0.1 1.75 ± 0.1 ST E ST E ST E xxz yww xxz yww xxz yww 0.73 ± 0.05 3.5 ± 0.1 8 ± 0.3 4 ± 0.1 4 ± 0.1 User direction of unreeling All dimensions in mm In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 4 Ordering information Table 5. 5 Part number Marking Package Weight Base qty Delivery mode ESDALC6V1F2 ED Flip-Chip 2.1 mg 5000 Tape and reel Revision history Table 6. 6/7 Ordering information Revision history Date Revision Changes 07-Aug-2006 1 Initial release. 11-Jul-2007 2 Updated marking from EDT to ED. ESDALC6V1F2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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