USBLC6-4 Very low capacitance ESD protection Features ■ 4 data lines protection Protects VBUS ■ Very low capacitance: 3 pF typ. ■ SOT23-6L package ■ RoHS compliant ■ Benefits ■ ■ ■ ■ ■ ■ Very low capacitance between lines to GND for optimized data integrity and speed Low PCB space consumption, 9 mm² maximum foot print Enhanced ESD protection. IEC 61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level ESD protection of VBUS. Allows ESD current flowing to Ground when ESD event occurs on data line High reliability offered by monolithic integration Low leakage current for longer operation of battery powered devices ■ Fast response time ■ Consistent D+ / D- signal balance: – Best capacitance matching tolerance I/O to GND = 0.015 pF – Compliant with USB 2.0 requirements < 1 pF Complies with the following standards ■ IEC 61000-4-2 level 4: – 15 kV (air discharge) – 8 kV (contact discharge) February 2008 SOT23-6L Applications ■ ■ ■ ■ ■ ■ USB 2.0 ports up to 480 Mb/s (high speed) Backwards compatible with USB 1.1 low and full speed Ethernet port: 10/100 Mb/s SIM card protection Video line protection Portable electronics Description The USBLC6-4SC6 is a monolithic application specific device dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet links and video lines. Its very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringent characterized ESD strikes. Figure 1. Rev 3 Functional diagram I/O1 1 1 6 I/O4 GND 2 5 VBUS I/O2 3 4 I/O3 1/13 www.st.com 13 Characteristics 1 USBLC6-4 Characteristics Table 1. Absolute ratings Symbol Parameter IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge MIL STD883C-Method 3015-6 Value Unit 15 15 25 kV VPP Peak pulse voltage Tstg Storage temperature range -55 to +150 °C Tj Operating junction temperature range -40 to +125 °C TL Lead solder temperature (10 seconds duration) 260 °C Table 2. Electrical characteristics (Tamb = 25 °C) Value Symbol Parameter Test Conditions Unit Min. VRM Reverse stand-off voltage IRM Leakage current VRM = 5 V VBR Breakdown voltage between VBUS and GND IR = 1 mA Forward voltage IF = 10 mA VF VCL Ci/o-GND ΔCi/o-i/o 2/13 10 Max. 5 V 150 nA 6 V 0.86 V IPP = 1 A, 8/20 µs Any I/O pin to GND 12 V IPP = 5 A, 8/20 µs Any I/O pin to GND 17 V Clamping voltage Capacitance between I/O and GND VR = 1.65 V ΔCi/o-GND Ci/o-i/o Typ. 3 4 pF 0.015 Capacitance between I/O VR = 1.65 V 1.85 2.7 pF 0.04 USBLC6-4 Figure 2. Characteristics Capacitance versus voltage (typical values) Figure 3. Line capacitance versus frequency (typical values) C(pF) C(pF) 5.0 5.0 F=1MHz VOSC=30mVRMS Tj=25°C 4.5 4.0 VOSC=30mVRMS Tj=25°C 4.5 VCC=0V 4.0 3.5 3.5 CO=I/O-GND VCC=1.65V 3.0 3.0 2.5 2.5 Cj=I/O-I/O 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 Data line voltage (V) 0.0 F(MHz) 0.0 0.0 0.5 Figure 4. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Relative variation of leakage current versus junction temperature (typical values) 1 10 Figure 5. IRM[Tj] / IRM[Tj=25°C] 0.00 100 100 1000 Frequency response S21(dB) VBUS=5V -5.00 -10.00 10 -15.00 F(Hz) Tj(°C) 1 -20.00 25 50 75 100 125 100.0k 1.0M 10.0M 100.0M 1.0G 3/13 Technical information 2 Technical information 2.1 Surge protection USBLC6-4 The USBLC6-4SC6 is particularly optimized to provide surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follows: VCL+ = VTRANSIL + VF for positive surges VCL- = - VF for negative surges with: VF = VT + Rd.Ip (VF forward drop voltage, VT forward drop threshold voltage Calculation example We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5 Ω and VT = 1.1 V. For an IEC 61000-4-2 surge level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 Ω), VBUS = +5 V, and if in a first approximation, we assume that: Ip = Vg / Rg = 24 A. So, we find: VCL+ = +31.2 V VCL- = -13.1 V Note: The calculations do not take into account phenomena due to parasitic inductances. 2.2 Surge protection application example If we consider that the connections from the pin VBUS to VCC, from from I/O to data line and from GND to PCB GND plane are implemented as racks 10 mm long and 0.5 mm large, we can assume that the parasitic inductances LVBUS LI/0 and LGND of these tracks are about 6 nH. So, when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to LI/0·dI/dt, + LGND·dI/dt The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The overvoltage due to the parasitic inductances is: LI/0·dI/dt, = LGND·dI/dt = 6 x 24 = 144 V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: VCL+ = +31.2 + 144 + 144 = 319.2 V VCL- = -13.1 - 144 -144 = -301.1 V We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some recommendations have to be followed (see 2.3: How to ensure good ESD protection). 4/13 USBLC6-4 Technical information Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout ESD sur ge on data line VCL+ VBUS Data line L I/O di dt L I/O L I/O di + L GND di dt dt L VBUS Positive Sur ge VCC pin VF VTRANSIL I/O pin VTRANSIL + VF VCL t t r = 1 ns GND pin t r = 1 ns L GND L GND di dt t - VF VCL + = VTRANSIL + VF + L I/O di + L GND di dt dt sur ge > 0 VCL- = -VF - L I/O di - L GND di dt dt sur ge > 0 Negative Sur ge -L I/O di - L GND di dt dt V TRANSIL = VBR + Rd.Ip VCL- 2.3 How to ensure good ESD protection While the USBLC6-4SC6 provides high immunity to ESD surge, efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to the VBUS pin and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see Figure 7 and Figure 8 for layout considerations) Figure 7. ESD behavior: optimized layout and Figure 8. addition of a capacitance of 100 nF ESD behavior: measurement conditions (with coupling capacitance) ESD SURGE TEST BOARD Unsuitable layout IN OUT USBLC6-4SC6 Vbus Optimized layout 5/13 Technical information USBLC6-4 Figure 9. Remaining voltage after the Figure 10. Remaining voltage after the USBLC6-4SC6 during positive ESD USBLC6-4SC6 during negative ESD surge surge Note: The measurements have been done with the USBLC6-4SC6 in open circuit. Important: A good precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector). 2.4 Crosstalk behavior 2.4.1 Crosstalk phenomenon Figure 11. Crosstalk phenomenon RG1 Line 1 VG1 RL1 RG2 VG2 Line 2 RL2 DRIVERS α 1 VG1 + β12VG2 α 2VG2 + β21VG1 RECEIVERS The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). 6/13 USBLC6-4 Technical information Figure 12. Analog crosstalk measurements USBLC6-4SC6 TEST BOARD NETWORK ANALYSER PORT 1 NETWORK ANALYSER PORT 2 Vbus Figure 12. shows the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 db ( see Figure 13.). Figure 13. Analog crosstalk results 0.00 dB - 30.00 - 60.00 - 90.00 F (Hz) - 120.00 100.0k 1.0M 10.0M f/Hz 100.0M 1.0G As the USBLC6-4SC6 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (Figure 5.) gives attenuation information and shows that the USBLC6-4SC6 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies, for instance. 7/13 Technical information 2.5 USBLC6-4 Application examples Figure 14. USB 2.0 port application diagram using USBLC6-4SC6 + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 + 5V USB connector SW1 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS - Protecting Bus Switch VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - VBUS D+ DRS USBLC6-2SC6 GND RS RS RS RPD + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 TX LS/FS - RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - D+ DRS USBLC6-2P6 GND RS USBLC6-4SC6 RS Mode SW1 SW2 Low Speed LS Open Closed Full Speed FS Closed Open High Speed HS Closed then open Open RS Figure 15. T1/E1/Ethernet protection Tx 100nF Rx SMP75-8 USBLC6-4SC6 SMP75-8 +VCC GND TX LS/FS + RPD 8/13 TX LS/FS - RPD VBUS TX LS/FS + GND TX LS/FS + USB connector SW1 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND HUBDOWNSTREAM TRANSCEIVER DATA TRANSCEIVER RPD TX LS/FS - USBLC6-4 2.6 Technical information PSPICE model Figure 16. shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes are defined by the PSPICE parameters given in Figure 17. Figure 16. PSPICE model MODEL = Dlow LIO MODEL = Dhigh RIO RIO io1 LIO io4 MODEL = Dlow LGND RGND MODEL = Dhigh MODEL = Dzener RIO LIO GND VBUS MODEL = Dlow LIO MODEL = Dhigh RIO RIO io2 LIO io3 MODEL = Dlow Note: MODEL = Dhigh This simulation model is available only for an ambient temperature of 27 °C. Figure 17. PSPICE parameters Dlow Dhigh BV 50 50 7.3 CJ0 2.4p 2.4p 20p Figure 18. USBLC6-4SC6 PCB layout considerations Dzener IBV 1m 1m 1m IKF 0.038 0.018 2.42 IS 55.2p 2.27f 3.21p ISR 100p 100p 100p N 1.62 1.13 1.24 M 0.3333 0.3333 0.3333 RS 0.38 0.63 0.42 VJ 0.6 0.6 0.6 TT 0.1u 0.1u 0.1u D+1 LIO 710p D-1 RIO 100m GND LGND 430p D+2 RGND 50m D-2 1 VBUS CBUS = 100nF USBLC6-4SC6 9/13 Ordering information scheme 3 USBLC6-4 Ordering information scheme Figure 19. Ordering information scheme USB Product Designation Low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 4 = 4 lines Package SC6 = SOT23-6L 10/13 LC 6 - 4 SC6 USBLC6-4 4 Package information Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. SOT23-6L dimensions Dimensions REF. A E Millimeters Min. e b D e A2 Typ. Max. Inches Min. Typ. Max. A 0.90 A1 0 A2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.014 0.02 C 0.09 0.20 0.004 0.008 D 2.80 3.05 0.110 0.120 E 1.50 1.75 0.059 0.069 e 1.45 0.035 0.057 0.10 0.004 0 0.95 0.037 A1 c θ L H Figure 20. SOT23-6L footprint (mm) H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 θ 0° 10° 0° 10° Figure 21. SOT23-6L marking 0.60 1.20 e3 3.50 2.30 0.95 1.10 x x x z y ww e3: ECOPACK (Leadfree) XXX: Marking Z: Manufacturing location Y: Year WW: week 11/13 Ordering information 5 Ordering information Table 4. 6 USBLC6-4 Ordering information Ordering code Marking Package Weight Base qty Delivery mode USBLC6-4SC6 UL46 SOT23-6L 16.7 mg 3000 Tape and reel Revision history Table 5. Document revision history Date Revision 10-Dec-2004 1 First issue. 28-Feb-2005 2 Minor layout update. No content change. 3 Updated operating junction temperature range in absolute ratings, page 2. Updated Section 2: Technical information. Updated marking illustration Figure 21. Reformatted to current standard. 04-Feb-2008 12/13 Description of changes USBLC6-4 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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