EMIF06-VID01C2 IPAD™ 6 line low capacitance EMI filter and ESD protection Main application Where EMI filtering in ESD sensitive equipment is required: ■ ■ ■ ■ LCD and camera for mobile phones Computers and printers Communication systems MCU board ® Lead free coated Flip-Chip (15 Bumps) Description The EMIF06-VID01C2 is a 6 line highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The Flip-Chip packaging means the package size is equal to the die size. Order code This filter includes ESD protection circuitry, which prevents damage to the application when it is subjected to ESD surges up to 15 kV. Part Number Marking EMIF06-VID01C2 GR Pin identities (bump side) Benefits ■ ■ ■ ■ ■ ■ ■ ■ ■ High efficiency EMI filtering (-40db @ 900MHz) Low line capacitance suitable for high speed data bus Low serial resistance for camera impedance adaptation Optimized PCB space consuming: 2.92mm x 1.29mm Very thin package: 0.69 mm High efficiency in ESD suppression on inputs pins (IEC61000-4-2 level 4) High reliability offered by monolithic integration High reducing of parasitic elements through integration and wafer level packaging Lead free package 9 8 I6 7 6 I5 I4 Gnd O6 5 4 3 I3 I2 Gnd O5 O4 O3 2 1 I1 Gnd O2 A B O1 C Circuit configuration R Input Output Complies with the following standards: IEC 61000-4-2 level 4 input pins 15 kV (air discharge) 8 kV (contact discharge R = 100Ω CLINE = 16pF typ. @ 3V MIL STD 883E - Method 3015-6 Class 3 June 2006 Rev 2 1/7 www.st.com 7 Characteristics 1 EMIF06-VID01C2 Characteristics Table 1. Absolute Ratings (limiting values) Symbol Parameter and test conditions Maximum junction temperature Tj Unit 125 °C Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to + 150 °C Table 2. Electrical Characteristics (Tamb = 25° C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM I VBR VRM IR IRM VRM Stand-off voltage IRM IR R Series resistance between Input and Output Cline Input capacitance per line Symbol Test conditions VBR IR = 1 mA IRM VRM = 3 V per line R Cline 2/7 Value I = 10 mA VR = 3 V DC 1 MHz VOSC = 30 mV VRM VBR V Min. Typ. Max. Unit 6 8 10 V 500 nA 100 120 Ω 16 19 pF 80 EMIF06-VID01C2 Figure 1. Characteristics S21 (db) attenuation measurement Figure 2. 0 Analog crosstalk measurement 0 dB dB -10 -10 -20 -30 -20 -40 -30 -50 -60 -40 -70 -80 -50 -90 -100 -60 100k 1M 10M 100M 100k 1G Figure 3. 1M 10M 100M 1G f/Hz f/Hz ESD response to IEC 61000-4-2 (+15kV air discharge) on one input (Vin) and on one output (Vout) Figure 4. ESD response to IEC 61000-4-2 (-15kV air discharge) on one input (Vin) and on one output (Vout) Input 10V/d Input 10V/d Output 10V/d Output 10V/d 200ns/d Figure 5. 200ns/d Junction capacitance versus reverse voltage applied (typical values) CLINE(pF) 28 26 24 22 20 18 16 14 12 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VLINE(V) 3/7 Ordering information scheme 2 EMIF06-VID01C2 Ordering information scheme EMIF yy - xxx zz Cx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package C = Coated Flip-Chip x = 1: 500µm, Bump = 315µm = 2: Leadfree Pitch = 500µm, Bump = 315µm 3 Package information Figure 6. Flip-Chip Dimensions 435µm ± 50 315µm ± 50 500µm ± 50 0 ±5 m 50 1µ 2.92mm ± 50µm 4/7 690µm ± 65 1.29mm ± 50µm 250µm ± 50 EMIF06-VID01C2 Package information Figure 7. Footprint recommendations Figure 8. Marking Dot, ST logo xx = marking z = manufacturing location yww = date code (y = year ww = week) Copper pad Diameter : 250µm recommended , 300µm max E Solder stencil opening : 330µm x x z y w w Solder mask opening recommendation : 340µm min for 300µm copper pad diameter Figure 9. Flip-Chip Tape and reel specifications Dot identifying Pin A1 location Ø 1.5 +/- 0.1 3.5 +/- 0.1 ST E xxx yww ST E xxx yww ST E All dimensions in mm xxx yww 8 +/- 0.3 0.78 +/- 0.05 1.75 +/- 0.1 4 +/- 0.1 4 +/- 0.1 User direction of unreeling In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Note: More packing informations are available in the application note AN1235: “Flip-Chip: Package description and recommendations for use” AN1751: “EMI Filters: Recommendations and measurements” 5/7 Ordering information 4 5 6/7 EMIF06-VID01C2 Ordering information Ordering code Marking Package Weight Base qty Delivery mode EMIF06-VID01C2 GR Flip-Chip 5.9 mg 5000 Tape and reel 7” Revision history Date Revision Changes 12-Aug-2005 1 First issue. 01-Jun-2006 2 Reformatted to current standards. Modified marking illustration to remove dimensions. Depth dimension changed in Figure 9. EMIF06-VID01C2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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