EMIF10-LCD03F3 10-line IPAD™, EMI filter and ESD protection Features ■ High attenuation in the mobile frequency range (typically better than -40 dB from 900 MHz to 2 GHz) ■ Very low clamping voltage ■ Low line capacitance (30 pF max) suitable for high-speed interfaces ■ Maximum rise and fall time: 6 ns (10% - 90%) ■ Compliant with high speed data rate ■ Lead-free Flip Chip package in 400 µm pitch ■ Very thin package: 0.6mm thickness Benefits ■ High efficiency in EMI filtering ■ High bandwidth: typically 200 MHz at -3 dB ■ 80% space saving versus discrete solution (BOM reduction) ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging Flip Chip (24 bumps) Description The EMIF10-LCD03F3 is a 10-line highly integrated LC filter designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF10 Flip Chip packaging means the package size is equal to the die size. This LC filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up ±15 kV. Figure 1. Pin layout (bump side) 5 4 3 2 1 O1 O2 GND I1 I2 A Complies with the following standards O3 O4 I3 I4 B ■ O5 O6 GND I5 I6 C O7 O8 GND I7 I8 D O9 O10 GND I9 I10 E IEC61000-4-2 level 4 on inputs and outputs – ±15 kV (air discharge) – ± 8 kV (contact discharge) Applications Figure 2. Device configuration Displays and cameras where outstanding EMI filtering in ESD sensitive equipment is required: ■ Mobile phones and PDAs ■ Personal and home entertainment (portable audio, DVD players, LCD TVs) ■ Portable navigation devices ■ Digital still cameras ■ Low-pass Filter 0000 Input GND GND Output GND Ri/o = 125 Ω ±20% Cline = 30 pF max Portable gaming systems TM: IPAD is a trademark of STMicroelectronics. April 2008 Rev 1 1/7 www.st.com 7 Characteristics 1 EMIF10-LCD03F3 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol VPP Tj Parameter Value Unit Input and output pins: ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge ± 15 ± 15 kV Maximum junction temperature 125 °C Top Operating temperature range -40 to +85 °C Tstg Storage temperature range -55 to 150 °C Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameters VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between Input & Output Cline Line capacitance IF Symbol 2/7 I VF VCL VBR VRM Test conditions VBR IR = 1 mA IRM VRM = 3 V per line RI/O Tolerance ± 20% Cline Vline = 0 V, VOSC = 30 mV, F =1 MHz V IRM IR IPP Min Typ Max 14 100 Unit V 125 200 nA 150 Ω 30 pF EMIF10-LCD03F3 Figure 3. 0.00 Characteristics S21 measurement (all GND bumps connected) Figure 4. dB 0.00 Analog crosstalk measurements (all GND bumps connected) dB -10.00 -10.00 -20.00 -20.00 -30.00 -40.00 -30.00 -50.00 -40.00 -60.00 -70.00 -50.00 -80.00 -90.00 -60.00 -100.00 -70.00 -110.00 F (Hz) -120.00 -80.00 100.0k 1.0M 10.0M 100.0M I1-O1 I3-O3 I5-O5 I7-O7 I9-O9 F (Hz) -130.00 1.0G -140.00 I2-O2 I4-O4 I6-O6 I8-O8 I10-O10 100.0k 1.0M I1-O2 Figure 5. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one line Figure 7. Line capacitance versus applied voltage (typical values) 30 Figure 6. 10.0M 100.0M I1-O10 1.0G ESD response to IEC 61000-4-2 (-15 kV air discharge) on one line Cline (pF) F=1 MHz VOSC = 30 mVRMS TJ = 25° C 25 20 15 10 5 Vline (V) 0 0 1 2 3 4 5 3/7 Ordering information scheme Figure 8. EMIF10-LCD03F3 Typical rise and fall time: input voltage Figure 9. Typical rise and fall time: output voltage OUTPUT VOLTAGE X: 10ns/DIV Y: 1V/DIV Trise10% -90% = 3.45 ns Tfall 90%-10% = 4.09 ns INPUT VOLTAGE X: 10 ns/DIV Y: 1 V/DIV 2 Ordering information scheme Figure 10. Ordering information scheme EMIF EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10 (pF) or 3 letters = application 2 digits = version Package F = Flip Chip 3 = Lead-free, pitch = 400 µm 4/7 yy - xxx zz F3 EMIF10-LCD03F3 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 11. Package dimensions Figure 12. Footprint Copper pad Diameter: 220 µm recommended 260 µm maximum Solder mask opening: 300 µm minimum Solder stencil opening: 220 µm recommended 255 µm± 40 605 µm ± 55 2.08 mm ± 30 µm 400 µm ± 40 400 µm ± 40 190 µm ± 10 240 µm ± 10 3 Package information 1.98 mm ± 30 µm Figure 13. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) E x x z y ww 5/7 Ordering information EMIF10-LCD03F3 Figure 14. Flip Chip tape and reel specification Dot identifying Pin A1 location 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 3.5 ± 0.1 2.13 ST E xxz yww 4 ± 0.1 User direction of unreeling All dimensions in mm Note: 2.22 ST E xxz yww ST E xxz yww 8 ± 0.3 0.69 ± 0.05 More information is available in the application notes: AN2348: “STMicroelectronics 400 micro-metre Flip Chip: Package description and recommendation for use” AN1751: "EMI Filters: Recommendations and measurements" 4 Ordering information Table 3. 5 Order code Marking Package Weight Base qty Delivery mode EMIF10-LCD03F3 HI Flip Chip 5.3 mg 5000 Tape and reel 7” Revision history Table 4. 6/7 Ordering information Document revision history Date Revision 14-Apr-2008 1 Changes Initial release EMIF10-LCD03F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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