EMIF10-LCD02F3 - STMicroelectronics

EMIF10-LCD02F3
10-line IPAD™, EMI filter and ESD protection for LCD and cameras
Features
■
Lead-free package
■
EMI symmetrical (I/O) low-pass filter
■
High efficiency in EMI filtering
■
400 µm pitch
■
Compatible with high speed data rate
Lead-free Flip-Chip package
(24 bumps)
2
■
Very low PCB space occupation: < 4 mm
■
Very thin package: 0.60 mm
■
High efficiency in ESD suppression
■
High reliability offered by monolithic integration
■
High reduction of parasitic elements through
integration and wafer level packaging
Figure 1.
Complies with the following standards
■
■
IEC 61000-4-2 level 4 on inputs and outputs
– 15 kV (air discharge)
– 8 kV (contact discharge)
Pin layout (bump side)
5
4
3
2
1
O1
O2
GND
I1
I2
A
O3
O4
I3
I4
B
O5
O6
GND
I5
I6
C
O7
O8
GND
I7
I8
D
O9
O10
GND
I9
I10
E
MIL STD 883G - Method 3015-6 Class 3
Applications
Where EMI filtering in ESD sensitive equipment is
required:
■
LCD for mobile phones
■
Computers and printers
■
Communication systems
■
MCU boards
Figure 2.
Device configuration
Low-pass Filter
Output
Input
Description
GND
GND
GND
Ri/o = 70Ω
Cline = 30pF
The EMIF10-LCD02F3 is a 10-line highly
integrated device designed to suppress EMI/RFI
noise in all systems subjected to electromagnetic
interference. The EMIF10 Flip-Chip packaging
means the package size is equal to the die size.
This filter includes ESD protection circuitry, which
prevents damage to the protected device when
subjected to ESD surges up 15 kV.
November 2009
TM: IPAD is a trademark of STMicroelectronics.
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Characteristics
1
EMIF10-LCD02F3
Characteristics
Table 1.
Absolute maximum ratings (Tamb = 25 °C)
Symbol
Tj
Parameter and test conditions
Value
Unit
125
°C
Maximum junction temperature
Top
Operating temperature range
-40 to +85
°C
Tstg
Storage temperature range
-55 to 150
°C
Figure 3.
Symbol
VBR
VCL
IRM
VRM
IPP
IR
IPP
RI/O
Cline
Electrical characteristics (definitions)
=
=
=
=
=
=
=
=
=
Parameter
Breakdown voltage
Clamping voltage
Leakage current @ VRM
Stand-off voltage
Peak pulse current
Breakdown current
Forward current
Series resistanc between input and output
Input capacitance per line
I
IPP
VCL VBR VRM
IR
IRM
IRM
IR
V
VRM VBR VCL
IPP
Table 2.
Electrical characteristics (Tamb = 25 °C)
Symbol
Min.
Typ.
Max.
Unit
6
8
10
V
200
nA
VBR
IR = 1 mA
IRM
VRM = 3 V
50
R2
Tolerance ± 20%
70
Cline
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Test conditions
Vline = 0 V, VOSC = 30 mV, F =1 MHz
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Ω
30
pF
EMIF10-LCD02F3
Figure 4.
Characteristics
S21 all lines attenuation
measurement
Figure 5.
Analog cross talk measurement
0.00
dB
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
100.0k
1.0M
10.0M
100.0M
1.0G
f/Hz
Xtalk 1/2
Figure 6.
ESD response to IEC 61000-4-2
Figure 7.
(+15 kV air discharge) on one input
and on one output
ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input
and on one output
Input
10V/d
Input
10V/d
Output
10V/d
Output
10V/d
100ns/d
100ns/d
Figure 8.
Line capacitance versus applied voltage
Cline (pF)
30
25
20
15
10
5
Vline (V)
0
0
1
2
3
4
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Ordering information scheme
2
EMIF10-LCD02F3
Ordering information scheme
Figure 9.
Ordering information scheme
EMIF
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10 (pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
3 = Lead-free, pitch = 400 µm, bump = 255 µm
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yy
-
xxx zz
F3
EMIF10-LCD02F3
Package information
●
Epoxy meets UL94, V0
●
Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 10. Package dimensions
255µm± 40
605µm ± 55
170 µm typ
Figure 11. Footprint
1.94 mm ± 30µm
400 µm typ
400 µm typ
170 µm typ
3
Package information
1.94 mm ± 30µm
Figure 12. Marking
Copper pad Diameter:
220 µm recommended
260 µm maximum
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
Solder mask opening:
300 µm minimum
E
x x z
y ww
Solder stencil opening:
220 µm recommended
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Package information
EMIF10-LCD02F3
Figure 13. Flip-Chip tape and reel specification
Dot identifying Pin A1 location
3.5 ± 0.1
xxz
yww
ST E
Note:
2.11
xxz
yww
All dimensions in mm
ST E
xxz
yww
ST E
8 ± 0.3
2.11
0.69 ± 0.05
4 ± 0.1
User direction of unreeling
More information is available in the application notes:
AN2348: “STMicroelectronics 400 micro-metre Flip-Chip: Package description and
recommendation for use”
AN1751: "EMI Filters: Recommendations and measurements"
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1.75 ± 0.1
Ø 1.5 ± 0.1
4 ± 0.1
EMIF10-LCD02F3
4
Ordering information
Table 3.
5
Ordering information
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
EMIF10-LCD02F3
GY
Flip-Chip
5.0 mg
5000
Tape and reel 7”
Revision history
Table 4.
Document revision history
Date
Revision
Changes
11-Jul-2005
1
First issue.
28-Apr-2008
2
Updated ECOPACK statement. Updated Figure 9, Figure 10, Figure 11
and Figure 13. Reformatted to current standards.
18-Nov-2009
3
Updated Figure 10 for die dimension reduction. Updated Figure 13 for
scaling.
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EMIF10-LCD02F3
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