ESDA6V1-5W6 ® TRANSIL ARRAY FOR ESD PROTECTION Application Specific Discretes A.S.D.ä APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : n Computers n Printers n Communication systems n Cellular phone handsets and accessories n Other telephone sets n Set top boxes DESCRIPTION SOT323-6L FUNCTIONAL DIAGRAM The ESDA6V1-5W6 is a 5-bit wide monolithic suppressor which is designed to protect components connected to data and transmission lines against ESD. I/O1 I/O5 Gnd I/O4 I/O2 I/O3 FEATURES n n n n 5 UNIDIRECTIONAL TRANSIL FUNCTIONS BREAKDOWN VOLTAGE: VBR = 6.1V min LOW LEAKAGE CURRENT: IR max < 1 µA VERY SMALL SIZE FOR PCB SPACE SAVING: 4.2mm2 TYPICALLY BENEFITS n n High integration Suitable for high density boards ESD response to IEC61000-4-2 (air discharge 16kV, positive surge) COMPLIES WITH THE FOLLOWING STANDARDS: - IEC 61000-4-2: level 4 15 kV (air discharge) 8 kV (contact discharge) - MIL STD 883C-Method 3015-6: class3 (human body model) March 2000 - Ed: 1A 1/9 ESDA6V1-5W6 ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol Test conditions Value Unit VPP ESD discharge - MIL STD 883C - Method 3015-6 IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge 25 20 15 kV PPP Peak pulse power (8/20µs) 100 W Junction temperature 150 °C -55 to +150 °C 260 °C -40 to +125 °C Tj Tstg Storage temperature range TL Lead solder temperature (10 seconds duration) Top Operating temperature range (note 1) Note 1: The evolution of the operating parameters versus temperature is given by curves and αT parameter. ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameter I VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IF VBR Peak pulse current αT Voltage temperature coefficient C Capacitance Rd Dynamic impedance VF Forward voltage drop Slope = 1/Rd IPP VBR @ IR min. ESDA6V1-5W6 max . IRM @ VRM Rd αT C max. typ. max. typ. note 2 note 3 0V bias VF @ IF max V V mA µA V mΩ 10-4/°C pF V mA 6.1 7.2 1 1 3 610 6 50 1.25 200 Note 2 : Square pulse, Ipp = 15A, tp=2.5µs. Note 3: ∆VBR = αT * (Tamb - 25°C) * VBR (25°C) 2/9 V IRM IPP Type VF VRM Vcl ESDA6V1-5W6 Fig. 1: Peak power dissipation versus initial junction temperature. Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25°C). Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Ppp(W) 1000 100 tp(µs) Tj initial(°C) 0 25 50 75 100 125 150 10 175 Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25°C) Rectangular waveform tp = 2.5µs. 1 10 100 Fig. 4: Capacitance versus reverse applied voltage (typical values). Ipp(A) C(pF) 50.0 50 F=1MHz Vosc=30mV tp=2.5µs 40 10.0 30 1.0 20 VR(V) Vcl(V) 0.1 0 5 10 15 20 25 30 35 40 Fig. 5: Relative variation of leakage current versus junction temperature (typical values). 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Fig. 6: Peak forward voltage drop versus peak forward current (typical values). IR[Tj] / IR[Tj=25°C] IFM(A) 50 1E+0 Tj=25°C 1E-1 10 1E-2 Tj(°C) 1 25 50 75 100 125 VFM(V) 1E-3 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 3/9 ESDA6V1-5W6 Connector IC to be protected APPLICATION EXAMPLE Implementation of ESDA6V1-5W6 in a typical application TECHNICAL INFORMATION ESD PROTECTION The ESDA6V1-5W6 is particularly optimized to perform ESD protection. ESD protection is achieved by clamping the unwanted overvoltage. The clamping voltage is given by the following formula : Vcl = Vbr + Rd ⋅ Ipp As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor. Fig. A1: ESD clamping behavior Rg Rd Voutput Vg Rload Vbr ESD Surge 4/9 ESDA6V1-5W6 Device to be protected ESDA6V1-5W6 To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis : Rg > Rd and Rload > Rd we have: Vin = Vbr + Rd × Vg Rg The results of the calculation done for Vg = 8 kV, Rg = 330 Ω (IEC 61000-4-2 standard), Vbr = 6.4 V (typ.) and Rd = 0.61 Ω (typ.) give: Vouput = 21.2 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side. Fig. A2: Measurement conditions: ESD SURGE TEST BOARD 16kV Air Discharge E62 Vi/o 5/9 ESDA6V1-5W6 The measurements done here after show very clearly (Fig. A3) the high efficiency of the ESD protection: the clamping voltage Vout becomes very close to Vbr (positive way, Fig. A3a) and -Vf (negative way, Fig. A3b). Fig. A3: Remaining voltage during ESD surge a: Vi/o during positive surge b: Vi/o during negative surge One can note that the ESDA6V1-5W6 is not only acting for positive ESD surges but also for negative ones. For these kind of disturbances it clamps close to ground voltage as shown in Fig. A3b. CROSSTALK BEHAVIOR Fig. A4: Crosstalk phenomenon RG1 Line 1 VG1 VG2 Line 2 RL2 DRIVERS 6/9 α1 VG1 + β12 VG2 RL1 RG2 α2 VG2 + β21 VG1 RECEIVERS ESDA6V1-5W6 The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor ( β12 or β21 ) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is α2VG1. In fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). Fig. A5: Analog crosstalk measurements TEST BOARD 50Ω E62 Port1 Port2 50Ω Vg Fig. A6: Typical analog crosstalk measurements Analog crosstalk (dB) 0 -20 -40 -60 -80 -100 1 10 100 frequency (MHz) 1,000 Figure A5 gives the measurement circuit for the analog crosstalk application. In figure A6, the curve shows the effect of the cell I/O5 on the cell I/O3. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -40dB. 7/9 ESDA6V1-5W6 Fig. A7: Digital crosstalk measurements configuration +5V +5V 74HC04 74HC04 Line1 VG1 Square Pulse Generator ESDA6V1 -5W6 +5V Line 2 β21 VG1 Fig. A8: Digital crosstalk measurements configuration Figure A7 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A8 shows that in such a condition, i.e signal from 0 to 5V and rise time of a few ns, the impact on the disturbed line is less than 50 mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges give an impact within the same range. ORDER CODE ESDA 6V1 - 5 W6 VBR min SOT323-6L ESD ARRAY 5 lines protected 8/9 ESDA6V1-5W6 PACKAGE MECHANICAL DATA SOT323-6L DIMENSIONS A2 A A1 D e e E H REF. c b Inches Min. Max. Min. Max. A 0.8 1.1 0.031 0.043 A1 0 0.1 0 0.004 A2 0.8 1 0.031 0.039 b 0.15 0.3 0.006 0.012 c 0.1 0.18 0.004 0.007 D 1.8 2.2 0.071 0.086 E 1.15 1.35 0.045 0.053 e Q Millimeters 0.65 Typ. 0.025 Typ. H 1.8 2.4 0.071 0.094 Q 0.1 0.4 0.004 0.016 FOOT PRINT 0.3mm 1mm 2.9mm 1mm 0.35mm MARKING Type Marking Package Weight Base Qty Delivery mode ESDA6V1-5W6 E62 SOT323-6L 5.4 mg 3000 Tape & Reel Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9