L5953 Multiple switching voltage regulator Features ■ PWM: adjustable 2.5/10V - 1A switching voltage regulator ■ External POWER MOS ability for output current enhancement ■ Synchronization function ■ REG1- Linear low drop 3.3/5V - 250mA STBY voltage regulator (low current consumption) with RESET PowerSO36 ■ REG2- Linear voltage regulator 1.5V to 3.3V externally adjustable - 300mA maximum current ■ HSD1 : 500mA High side driver Protections ■ HSD2 : 200mA High side driver ■ Over voltage protection ■ SPI Interface ■ Internal current limiting ■ SPI Diagnostics HSD1, HSD2 ■ Thermal shutdown ■ Double switching frequency SPI selectable ■ ESD ■ Double inpuT LVW SPI functions Description ■ Input controls – Turn-on/off PWM – Turn-on/off REG2 – Turn-on/off HSD1 – Turn-on/off HSD2 – Switching frequency selection f1- f2 ■ Output functions: – HSD1 & HSD2 short to gnd, open load and short to battery (Test mode) – Thermal warning The L5953 is the integration of one switching regulator, two linear voltage regulators, two low voltage warnings and two high side drivers. It has a stand-by operation mode (low current consumption) where only the stand-by voltage regulator plus the low voltage warnings are active. The other regulators and high side drivers are controlled by the SPI interface. Table 1. Device summary Part number Package Packing L5953 PowerSO36 Tray September 2007 Rev 2 1/31 www.st.com 1 Contents L5953 Contents 1 Block diagram and electrical specifications . . . . . . . . . . . . . . . . . . . . . . 6 2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 REG1 stand-by regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Low voltage warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 REG2 linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 High side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 PWM step down voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.1 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . 15 3 Internal pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 6 2/31 4.1 Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 Write Enable (WREN and Write Disable (WRDI)) . . . . . . . . . . . . . . . . . . 18 Summary of the main operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 Operation A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 Operation B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 Operation C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Operation D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 Operation E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6 Operation F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.7 Operation G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.8 Operation H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9 IRQ - Interrupt Request Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 REG1 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 Feedback resistors for REG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 L5953 Contents 6.3 External components for PWM regulator . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 Bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 Free-wheeling diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 Compensation Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3/31 List of tables L5953 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. 4/31 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Diagnostic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Diagnostic register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Diagnostic register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 L5953 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Low voltage warning block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 HSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI & IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write enable latch sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Test mode diagnostic procedure start (after a write enable latch sequence. . . . . . . . . . . . 22 Read the diagnostic registerCase1: after a test mode diagnostic procedure start . . . . . . . 22 Diagnostic procedure start (after write enable latch sequence operation A) . . . . . . . . . . . 23 Read the diagnostic RegisterCase2: after a diagnostic procedure start. . . . . . . . . . . . . . . 23 Write the status register (after a write enable latch sequence operation A) . . . . . . . . . . . . 23 Read the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block and application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Block diagram and application with external Power MOS . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerSO36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5/31 Block diagram and electrical specifications 1 L5953 Block diagram and electrical specifications Figure 1. Block diagram S1 W1 S2 W2 VDD-SW VDD-LIN STCAP CT RES FGND REC1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA VOLTAGE WARNING VSTBY ADJ HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A HSD2 HSD2 STRAP DRAINOUT VSW GATEIN GATEOUT FB VSPI REC2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA SPI INTERFACE IRQ COMP OSCILLATOR & SYNC SWGND GND Q Table 2. D S C VLR FBLR Parameter DC operating supply voltage VSPI DGND D01AU1330A Transient supply over voltage (250ms) Supply voltage for SPI I/O Value Unit -0.6 to 30 V 50 V -0.6 to 6 V IO Voltage regulator output current Internally limited Vinlog Input voltage (C, D, Q, S, SYNC) 0 to 6 V RESR Output capacitor series e.g. resistance (linear reg.) (allowed range) From 0.2 to 10 W Top Operating temperature range -40 to 85 °C Tstg Storage temperature ranges -55 to 150 °C Operative junction temperature -40 to 150 °C Value Unit 1.7 °C/W Tj Table 3. Symbol Rthj-case 6/31 SYNC Absolute maximum ratings Symbol VDD VIN Thermal data Parameter Thermal resistance junction to case L5953 Block diagram and electrical specifications Figure 2. PIN connections FGND 1 36 ADJ S2 2 35 VSTBY S1 3 34 VSPI W2 4 33 STCAP W1 5 32 FB RES 6 31 COMP CT 7 30 FBLR D 8 29 VIN C 9 28 VLR Q 10 27 SYNC S 11 26 STRAP DGND 12 25 GATEOUT IRQ 13 24 GATEIN HSD2 14 23 VSW VDD-LIN 15 22 GND N.C. 16 21 N.C. HSD1 17 20 DRAINOUT SWGND 18 19 VDD-SW D02AU1345A Table 4. PIN function Pin number Pin name Function 1 FGND Analog ground 2 S2 Input voltage for LVW2 3 S1 Input voltage for LVW1 4 W2 LVW2 output 5 W1 LVW1 output 6 RES Reset 7 CT Timing capacitor 8 D SPI serial input 9 C SPI clock 10 Q SPI serial output 11 S SPI chip select 12 DGND SPI ground 13 IRQ Interrupt 14 HSD2 HSD2 output 15 VDD-LIN Battery 16 N.C. Not connected 17 HSD1 HSD1 output 18 SWGND Switching ground 19 VDD-SW PWM battery 20 DRAINOUT Drain of the external MOS 7/31 Block diagram and electrical specifications Table 4. PIN function (continued) Pin number Table 5. Pin name Function 21 N.C. Not connected 22 GND Ground 23 VSW Source of the external MOS 24 GATEIN Gate of the internal MOS 25 GATEOUT Switching output for power mos gate 26 STRAP Bootstrap 27 SYNC Synchronization 28 VLR REG2 linear voltage regulator output 29 VIN REG2 linear voltage regulator input 30 FBLR REG2 linear voltage regulator feedback 31 COMP PWM compensation 32 FB PWM feedback 33 STCAP ST-CAP 34 VSPI Supply voltage for SPI I/O 35 VSTBY REG1 stand-by linear voltage regulator output 36 ADJ 3.3V/5V REG1 voltage select Electrical characteristics (Tamb = 25°C, VDD = 14.4V) Symbol Parameter IQ,STBY Quiescent current with regulators and high-side drivers off Tsd L5953 Test condition Min. Typ. W1, W2, RES, IRQ, not active; REG2, HSD1, HSD2, PWM off; S, C, D fixed at high/low logic level Thermal shutdown junction temperature Max. Unit 100 μA 150 °C SMPS.PWM (Tamb = 25°C, VDD = 14.4V, Vo = 5V; unless otherwise specified.) Vo,min Minimum output voltage Io = 200mA 2.4 2.5 2.6 V Vo,max Maximum output voltage Io = 200mA 9.6 10 10.4 V Vref,PWM Vi 8/31 Voltage reference 1.275 Input voltage range Vo = 5V; Io = 0.5A ΔVo Line regulation ΔVo 6 V 18 V Io = 0.5A 100 mV Load regulation Vo = 5V; Io = 0.2A to 0.5A 50 mV Dropout voltage between Pin 19 and Pin 23 Io = 0.5A, Vo = 5V 0.5 V Vd 1 V ILim Current limit Io = 1A, Vo = 5V 1.2 A L5953 Table 5. Block diagram and electrical specifications Electrical characteristics (continued) (Tamb = 25°C, VDD = 14.4V) Symbol h SVR Parameter Test condition Min. Typ. Max. Unit Efficiency f = 260kHz; Io = 0.5A f = 400kHz; Io = 0.5A 90 86 % % Supply voltage ripple rejection ΔVi = 1Vrms; fripple = 300Hz; Io = 0.4A 50 dB Oscillator f1 Switching frequency 240 260 280 kHz f2 Switching frequency 375 400 425 kHz Δf --------ΔV i Voltage stability of switching frequency VDD = 8 to 18V Tbd % Δf --------ΔT j Temperature stability of switching frequency Tj = -40°C to 85°C Tbd % Sync VIL Low input voltage VIH High input voltage VOL Low output voltage VOH High output voltage 0.8 2 V 0.4 ISOURCE=1.5mA V 4 V V ISLAVE Slave sink current 100 μA TW Output pulse width 300 ns REG1 - 3.3V/5V STBY linear voltage regulator VSTBY Output voltage no load; ADJ pin = open no load; ADJ pin = VSTBY pin ΔVline Line regulation ΔVload Vdropout Ilim SVR 4.9 3.20 5 3.3 5.1 3.4 V V no load; 7 < Vdd < 26V 5 50 mV Load regulation 5mA < Io < 250mA 12 80 mV VSTCAP - VSTBY Io = 100mA, Vo = 5V Io = 100mA, Vo = 3.3V 0.36 0.47 0.5 0.65 V Current limit Out short to GND Supply voltage rejection ΔVDD = 1Vrms: f = 300Hz Io = 250mA 300 mA 55 dB REG2 - Linear voltage regulator 1.5V to 3.3V no load; 4.75 ≤ VIN ≤ 16V; 1+ (R5/R6) = 2.588 VLR Linear regulator output voltage no load; 3.135 ≤ VIN ≤ 16V; 1+ (R5/R6) = 1.176 3.2 3.3 3.4 V 1.45 1.5 1.55 9/31 Block diagram and electrical specifications Table 5. Electrical characteristics (continued) (Tamb = 25°C, VDD = 14.4V) Symbol VIN L5953 Parameter Input voltage Test condition Min. Typ. Max. Unit IO = 150mA 1.5V ≤ VLR ≤ 2V 3.135 16 V IO = 300mA 1.5V ≤ VLR ≤ 3.3V 4.75 16 V ΔVload Load regulation 5mA ≤ IO ≤ 300mA 4.75V ≤ VIN ≤ 16V; 1.5V ≤ VLR ≤ 3.3V 12 mV ΔVline Line regulation no load; 4.75V ≤ VIN ≤ 16V; 1.5V ≤ VLR ≤ 3.3V 1 mV 1.275 V Vref,REG2 ILim SVR Voltage reference Current limit Supply voltage rejection Out short to ground 400 mA VIN = 5Vdc, 0.5Vacpp, 300Hz IO = 300mA; 1.5V ≤ VLR ≤ 3.3V 55 dB VIN = 3.3Vdc, 0.5Vacpp, 300Hz IO = 150mA; 1.5V ≤ VLR ≤ 2V 55 dB HSD1 Vsat, peak Ilim Lload Saturation voltage IO = 0.5A Current limit 350 600 mV mA Load inductance 100 mH 300 mV HSD2 Vsat, peak Ilim Lload Saturation voltage IO = 0.2A Current limit 300 mA Load inductance 100 mH Voltage warning Vst Sense low threshold Vsth Sense threshold hysteresis VSL Sense output low voltage ISH ISI 1.245 1.275 1.305 35 45 V 60 mV Io = 1mA 0.4 V Sense output leakage VW = 5V; VSI ≥ 1.5V 10 μA Sense input current VSI=5V 1 μA Reset VRT Reset threshold voltage 0.95 x VSTBY V VRTH Reset threshold hysteresis 0.02 x VSTBY V VRL Reset output voltage 10/31 Io = 1mA 0.4 V L5953 Table 5. Block diagram and electrical specifications Electrical characteristics (continued) (Tamb = 25°C, VDD = 14.4V) Symbol IRH Parameter Test condition Reset output leakage Min. Typ. VRT = VSTBY Max. Unit 10 μA VCTth Delay comparator threshold 0.5 x VSTBY VCThy Delay comparator threshold hysteresis 180 mV ICT1 Timing capacitor output source current 7.5 μA RCT2 Timing capacitor output pull-down equivalent resistor 150 Ω Table 6. Diagnostic parameters Symbol Parameter Test condition HSD1W1 High side driver 1 overcurrent warning activation HSD1W2 High side driver 1 open load warning activation HSD1 output voltage in test mode HSD1W2 TEST High side driver 1 vdd short warning activation in test mode HSD1 in test mode measure VVDD-LIN-VHSD1 HSD2W1 High side driver 2 overcurrent warning activation HSD2W2 High side driver 2 open load warning activation HSD2 output voltage in test mode HSD2W3 High side driver 2 vdd short warning activation in test mode HSD2 in test mode measure VVDD-LIN-VHSD1 THW Min. Typ. 1 Max. 1 A 3 V 1.5 1 2 V 0.5 A 3 V 1.5 Thermal warning activation Unit 2 145 V °C IRQ - Interrupt request pin IRQ-L IRQ low voltage Io = 1mA 0.4 V IRQ-H IRQ leakage Virq = 5V 1 μA Min. Max. Unit 3 5.5 V Table 7. Symbol SPI interface Alt Parameter Test conditions Recommended DC operating voltage VSPI Supply voltage for SPI I/O Input parameters (Tamb = 25°C, f = 1MHz) CIN Input capacitance (D) 8 pF CIN Input capacitance (others pins) 6 pF tLPF Input signal pulse width 10 ns 11/31 Block diagram and electrical specifications Table 7. Symbol L5953 SPI interface (continued) Alt Parameter Test conditions Min. Max. Unit DC characteristics (Tamb = -40 to 85°C, VSPI = 3V to 5.5V) ILI Input leakage current 5 μA ILO Output leakage current ±2 μA VIL Input low voltage 0.3VSP V VIH Input high voltage VOL Output low voltage IOL = 2mA VOH Output high voltage IOH = -2mA -0.3 I 0.7VSPI VSPI+1 V 0.2VSPI V 0.8VSPI V AC characteristics (Tamb = -40 to 85°C, VSPI = 3V to 5.5V tSCLH tSU S setup time 50 ns tCLSH tSH S hold time 50 ns tCH tWH Clock high time 200 ns tCL tWL Clock low time 300 ns tCLCH tRC Clock rise time 1 μs tCHCL tFC Clock fall time 1 μs tDVCH tDSU Data In setup time 50 ns tCHDX tDH Data In hold time 50 ns tDLDH tRI Data In rise time 1 μs tDHDL tFI Data in fall time 1 μs tSHSL tCS S deselect time tSHQZ tDIS Output disable time 150 ns tQVCL tV Clock low to output valid 250 ns tCLQX tHO Output hold time tQLQH tRO Output rise time 100 ns tQHQL tFO Output fall time 100 ns Figure 3. 4.5V < VSPI < 5.5V 3V < VSPI < 4.5V ns ns 0 AC testing input output waveforms 0.8VSPY 0.2VSPY 0.7VSPY 0.3VSPY D03AU1479 12/31 200 250 ns L5953 Block diagram and electrical specifications Figure 4. SPI clocking scheme S (MODE 0: CPOL=0,CPHA=0) C C (MODE 3: CPOL=1,CPHA=1) D Q MSB Figure 5. 6 5 4 3 2 1 0 Output timing S tCH C tCL tCLQX tSHQZ tQVCL MSB OUT Q MSB-1 OUT LSB OUT tQLQH tQHQL D ADDR.LSB IN (CPOL=0, CPHA=0) Figure 6. AI01070B Serial input timing tSHSL S tSLCH tCLSH C tDVCH tCHCL tCHDX D tCLCH MSB IN LSB IN HIGH IMPEDANCE tDLDH tDHDL Q (CPOL=0, CPHA=0) AI01071 13/31 Functional description 2 Functional description 2.1 REG1 stand-by regulator L5953 The stand-by regulator (Figure 7.) output voltage can be 5V or 3.3V. It is externally selectable by means of the ADJ pin: - leaving the ADJ pin open, the output voltage is 5V; - connecting the ADJ pin to the Vstby pin the output voltage becomes 3.3V. This regulator is supplied by STCAP pin and provide the reset information. It has a current protection which limits the maximum allowable output current. 2.2 Reset The RES pin (Figure 8.) is an open collector that is activated (that is forced to zero) when the stand-by regulator is not in regulation (including thermal shutdown and faults). The indication that REG1 is in regulation is delayed by a time set up by the external capacitor CT. When the RES is switched on, HSD1, HSD2, REG2, PWM are turned off and until the RES is forced to zero only the REG1 and low Voltage Warnings are active. 2.3 Low voltage warning This circuit is able to sense two different voltages through external resistors to increase the overall flexibility. (Figure 9.) If S1 pin voltage is higher than Vst, the output of mos M1 is off: W1 is floating and can be pulled up by an external resistor. If S1 pin voltage goes down and becomes lower than Vst, the mos M1 is turned on and forces W1 to zero. The same thing happens for S2 - W2. The outputs W1 and W2 can be connected together to get a single output. 2.4 REG2 linear voltage regulator REG2 is a linear voltage regulator (Figure 7.) with a dedicated supply pin VIN. The output voltage (between 1.5V and 3.3V) is fixed by an external divider. It can be turned on/off by SPI. It has a current protection which limits the maximum allowable output current. 2.5 High side drivers Two high-side driver (Figure 10.) with charge pump controlled by SPI are available inside L5953. They are protected against short to ground: the short circuit protection limits the maximum output current. A diagnostic procedure is available to detect open load, short to battery and overcurrent. Open load and short to battery can be reveal only in test mode while overcurrent is active only during normal operation of the device. (see 4.2 on page 18) 14/31 L5953 2.6 Functional description PWM step down voltage regulator The switching regulator (Figure 11.) inside the L5953 is a voltage control mode (also known as a direct duty cycle) Buck regulator: the error signal coming from the error amplifier is compared with a sawtooth to set on and off times of the power switch. The feedforward control is introduced to get a quickly response to input voltage changes: the sawtooth has a fixed frequency and an amplitude variable with the battery voltage. Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the free-wheeling diode. 2.6.1 Error amplifier and compensation network The error amplifier (EA) is a voltage amplifier whose non-inverting input is fixed to the reference voltage (1.275V bandgap voltage) and whose inverting input and output are externally available for feedback and frequency compensation. 15/31 Internal pin connections 3 L5953 Internal pin connections Figure 7. Linear regulators STCAP VREF 1.275V POWER MOS VSTBY VSTBY VSTBY CONTROLLER ADJ FGND FBLR LINEAR REGULATOR CONTROLLER VLR POWER MOS VREF 1.275V VIN D03AU1493 Figure 8. Reset RES Vref 2.5V/1.65V 7.5μA CT FROM VST-BY Vref 1.275V D03AU1480 Figure 9. Low voltage warning block diagram. V1 Vref =1.275V S1 W1 + - M1 V2 Vref =1.275V S2 W2 + - M2 D03AU1478 16/31 L5953 Internal pin connections Figure 10. HSD HSD1 POWER MOS HSD1 HSD1 CONTROLLER VDD-LIN POWER MOS HSD2 HSD2 CONTROLLER HSD2 D01AU1333 Figure 11. PWM STRAP COMP ERROR AMPLIFIER FB VDD-SW RS2 DRAINOUT CURRENT SENSING RS1 VREF 1.275V PWM CONTROLLER POWER MOS FROM THE OSCILLATOR VSW GATEIN GATEOUT D03AU1482 Figure 12. SPI & IRQ IRQ S Q SPI INTERFACE D C DGND D03AU1481 17/31 SPI interface L5953 4 SPI interface 4.1 Signals description The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3. Serial output (Q). The output pin is used to transfer data serially out of the L5953. Data is shifted out on the falling edge of the serial clock. Serial input (D). The input pin is used to transfer data serially into the device. It receives instructions, addresses, and data to be written. Input is latched on the rising edge of the serial clock. Serial clock (C). The serial clock provides the timing of the serial interface. Instructions, addresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after the falling edge of the clock input. Chip select (S). This input is used to select the L5953. The chip is selected by a high to low transition on the S pin. At any time, the chip is deselected by a low to high transition on the S pin. As soon as the chip is deselected, the Q pin is at high impedance state. The pin allows multiple L5953 to share the same SPI bus. After power up, the chip is at the deselect state. SPI Input/Output are supplied by an external supply voltage VSPI while the core is supplied by the stand-by regulator VSTBY. The SPI is reset by an internal signal whose buffered version is RES. (See Figure 12.) 4.2 Operations All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction code must be entered in the chip. This code is entered in the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S = low). Table 1 shows the instruction set and format for device operation. An invalid instruction (one not contained in table 1) leaves the chip as previously selected. 4.3 Write enable (WREN and write disable (WRDI)) The L5953 contains a write enable latch. This latch must be set prior to every WRITE operation. The WREN instruction will set the latch and the WRDI instruction will reset the latch. The latch is reset under all the following conditions: – – Power on – – WRDI instruction executed As soon as the WREN or WRDI instruction is received by the L5953, the circuit executes the instruction and enters a wait mode until it is deselected. 18/31 L5953 SPI interface . Table 8. Instruction set Instruction Table 9. Description Instruction Format WREN Set write enable latch 00000110 WRDI Reset write enable latch 00000100 WSTA Write status register 00000010 RDIA Read diagnostic register 00000101 RSTA Read status register 00000011 . Status register s15 s14 s13 s12 s11 REG 2 HSD 1 HSD 2 TBD TBD Table 10. s10 s9 s8 PWM PWM TBD freq. s7 s6 s5 s4 s3 s2 TBD TBD TBD TBD TBD TBD s1 s0 Test START mode DIAG Status register description 0 1 s15 REG2 linear voltage regulator 1.5 to 3.3V Regulator off Regulator on s14 High side driver 1 HSD1 off HSD1 on s13 High side driver 2 HSD2 off HSD2 on s12 TBD s11 TBD s10 PWM switching frequency 260kHz 400kHz s9 PWM voltage regulator PWM1 off PWM1 on s8 TBD s7 TBD s6 TBD s5 TBD s4 TBD s3 TBD s2 TBD s1 Test mode Test mode off Test mode on (1) Diagnostic off Starts the diagnostic procedure: - in test mode if s1=1; - during normal operation if s1=0 If s1=0 and s0=1, must be s14 = 1 (HSD1 ON) and s13=1 (HSD2 ON) s0 Diagnostic 1. In this case the bits s15 - s2 are internally set to 0 (regulators and high side drivers are in off condition) 19/31 SPI interface L5953 . Table 11. Diagnostic register d7 d6 d5 d4 d3 d2 d1 d0 Test mode HSD1W1 HSD1W2 HSD1W3 HSD2W1 HSD2W2 HSD2W3 THW . Table 12. Diagnostic register description 0 1 Test mode The diagnostic register is referred to a test performed during the normal working of the L5953 The diagnostic register is referred to a test performed in Test mode HSD1W1 If d7=0: HSD1 in normal condition; If d7=1: bit value meaningless If d7=0: HSD1 is in overcurrent If d7=1: bit value meaningless HSD1W2 If d7=0: bit value meaningless; If d7=1: HSD1 in normal condition If d7=0: bit value meaningless If d7=1: an open load is present on HSD1 HSD1W3 If d7=0: bit value meaningless; If d7=1: HSD1 in normal condition If d7=0: bit value meaningless If d7=1: HSD1 is shorted to the supply voltage VDD HSD2W1 If d7=0: HSD1 in normal condition; If d7=1: bit value meaningless If d7=0: HSD2 is in overcurrent; If d7=1: bit value meaningless HSD2W2 If d7=0: bit value meaningless If d7=1: HSD2 in normal condition If d7=0: bit value meaningless If d7=1: an open load is present on HSD2 d1 HSD1W3 If d7=0: bit value meaningless If d7=1: HSD2 in normal condition; If d7=0: bit value meaningless If d7=1: HSD1 is shorted to the supply voltage VDD d0 Thermal warning Normal condition Over temperature protection activated(Tj>150°C) d7 d6 d5 d4 d3 d2 20/31 L5953 Summary of the main operations 5 Summary of the main operations 5.1 Operation A 5.2 ● Test mode diagnostic procedure start ● 1) WREN instruction (Figure 13.) ● 2) WSTA instruction (Figure 14.) Operation B ● Read the diagnostic register Case1: after a test mode diagnostic procedure start 1) RDIA instruction (Figure 15.) 2) Diagnostic register output (Figure 15.) Note: An operation B must follow an operation A. The delay between the end of the operations A to the start of the operations B must be longer than 100μS 5.3 Operation C ● 5.4 Operation D ● 5.5 Read the status register 1) RSTA instruction (Figure 19.) 2) Status Register output (Figure 19.) Operation E ● 5.6 Write the status register 1) WREN instruction (Figure 13.) 2) WSTA instruction (Figure 18.) Diagnostic procedure start 1) WREN instruction (Figure 13.) 2) WSTA instruction (Figure 16.) Operation F ● Read the diagnostic register Case 2: after a diagnostic procedure start 1) RDIA instruction (Figure 17.) 2) Diagnostic register output (Figure 17.) An operation F must follow an operation E, if the IRQ pin is not activated. The delay between Operation E and Operation F must be longer than 100μs. To be recognized, the fault must be present without interruptions, during all the delays mentioned. After an Operation F, the bit s0 of the status register is reset (0) 21/31 Summary of the main operations 5.7 Operation G ● 5.8 L5953 Write operation disabled 1) WRDI instruction (Table 8.) Operation H ● Read the diagnostic register case 3: after an IRQ pin activation 1) RDIA instruction (Figure 17.) 2) Diagnostic register output (Figure 17.) The delay between the IRQ activation and operation F must be longer than 100μs Figure 13. Write enable latch sequence S 00 01 02 03 04 05 06 07 C CPOL=0 CPHA=0 D HIGH IMPEDANCE Q D03AU1483 Figure 14. Test mode diagnostic procedure start (after a write enable latch sequence) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 s15 s14 s13 s12 s11 s10 14 15 16 17 18 19 20 21 22 23 s6 s5 s4 s3 s2 s1 s0 C INSTRUCTION STATUS REGISTER D s9 s8 s7 HIGH IMPEDANCE Q D03AU1484 Figure 15. Read the diagnostic registerCase1: (after a test mode diagnostic procedure start) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 d7 d6 10 11 12 13 14 15 C INSTRUCTION D DIAGNOSTIC REGISTER OUT HIGH IMPEDANCE Q 22/31 d5 d4 d3 d2 d1 d0 D03AU1485 L5953 Summary of the main operations Figure 16. Diagnostic procedure start (after write enable latch sequence operation A) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 s15 s14 s13 s12 s11 s10 14 15 16 17 18 19 20 21 22 23 s6 s5 s4 s3 s2 s1 s0 C INSTRUCTION STATUS REGISTER D s9 s8 s7 HIGH IMPEDANCE Q D03AU1486 Figure 17. Read the diagnostic RegisterCase2: during the normal working of the L5953 (after a diagnostic procedure start, see Figure 16) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 C INSTRUCTION D DIAGNOSTIC REGISTER OUT HIGH IMPEDANCE d7 Q d6 d5 d4 d3 d2 d1 d0 D03AU1487 Figure 18. Write the status register (after a write enable latch sequence operation A) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 s15 s14 s13 s12 s11 s10 14 15 16 17 18 19 20 21 22 23 s6 s5 s4 s3 s2 s1 s0 C INSTRUCTION STATUS REGISTER D s9 s8 s7 HIGH IMPEDANCE Q D03AU1488 Figure 19. Read the status register CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 s15 s14 s13 s12 s11 s10 14 15 16 17 18 19 20 21 s5 s4 s3 s2 22 23 s1 s0 C INSTRUCTION D STATUS REGISTER OUT HIGH IMPEDANCE Q s9 s8 s7 s6 D03AU1489 23/31 Summary of the main operations 5.9 24/31 L5953 IRQ - Interrupt request pin ● It is an open drain pin activated (low) every time a variation occurs in the diagnostic register. ● Purpose: to alert the μP that one or more warning bit of the diagnostic register has changed from 0 to 1 or from 1 to 0. ● An activation of this pin puts the bit s0 of the status register to 1 (start diagnostic) like an operation e (diagnostic procedure start). Then an operation F has to be executed without an operation E before. ● After an operation F, the IRQ pin is deactivated, and goes to 1 if connected to a pull-up resistor. L5953 6 Application note Application note Figure 20. Block and application diagram C2 C5 S1 W1 S2 D1 C1 VDD W2 VDD-LIN VDD-SW C3 C11 STCAP CT RES FGND VSTBY REG1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA VOLTAGE WARNING C4 ADJ HSD1 HSD1 STRAP PWM STEP DOWN REGULATOR 2.5-10V/1A HSD2 HSD2 C6 DRAINOUT L1 VSW Vo GATEIN D2 GATEOUT R2 FB VSPI REG2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA SPI INTERFACE IRQ COMP OSCILLATOR & SYNC R4 R3 C9 SWGND GND Q D S VLR C C10 FBLR R5 VIN SYNC C7 R1 C8 D01AU1331B DGND R6 Figure 21. Block diagram and application with external power MOS C2 C5 S1 W1 S2 D1 C1 VDD W2 VDD-LIN VDD-SW C3 STCAP CT RES FGND REG1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA VOLTAGE WARNING VSTBY C4 ADJ HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A HSD2 HSD2 STRAP C6 DRAINOUT L1 VSW Vo D2 GATEIN GATEOUT M1 R2 FB VSPI REG2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA SPI INTERFACE IRQ C7 R1 COMP R4 OSCILLATOR & SYNC SWGND C9 R3 GND C8 Q D S C VLR C10 FBLR R5 VIN SYNC DGND D01AU1332B R6 25/31 Application note L5953 Part list on evaluation board C1 = 470 μF C2 = 220 nF C3 = 470 μF C4 = 10 μF C5 = 1 μF C7 = 470 μF ESR=65 mΩ C8 = 56nF C9 = 2.7 nF C10 = 10 μF C11 = 4.7 nF R1 = 2.2 kΩ R2 = 2 x 1.5 kΩ in parallel R3 = 10 kΩ R4 = 220 kΩ R5 = 3.3 kΩ D1 = 1N4007 or MBR160 D2 = MBR360 L1 = 180 μH 6.1 C6 = 100 nF R6 = 1 kΩ REG1 output voltage VSTBY = 5V if pin ADJ left floating VSTBY = 3.3V if pin ADJ is connected to the pin VSTBY Timing capacitor The value for this capacitor has to be chosen according the wanted power-on delay Td: I CT1 ⋅ T d C11 = ---------------------------------------------------------------( 0.5 ⋅ V STBY ) + V CTLHy where ICT1 is the source current used to charge the timing capacitor and VSTBY is the REG1 output voltage. 6.2 Feedback resistors for REG2 V LR ⎛ ⎞ R5 = R6 ⋅ ⎜ ---------------------------- – 1⎟ ⎝ V ref, REG2 ⎠ where VLR is the required output voltage for REG2. 6.3 External components for PWM regulator 6.3.1 Bootstrap capacitor The suggested value for the bootstrap capacitor is C6 = 100nF Here following you find the criteria for the selection of the inductor L1, the free-wheeling diode D2, the output filter capacitor C7, the feedback resistor R1, R2 and the compensation network R3, C8, R4, C9 to have a Buck regulator working in continuous mode. Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the free-wheeling diode. 6.3.2 Inductor selection The minimum value of the inductor L7 has to be so that the maximum inductor current ripple ΔIL,max is 20% to 30% of the maximum load current load Io,max.The maximum ripple is present when the switching frequency is minimum (fsw,min) and the input voltage is maximum (Vin,max) so the minimum value for the inductor Lmin is: 26/31 L5953 Application note VO VO 1 L min = --------------------- ⋅ 1 – ------------------ ⋅ -------------------ΔI L, max V i, max f sw, min 6.3.3 Output capacitor selection The criteria for the selection of the capacitor C7 is based on the output voltage ripple requirements. The ripple on the output voltage is due to a capacitive contribute, often negligible, equal to ΔI L, max ΔV c = ---------------------------------------8 ⋅ C7 ⋅ f sw, min and a resistive contribute given by the ESR of the capacitor and which is equal to ΔV ESR = ESR ⋅ ΔI L, max ΔVC fixes the value for C7 while ΔVESR limits the ESR of the capacitor.Usually the capacitor is chosen so that the total ripple on the output regulated voltage Vo is equal to 1% of the value of Vo. If Vripple is the maximum allowed voltage ripple on Vo then it should result: 2 V ripple ≥ ΔV c + ΔV ESR 2 More often the minimum value of C7 is imposed by other considerations such as to get a good dynamic behavior of the output voltage in case of large load variations. 6.4 Free-wheeling diode The diode must withstand an average current Id equal to Id = Ilim (1- Dmin) where Ilim is the current of intervention of the short circuit protection and Dmin is the minimum duty cycle. As Dmin is very low, the current Id can be assumed equal to Ilim. 6.5 Compensation network In continuous mode, the voltage controlled buck converter shows two poles due to the output LC filter and one zero due to the ESR of the output capacitor. The suggested compensation network introduces two zeros and two poles: – the zeros compensate the double poles of the LC filter – one pole compensates the zero due to ESR of the output capacitor the second pole is nominally located in the origin which means an infinite gain at frequency null. In the reality the DC value of the closed loop gain can not be greater than the DC value of the EA open loop gain and the pole is located at very low frequency. The values for the components of the compensation network can be fixed when the inductor L1 and the output capacitor C7 are chosen. The necessary steps are: 27/31 Application note L5953 1. Fix the cross-over frequency fC of the overall loop gain. Usually: f c = 0.1 ⋅ f sw,min where fsw,min is the minimum switching frequency 2. Calculate the high frequency error amplifier gain L1 G c = 0.25 ⋅ f c ⋅ 2 ⋅ π ⋅ ------------ESR 3. Chose R3 and calculate L1 ⋅ C7 C8 = 2 ⋅ ----------------------R3 The value for R3 has not to be very high (for example 10KΩ) so to limit the error due to an error amplifier input offset current. 4. Calculate R3 R p = --------------------------------------------2 L1 ⎛ ------------ ⋅ --------⎞ – 1 ⎝ ESR C7⎠ VO R1 = R p ⋅ -------------------------V ref, PWM Rp R2 = ---------------------------------V ref,PWM 1 – ------------------------VO 5. Finally calculate R4 = G C ⋅ R1 and 28/31 L1 ⋅ C7 C9 = 2 ⋅ ----------------------R4 L5953 7 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 22. PowerSO36 mechanical data and package dimensions DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.60 0.10 0.30 a2 MAX. 0.1417 0.0039 0.0118 3.30 0.1299 a3 0 0.10 b 0.22 0.38 0.0087 0.0150 c 0.23 0.32 0.0091 0.0126 D 15.80 16.00 0.6220 0.6299 D1 9.40 9.80 0.3701 0.3858 E 13.90 14.5 0.5472 0.5709 E1 10.90 11.10 0.4291 0.4370 2.90 0.1142 E2 E3 5.80 e 0.0039 0.2283 0.65 e3 0 H 15.50 h 0.8 0.2441 0.0256 11.05 G L 6.20 OUTLINE AND MECHANICAL DATA 0.4350 0.10 0.0039 15.90 0.6102 0.6260 1.10 0.0433 1.10 0.0315 N 10˚ (max) s 8˚ (max) 0.0433 PowerSO-36 Note: “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions are "a3", "E" and "G". 0096119 C 29/31 Revision history 8 L5953 Revision history Table 13. 30/31 Document revision history Date Revision Changes 25-Mar-2003 1 Initial release. 04-Sep-2007 2 Layout changes and text mofifications. L5953 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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