VIPER27 Off-line high voltage converters Features ■ 800 V avalanche rugged power section ■ PWM operation with frequency jittering for low EMI ■ Operating frequency: – 60 kHz for L type – 115 kHz for H type SO16 narrow DIP-7 SO 16 Description ■ Standby power < 50 mW at 265 Vac ■ Limiting current with adjustable set point ■ Adjustable and accurate overvoltage protection ■ On-board soft-start ■ Safe auto-restart after a fault condition ■ Hysteretic thermal shutdown The device is an off-line converter with an 800 V rugged power section, a PWM control, two levels of over-current protection, overvoltage and overload protections, hysteretic thermal protection, soft-start and safe auto-restart after any fault condition removal. Burst mode operation and device very low consumption help to meet the standby energy saving regulations. Application ■ Auxiliary power supply for consumer and home equipments ■ ATX auxiliary power supply ■ Low / medium power AC-DC adapters ■ SMPS for set-top boxes, DVD players and recorders, white goods Advance frequency jittering reduces EMI filter cost. Brown-out function protects the switch mode power supply when the rectified input voltage level is below the normal minimum level specified for the system. The high voltage start-up circuit is embedded in the device. Figure 1. Typical topology + + DC input high voltage wide range DC Output voltage DRAIN DRAIN BR VIPER27 GND Table 1. VDD CONT FB Device summary Order codes Package VIPER27LN / VIPER27HN DIP-7 Packaging Tube VIPER27HD / VIPER27LD SO16 narrow VIPER27HDTR / VIPER27LDTR July 2010 Tape and reel Doc ID 15133 Rev 5 1/31 www.st.com 31 Contents VIPER27 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 Power-up and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 Auto restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7 Current mode conversion with adjustable current limit set point . . . . . . . 18 7.8 Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10 Feed-back and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 23 7.12 Brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.13 2nd level over current protection and hiccup mode . . . . . . . . . . . . . . . . . 25 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/31 Doc ID 15133 Rev 5 VIPER27 Block diagram 1 Block diagram Figure 2. Block diagram VDD VDD Vcc BR DRAIN + Vin_OK VBRth Internal Supply bus & Ref erence Voltages SUPPLY & UVLO HV_ON I DDch 15uA UVLO SOFT START OCP BLOCK - CONT OTP OCP BURST + . OVP LOGIC + THERMAL SHUTDOWN OSCILLATOR PWM TURN-ON LOGIC LEB S Q R1 R2 6uA + OVP 2nd OCP LOGIC Ref OLP OVP OTP Rsense BURST-MODE LOGIC BURST FB GND 2 Typical power Table 2. Typical power 230 VAC Part number VIPER27 85-265 VAC Adapter(1) Open frame(2) Adapter(1) Open frame(2) 18 W 20 W 10 W 12 W 1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient. 2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking. Doc ID 15133 Rev 5 3/31 Pin settings 3 VIPER27 Pin settings Figure 3. Note: Connection diagram (top view) The copper area for heat dissipation has to be designed under the DRAIN pins. Table 3. Pin description Pin n. Name SO16N 1 1...2 GND This pin represents the device ground and the source of the power section. - 4 N.A. Not available for user. It can be connected to GND (pins 1-2) or left not connected. 2 5 VDD Supply voltage of the control section. This pin also provides the charging current of the external capacitor during start-up time. 3 4 5 7,8 4/31 Function DIP7 6 7 8 Control pin. The following functions can be selected: 1. current limit set point adjustment. The internal set default value of the cycle-by-cycle current limit can be reduced by connecting to ground an CONT external resistor. 2. output voltage monitoring. A voltage exceeding VOVP threshold (see Table 8 on page 7) shuts the IC down reducing the device consumption. This function is strobed and digitally filtered for high noise immunity. FB Control input for duty cycle control. Internal current generator provides bias current for loop regulation. A voltage below the threshold VFBbm activates the burst-mode operation. A level close to the threshold VFBlin means that we are approaching the cycle-by-cycle over-current set point. BR Brownout protection input with hysteresis. A voltage below the threshold VBRth shuts down (not latch) the device and lowers the power consumption. Device operation restarts as the voltage exceeds the threshold VBRth + VBRhyst. It can be connected to ground when not used. High voltage drain pin. The built-in high voltage switched start-up bias 13...16 DRAIN current is drawn from this pin too. Pins connected to the metal frame to facilitate heat dissipation. Doc ID 15133 Rev 5 VIPER27 Electrical data 4 Electrical data 4.1 Maximum ratings Table 4. Absolute maximum ratings Value Symbol Parameter Unit Min VDRAIN Drain-to-source (ground) voltage 800 V EAV Repetitive avalanche energy (limited by TJ = 150 °C) 5 mJ IAR Repetitive avalanche current (limited by TJ = 150 °C) 1.5 A 3 A IDRAIN Pulse drain current (limited by TJ = 150 °C) VCONT Control input pin voltage (with ICONT = 1 mA) -0.3 Self limited V VFB Feed-back voltage -0.3 5.5 V VBR Brown-out input pin voltage (with IBR = 0.5 mA) -0.3 Self limited V VDD Supply voltage (IDD = 25 mA) -0.3 Self limited V IDD Input current 25 mA Power dissipation at TA < 40 °C (DIP-7) 1 PTOT TJ TSTG 4.2 Max W Power dissipation at TA < 60 °C (SO16N) 1.5 Operating junction temperature range -40 150 °C Storage temperature -55 150 °C Thermal data Table 5. Thermal data Max value Symbol Parameter Unit SO16N DIP7 RthJP Thermal resistance junction pin (Dissipated power = 1 W) 25 35 °C/W RthJA Thermal resistance junction ambient (Dissipated power = 1 W) 60 100 °C/W RthJA Thermal resistance junction ambient (1) (Dissipated power = 1 W) 50 80 °C/W 1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq in) of Cu (35 µm thick) Doc ID 15133 Rev 5 5/31 Electrical data 4.3 VIPER27 Electrical characteristics (TJ = -25 to 125 °C, VDD = 14 V(a); unless otherwise specified) Table 6. Power section Symbol Parameter VBVDSS Break-down voltage IDRAIN = 1 mA, VFB = GND TJ = 25 °C OFF state drain current VDRAIN = max rating, VFB = GND 60 μA IDRAIN = 0.4 A, VFB = 3 V, VBR = GND, TJ = 25 °C 7 Ω IDRAIN = 0.4 A, VFB = 3 V, VBR = GND, TJ = 125 °C 14 Ω IOFF RDS(on) COSS Table 7. Symbol Drain-source on state resistance Effective (energy related) output capacitance Test condition Min Typ Max Unit 800 VDRAIN = 0 to 640 V V 40 pF Supply section Parameter Test condition Min Typ Max Unit Voltage VDRAIN_START Drain-source start voltage IDDch VDD VDDclamp Start up charging current VDRAIN = 120 V, VBR = GND, VFB = GND, VDD = 4 V 60 80 100 V -2 -3 -4 mA VDRAIN = 120 V, VBR = GND, VFB = GND, VDD = 4 V after fault. -0.4 -0.6 -0.8 Operating voltage range After turn-on 8.5 VDD clamp voltage IDD = 20 mA 23.5 23.5 mA V V 13 14 15 V 7.5 8 8.5 V 4 4.5 5 V VFB = GND, FSW = 0 kHz, VBR = GND, VDD = 10 V 0.9 mA VDRAIN = 120 V, FSW = 60 kHz 2.5 mA VDRAIN = 120 V, FSW = 115 kHz 3.5 mA 400 μA 270 μA VDDon VDD start up threshold VDDoff VDD under voltage shutdown threshold VDD(RESTART) VDD restart voltage threshold VDRAIN = 120 V, VBR = GND, VFB = GND IDD0 Operating supply current, not switching IDD1 Operating supply current, switching IDD_FAULT Operating supply current, with protection tripping IDD_OFF Operating supply current with VDD < VDD_OFF VDRAIN = 120 V, VBR = GND, VFB = GND Current VDD = 7 V a. Adjust VDD above VDDon start-up threshold before settings to 14 V. 6/31 Doc ID 15133 Rev 5 VIPER27 Table 8. Electrical data Controller section Symbol Parameter Test condition Min Typ Max Unit Feed-back pin VFBolp Over load shutdown threshold 4.5 4.8 5.2 V VFBlin Linear dynamics upper limit 3.2 3.5 3.7 V VFBbm Burst mode threshold Voltage falling 0.6 V VFBbmhys Burst mode hysteresis Voltage rising 100 mV -150 -200 -280 μA -3 μA IFB RFB(DYN) HFB VFB = 0.3 V Feed-back sourced current 3.3 V < VFB < 4.8 V Dynamic resistance VFB < 3.3 V ΔVFB / ΔID 14 21 kΩ 2 6 V/A CONT pin ICONT = -100 µA VCONT_l Low level clamp voltage 0.5 V Current limitation IDlim Max drain current limitation tSS Soft-start time TON_MIN td tLEB ID_BM VFB = 4 V, ICONT = -10 µA TJ = 25 °C 0.66 0.7 0.74 8.5 Minimum turn ON time 220 400 A ms 480 ns Propagation delay 100 ns Leading edge blanking 300 ns 160 mA Peak drain current during burst mode VFB = 0.6 V Oscillator section VDD = operating voltage range, VFB = 1 V VIPER27L FOSC VIPER27H FD 60 66 kHz 103 115 127 kHz VIPER27L ±4 kHz VIPER27H ±8 kHz 250 Hz Modulation depth FM Modulation frequency DMAX Maximum duty cycle Over current protection IDMAX 54 70 80 % (2nd OCP) Second over current threshold 1 A Overvoltage protection VOVP TSTROBE Overvoltage protection threshold 2.7 Overvoltage protection strobe time 3 2.2 Doc ID 15133 Rev 5 3.3 V us 7/31 Electrical data Table 8. VIPER27 Controller section (continued) Symbol Parameter Test condition Min Typ Max Unit Brown out protection VBRth Brown out threshold Voltage falling 0.41 0.45 0.49 V VBRhyst Voltage hysteresis above VBRth Voltage rising 50 mV IBRhyst Current hysteresis VBRclamp VDIS Clamp voltage 7 IBR = 250 µA Brown out disable voltage 12 3 50 μA V 150 mV Thermal shutdown TSD THYST 8/31 Thermal shutdown temperature 150 Thermal shutdown hysteresis Doc ID 15133 Rev 5 160 °C 30 °C VIPER27 Electrical data Figure 4. Minimum turn-on time test circuit VDRAIN 14 V GND DRAIN VDD DRAIN 90 % TONmin 50 Ω CONT 10 % IDRAIN BR FB 30 V 3.5 V Time IDLIM Time Figure 5. Brown out threshold test circuit VBR GND DRAIN VBRth+VBRhyst VBRth VDD DRAIN VDIS IBR Time IDRAIN Time 10 kΩ CONT IBRhyst IBRhyst BR FB 14 V 30 V 2V Time Figure 6. OVP threshold test circuit VCONT 14 V GND DRAIN VDD DRAIN CONT FB VOVP 10 kΩ VDRAIN BR Time 30 V 2V Time Note: Adjust VDD above VDDon start-up threshold before settings to 14 V Doc ID 15133 Rev 5 9/31 Typical electrical characteristics 5 VIPER27 Typical electrical characteristics Figure 7. Current limit vs TJ Figure 8. Figure 9. Drain start voltage vs TJ Figure 10. HFB vs TJ Figure 11. Brown out threshold vs TJ 10/31 Switching frequency vs TJ Figure 12. Brown out hysteresis vs TJ Doc ID 15133 Rev 5 VIPER27 Typical electrical characteristics Figure 13. Brown out hysteresis current Figure 14. Operating supply current vs TJ (no switching) vs TJ Figure 15. Operating supply current (switching) vs TJ Figure 16. current limit vs RLIM Figure 17. Power MOSFET on-resistance Figure 18. Power MOSFET break down vs TJ voltage vs TJ Doc ID 15133 Rev 5 11/31 Typical electrical characteristics VIPER27 Figure 19. Thermal shutdown VDD VDDon VDDoff VDD(RESTART) time IDRAIN time TJ TSD TSD - THYST Normal operation 12/31 Shut down after over temperature Doc ID 15133 Rev 5 Normal operation time VIPER27 6 Typical circuit Typical circuit Figure 20. Min-features flyback application D3 AC IN R1 C2 BR Vout C1 C5 AC IN D1 GND D2 R2 R3 VVcc DD OPTO DRAIN R5 BR CONTROL C3 R4 CONT FB C6 GND SOURCE U2 C4 R6 Figure 21. Full-features flyback application D3 Rh AC IN BR C2 Vout R1 C1 C5 Rl AC IN D1 GND Daux Rov p D2 R2 R3 VVcc DD DRAIN OPTO R5 BR CONTROL C3 R4 CONT FB C6 GND SOURCE U2 Rlim C4 Doc ID 15133 Rev 5 R6 13/31 Operation descriptions 7 VIPER27 Operation descriptions VIPER27 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche rugged Power section. The controller includes: the oscillator with jittering feature, the start up circuits with soft-start feature, the PWM logic, the current limit circuit with adjustable set point, the second over current circuit, the burst mode management, the brown-out circuit, the UVLO circuit, the auto-restart circuit and the thermal protection circuit. The current limit set-point is set by the CONT pin. The burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment. All the fault protections are built in auto restart mode with very low repetition rate to prevent IC's over heating. 7.1 Power section and gate driver The power section is implemented with an avalanche ruggedness N-channel MOSFET, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. The power section has a BVDSS of 800 V min. and a typical RDS(on) of 7 Ω at 25 °C. The integrated SenseFET structure allows a virtually loss-less current sensing. The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. 7.2 High voltage startup generator The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than VDRAIN_START threshold, 80 VDC typically. When the HV current generator is ON, the IDDch current (3 mA typical value) is delivered to the capacitor on the VDD pin. In case of auto restart mode after a fault event, the IDDch current is reduced to 0.6 mA, in order to have a slow duty cycle during the restart phase. 14/31 Doc ID 15133 Rev 5 VIPER27 7.3 Operation descriptions Power-up and soft-start up If the input voltage rises up till the device start threshold, VDRAIN_START, the VDD voltage begins to grow due to the IDDch current (see Table 7 on page 6) coming from the internal high voltage start up circuit. If the VDD voltage reaches VDDon threshold (see Table 7 on page 6) the power MOSFET starts switching and the HV current generator is turned OFF. See Figure 23 on page 16. The IC is powered by the energy stored in the capacitor on the VDD pin, CVDD, until when the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. CVDD capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than VDDoff threshold. In fact, a too low capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding. The following formula can be used for the VDD capacitor calculation: Equation 1 I DDch × tSSaux C VDD = ---------------------------------------V DDon – V DDoff The tSSaux is the time needed for the steady state of the auxiliary voltage. This time is estimated by applicator according to the output stage configurations (transformer, output capacitances, etc.). During the converter start up time, the drain current limitation is progressively increased to the maximum value. In this way the stress on the secondary diode is considerably reduced. It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the feature is implemented for every attempt of start up converter or after a fault. Figure 22. IDD current during start-up and burst mode VDD VDDon VDDoff t VFB VFBolp VFBlin VFBbmhys VFBbm t VDRAIN t IDD IDD1 IDD0 t IDDch (-3 mA) START- UP NORMAL MODE Doc ID 15133 Rev 5 BURST MODE NORMAL MODE 15/31 Operation descriptions VIPER27 Figure 23. Timing diagram: normal power-up and power-down sequences VIN VIN < VDRAIN_START HV startup is no more activated VDRAIN_START VDD regulation is lost here time VDDon VDDoff VDD(RESTART) VDRAIN time IDD time IDDch (3mA) Normal operation Power-on time Power-off Figure 24. Soft-start: timing diagram IDRAIN IDlim t VFB VFBolp VFBlin t VOUT t tSS 16/31 ( SOFT START- UP ) DELAY (OLP) Doc ID 15133 Rev 5 STEADY STATE VIPER27 7.4 Operation descriptions Power down operation At converter power down, the system loses regulation as soon as the input voltage is so low that the peak current limitation is reached. The VDD voltage drops and when it falls below the VDDoff threshold (see Table 7 on page 6) the power MOSFET is switched OFF, the energy transfers to the IC interrupted and consequently the VDD voltages decreases, Figure 23 on page 16. Later, if the VIN is lower than VDRAIN_START (see Table 7 on page 6), the start up sequence is inhibited and the power down completed. This feature is useful to prevent converter’s restart attempts and ensures monotonic output voltage decay during the system power down. 7.5 Auto restart operation If after a converter power down, the VIN is higher than VDRAIN_START, the start up sequence is not inhibited and will be activated only when the VDD voltage drops down the VDD(RESTART) threshold (see Table 7 on page 6). This means that the HV start up current generator restarts the VDD capacitor charging only when the VDD voltage drops below VDD(RESTART). The scenario above described is for instance a power down because of a fault condition. After a fault condition, the charging current, IDDch, is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal start up converter phase. This feature together with the low VDD(RESTART) threshold ensures that, after a fault, the restart attempts of the IC has a very long repetition rate and the converter works safely with extremely low power throughput. The Figure 25 shows the IC behavioral after a short circuit event. Figure 25. Timing diagram: behavior after short circuit 6$$ 6KRUWFLUFXLWRFFXUVKHUH 9'' RQ 9''RII 9''5(67$57 7UHS 6$2!). W 7UHS W W )$$ )$$CHM! 6&" W 6&"OLP 6&"LIN W 7.6 Oscillator The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz (115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of sideband harmonics having the same energy on the whole but smaller amplitudes. Doc ID 15133 Rev 5 17/31 Operation descriptions 7.7 VIPER27 Current mode conversion with adjustable current limit set point The device is a current mode converter: the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. This voltage is compared with the one on the feed-back pin through a voltage divider on cycle by cycle basis. The VIPER27 has a default current limit value, IDlim, that the designer can adjust according the electrical specification, by the RLIM resistor connected to the CONT see Figure 16 on page 11. The CONT pin has a minimum current sunk needed to activate the IDlim adjustment: without RLIM or with high RLIM (i.e. 100 kΩ) the current limit is fixed to the default value (see IDlim, Table 8 on page 7). 7.8 Overvoltage protection (OVP) The VIPER27 has integrated the logic for the monitor of the output voltage using as input signal the voltage VCONT during the OFF time of the power MOSFET. This is the time when the voltage from the auxiliary winding tracks the output voltage, through the turn ratio N AUX -------------N SEC The CONT pin has to be connected to the auxiliary winding through the diode DOVP and the resistors ROVP and RLIM as shows the Figure 27 on page 20 When, during the OFF time, the voltage VCONT exceeds, four consecutive times, the reference voltage VOVP (see Table 8 on page 7) the overvoltage protection will stop the power MOSFET and the converter enters the auto-restart mode. In order to bypass the noise immediately after the turn off of the power MOSFET, the voltage VCONT is sampled inside a short window after the time TSTROBE, see Table 8 on page 7 and the Figure 26 on page 19. The sampled signal, if higher than VOVP, trigger the internal OVP digital signal and increments the internal counter. The same counter is reset every time the signal OVP is not triggered in one oscillator cycle. Referring to the Figure 21, the resistors divider ratio kOVP will be given by: Equation 2 V OVP k OVP = -------------------------------------------------------------------------------------------------N AUX -------------- ⋅ ( V OUTOVP + V DSEC ) – V DAUX N SEC Equation 3 R LIM k OVP = --------------------------------R LIM + R OVP 18/31 Doc ID 15133 Rev 5 VIPER27 Operation descriptions Where: ● VOVP is the OVP threshold (see Table 8 on page 7) ● VOUT OVP is the converter output voltage value to activate the OVP set by designer ● NAUX is the auxiliary winding turns ● NSEC is the secondary winding turns ● VDSEC is the secondary diode forward voltage ● VDAUX is the auxiliary diode forward voltage ● ROVP together RLIM make the output voltage divider Than, fixed RLIM, according to the desired IDlim, the ROVP can be calculating by: Equation 4 1 – k OVP R OVP = R LIM × ----------------------k OVP The resistor values will be such that the current sourced and sunk by the CONT pin be within the rated capability of the internal clamp. Figure 26. OVP timing diagram VDS t VAUX 0 VCONT t V OVP t 2 µs STROBE 0.5 µs t OVP t COUNTER RESET COUNTER STATUS t 0 0 0 0 →1 1 →2 2 →0 0 0 →1 1 →2 2 →3 FAULT 3 →4 t NORMAL OPERATION TEMPORARY DISTURBANCE Doc ID 15133 Rev 5 FEEDBACK LOOP FAILURE t 19/31 Operation descriptions 7.9 VIPER27 About CONT pin Referring to the Figure 27, through the CONT pin, the below features can be implemented: 1. Current limit set point 2. Over voltage protection on the converter output voltage The Table 9 on page 20 referring to the Figure 27, lists the external components needed to activate one or plus of the CONT pin functions. Figure 27. CONT pin configuration R OV P CONT SOFT START OCP BLOCK - Daux + Auxiliary winding OVP LOGIC R LIM OCP to GATE driver From RSENSE OVP Table 9. CONT pin configurations Function / component RLIM (1) ROVP DAUX IDlim reduction See Figure 16 No No OVP ≥ 80 kΩ See Equation 4 Yes IDlim reduction + OVP See Figure 16 See Equation 4 Yes 1. RLIM has to be fixed before of ROVP 7.10 Feed-back and overload protection (OLP) The VIPER27 is a current mode converter: the feedback pin controls the PWM operation, controls the burst mode and actives the overload protection. Figure 28 on page 22 and Figure 29 show the internal current mode structure. With the feedback pin voltage between VFBbm and VFBlin, (see Table 8 on page 7) the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. See Figure 2 on page 3. This voltage is compared with the one on the feedback pin through a voltage divider on cycle by cycle basis. When these two voltages are equal, the PWM logic orders the switch off of the power MOSFET. The drain current is always limited to IDlim value. In case of overload the feedback pin increases in reaction to this event and when it goes higher than VFBlin, the PWM comparator is disabled and the drain current is limited to IDlim by the OCP comparator, seeFigure 2 on page 3. 20/31 Doc ID 15133 Rev 5 VIPER27 Operation descriptions When the feedback pin voltage reaches the threshold VFBlin an internal current generator starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the VFBolp threshold, the converter is turned off and the start up phase is activated with reduced value of IDDch to 0.6 mA, see Table 7 on page 6. During the first start up phase of the converter, after the soft-start up time, tSS, the output voltage could force the feedback pin voltage to rise up to the VFBolp threshold that switches off the converter itself. To avoid this event, the appropriate feedback network has to be selected according to the output load. More the network feedback fixes the compensation loop stability. The Figure 28 on page 22 and Figure 29 show the two different feedback networks. The time from the over load detection (VFB = VFBlin) to the device shutdown (VFB = VFBolp) can be set by CFB value (see Figure 28 on page 22 and Figure 29), using the formula: Equation 5 V FBolp – V FBlin T OLP – delay = C FB × ---------------------------------------3μA In the Figure 28, the capacitor connected to FB pin (CFB) is part of the compensation circuit as well as it needs to activate the over load protection (see equation 5). After the start up time, tSS, during which the feedback voltage is fixed at VFBlin, the output capacitor could not be at its nominal value and the controller interprets this situation as an over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down during the start up phase. Owing to the above considerations, the OLP delay time must be long enough to by-pass the initial output voltage transient and check the over load condition only when the output voltage is in steady state. The output transient time depends from the value of the output capacitor and from the load. When the value of the CFB capacitor calculated for the loop stability is too low and cannot ensure enough OLP delay, an alternative compensation network can be used and it is showed in Figure 29 on page 22. Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are introduced by the capacitors CFB and CFB1 and the resistor RFB1. The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole is usually used to compensate the high frequency zero due to the ESR (equivalent series resistor) of the output capacitance of the fly-back converter. The mathematical expressions of these poles and zero frequency, considering the scheme in Figure 29 are reported by the equations below: Equation 6 fZFB = 1 2 ⋅ π ⋅ CFB1 ⋅ RFB1 Doc ID 15133 Rev 5 21/31 Operation descriptions VIPER27 Equation 7 fPFB = RFB(DYN) + RFB1 2 ⋅ π ⋅ CFB ⋅ RFB(DYN) ⋅ RFB1 ( ) 1 2 ⋅ π ⋅ CFB1 ⋅ RFB1 + RFB(DYN) ) Equation 8 fPFB1 = ( The RFB(DYN) is the dynamic resistance seen by the FB pin. The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. The Equation 5 can be still used to calculate the OLP delay time but CFB1 has to be considered instead of CFB. Using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough OLP delay time alike. Figure 28. FB pin configuration From sense FET PWM To PWM Logic + PWM CONTROL - Cfb BURST BURST-MODE LOGIC BURST-MODE REFERENCES OLP comparator To disable logic + - 4.8V Figure 29. FB pin configuration From sense FET PWM To PWM Logic + PWM CONTROL - Rfb1 Cfb BURST Cfb1 BURST-MODE REFERENCES BURST-MODE LOGIC OLP comparator + 4.8V 22/31 Doc ID 15133 Rev 5 - To disable logic VIPER27 7.11 Operation descriptions Burst-mode operation at no load or very light load When the load decrease the feedback loop reacts lowering the feedback pin voltage. If it falls down the burst mode threshold, VFBbm, the power MOSFET is not more allowed to be switched on. After the MOSFET stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding the level, VFBbm + VFBbmhys, the power MOSFET starts switching again. The burst mode thresholds are reported on Table 8 and Figure 30 shows this behavior. Systems alternates period of time where power MOSFET is switching to period of time where power MOSFET is not switching; this device working mode is the burst mode. The power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. The advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. During the burst-mode the drain current peak is clamped to the level, ID_BM, reported on Table 8. Figure 30. Burst mode timing diagram, light load management VFB 100 50 mV hyster. VFBbm t IDRAIN Normal -mode 7.12 Burst-mode Normal -mode t Brown-out protection Brown-out protection is a not-latched shutdown function activated when a condition of mains under voltage is detected. The Brown-out comparator is internally referenced to VBRth threshold, see Table 8 on page 7, and disables the PWM if the voltage applied at the BR pin is below this internal reference. Under this condition the power MOSFET is turned off. Until the Brown out condition is present, the VDD voltage continuously oscillates between the VDDon and the UVLO thresholds, as shown in the timing diagram of Figure 31 on page 24. A voltage hysteresis is present to improve the noise immunity. The switching operation is restarted as the voltage on the pin is above the reference plus the before said voltage hysteresis. See Figure 5 on page 9. The Brown-out comparator is provided also with a current hysteresis, IBRhyst. The designer has to set the rectified input voltage above which the power MOSFET starts switching after brown out event, VINon, and the rectified input voltage below which the power MOSFET is switched off, VINoff. Thanks to the IBRhyst, see Table 8 on page 7, these two thresholds can be set separately. Doc ID 15133 Rev 5 23/31 Operation descriptions VIPER27 Figure 31. Brown-out protection: BR external setting and timing diagram VIN VINon VINoff VBR t VBRth VDD Vcc VIN t VDIS Rh Vin_OK + - t IBR AC_OK Disable IBRhyst BR + VDDon - VBRth VDD Vin_OK t VDDoff IBRhyst Rl t VDRAIN t VOUT t Fixed the VINon and the VINoff levels, with reference to Figure 31, the following relationships can be established for the calculation of the resistors RH and RL: Equation 9 RL = − VBRhyst IBRhyst + VINon − VINoff − VBRhyst VINoff − VBRth × VBRth IBRhyst Equation 10 RH = VINon − V INoff − V BRhyst I BRhyst × RL + RL V BRhyst I BRhyst For a proper operation of this function, VIN on must be less than the peak voltage at minimum mains and VIN off less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load. The BR pin is a high impedance input connected to high value resistors, thus it is prone to pick up noise, which might alter the OFF threshold when the converter operates or gives origin to undesired switch-off of the device during ESD tests. It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind. If the brown-out function is not used the BR pin has to be connected to GND, ensuring that the voltage is lower than the minimum of VDIS threshold (50 mV, see Table 8). In order to enable the brown-out function the BR pin voltage has to be higher than the maximum of VDIS threshold (150 mV, see Table 8). 24/31 Doc ID 15133 Rev 5 VIPER27 7.13 Operation descriptions 2nd level over current protection and hiccup mode The VIPER27 is protected against short circuit of the secondary rectifier, short circuit on the secondary winding or a hard-saturation of fly-back transformer. Such as anomalous condition is invoked when the drain current exceed the threshold IDMAX, see Table 8 on page 7. To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a “warning state” is entered after the first signal trip. If in the subsequent switching cycle the signal is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the IDMAX threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power MOSFET is turned OFF. The shutdown condition is latched as long as the device is supplied. While it is disabled, no energy is transferred from the auxiliary winding; hence the voltage on the VDD capacitor decays till the VDD under voltage threshold (VDDoff), which clears the latch. The start up HV current generator is still off, until VDD voltage goes below its restart voltage, VDD(RESTART). After this condition the VDD capacitor is charged again by 600 µA current, and the converter switching restarts if the VDDon occurs. If the fault condition is not removed the device enters in auto-restart mode. This behavioral results in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. See the timing diagram of Figure 32. Figure 32. Hiccup-mode OCP: timing diagram VDD Vcc Secondary diode is shorted here VDDon VDD off VDD (RESTART) t IDRAIN IDMAX t VDRAIN t Doc ID 15133 Rev 5 25/31 Package mechanical data 8 VIPER27 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 10. DIP-7 mechanical data mm Dim. Min. Typ. A 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.26 E1 6.10 6.35 7.11 e 2.54 eA 7.62 eB L 10.92 2.92 M N 3.30 3.81 2.508 0.40 0.50 N1 0.60 0.60 O 26/31 Max. 0.548 Doc ID 15133 Rev 5 VIPER27 Package mechanical data Figure 33. Package dimensions Doc ID 15133 Rev 5 27/31 Package mechanical data Table 11. VIPER27 SO16 narrow mechanical data mm Dim. Min. Typ. A 1.75 A1 0.1 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.8 9.9 10 E 5.8 6 6.2 E1 3.8 3.9 4 e 0.25 1.27 h 0.25 0.5 L 0.4 1.27 k 0 8 ccc 28/31 Max. 0.1 Doc ID 15133 Rev 5 VIPER27 Package mechanical data Figure 34. SO16 narrow mechanical data Doc ID 15133 Rev 5 29/31 Revision history 9 VIPER27 Revision history Table 12. 30/31 Document revision history Date Revision Changes 16-Jan-2009 1 Initial release 20-Jul-2009 2 Added SO16 narrow package. 22-Oct-2009 3 Updated Table 5 on page 5. 16-Jun-2010 4 Updated Figure 3 on page 4 and Table 3 on page 4. 30-Jul-2010 5 Updated Figure 11, Figure 12 and Figure 13. Doc ID 15133 Rev 5 VIPER27 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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