L5953 MULTIPLE SWITCHING VOLTAGE REGULATOR PRODUCT PREVIEW ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PWM: ADJUSTABLE 2.5/10V - 1A SWITCHING VOLTAGE REGULATOR EXTERNAL POWER MOS ABILITY FOR OUTPUT CURRENT ENHANCEMENT SYNCHRONIZATION FUNCTION REG1- LINEAR LOW DROP 3.3/5V - 250mA STBY VOLTAGE REGULATOR (LOW CURRENT CONSUMPTION) with RESET REG2- LINEAR VOLTAGE REGULATOR 1.5V to 3.3V EXTERNALLY ADJUSTABLE - 300mA MAXIMUM CURRENT HSD1 : 500mA HIGH SIDE DRIVER HSD2 : 200mA HIGH SIDE DRIVER SPI INTERFACE SPI DIAGNOSTICS HSD1, HSD2 DOUBLE SWITCHING FREQUENCY SPI SELECTABLE DOUBLE INPUT LVW SPI FUNCTIONS ■ INPUT CONTROLS – Turn-on/off PWM – Turn-on/off REG2 – Turn-on/off HSD1 – Turn-on/off HSD2 – Switching frequency selection f1- f2 ■ OUTPUT FUNCTIONS: PowerSO36 ORDERING NUMBER: L5953 – HSD1 & HSD2 short to gnd, open load and short to battery (Test mode) – Thermal warning PROTECTIONS ■ OVERVOLTAGE PROTECTION ■ INTERNAL CURRENT LIMITING ■ THERMAL SHUTDOWN ■ ESD DESCRIPTION The L5953 is the integration of one switching regulator, two linear voltage regulators, two low voltage warnings and two high side drivers. It has a stand-by operation mode (low current consumption) where only the stand-by voltage regulator plus the low voltage warnings are active. The other regulators and high side drivers are controlled by the SPI interface. BLOCK DIAGRAM S1 W1 S2 W2 VDD-LIN STCAP VDD-SW CT RES FGND REC1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA VOLTAGE WARNING VSTBY ADJ HSD1 HSD1 STRAP PWM STEP DOWN REGULATOR 2.5-10V/1A HSD2 HSD2 DRAINOUT VSW GATEIN GATEOUT FB VSPI REC2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA SPI INTERFACE IRQ COMP OSCILLATOR & SYNC SWGND GND Q D S C VLR FBLR VIN SYNC DGND D01AU1330A September 2003 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/24 L5953 ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter DC Operating Supply Voltage Value Unit -0.6 to 30 V 50 V -0.6 to 6 V Transient Supply Overvoltage (250ms) VSPI IO Supply Voltage for SPI I/O Voltage Regulator Output Current Internally limited Vinlog Input Voltage (C,D,Q,S,SYNC) RESR Output Capacitor Series Eq. Resistance (Linear reg.)(Allowed range) 0 to 6 V From 0.2 to 10 Ω Top Operating Temperature Range -40 to 85 °C Tstg Storage Temperature Ranges -55 to 150 °C Operative Junction Temperature -40 to 150 °C Value Unit 1.7 °C/W Tj THERMAL DATA Symbol Parameter Rthj-case Thermal Resistance Junction to Case PIN CONNECTION FGND 1 36 ADJ S2 2 35 VSTBY S1 3 34 VSPI W2 4 33 STCAP W1 5 32 FB RES 6 31 COMP CT 7 30 FBLR D 8 29 VIN C 9 28 VLR Q 10 27 SYNC S 11 26 STRAP DGND 12 25 GATEOUT IRQ 13 24 GATEIN HSD2 14 23 VSW VDD-LIN 15 22 GND N.C. 16 21 N.C. HSD1 17 20 DRAINOUT SWGND 18 19 VDD-SW D02AU1345A 2/24 L5953 PIN FUNCTION Pin Number Pin Name Function 1 FGND Analog Ground 2 S2 Input Voltage for LVW2 3 S1 Input Voltage for LVW1 4 W2 LVW2 Output 5 W1 LVW1 Output 6 RES Reset 7 CT Timing capacitor 8 D SPI Serial Input 9 C SPI Clock 10 Q SPI Serial Output 11 S SPI Chip Select 12 DGND SPI Ground 13 IRQ Interrupt 14 HSD2 HSD2 Output 15 VDD-LIN Battery 16 N.C. Not Connected 17 HSD1 HSD1 Output 18 SWGND Switching Ground 19 VDD-SW PWM Battery 20 DRAINOUT Drain of the exrternal MOS 21 N.C. Not Connected 22 GND Ground 23 VSW Source of the external MOS 24 GATEIN Gate of the internal MOS 25 GATEOUT Switching Output for power mos gate 26 STRAP Bootstrap 27 SYNC Synchronization 28 VLR REG2 Linear Voltage Regulator Output 29 VIN REG2 Linear Voltage Regulator Input 30 FBLR REG2 Linear Voltage Regulator Feedback 31 COMP PWM Compensation 32 FB PWM Feedback 33 STCAP ST-CAP 34 VSPI Supply Voltage for SPI I/O 35 VSTBY REG1 Stand-by Linear Voltage Regulator Output 36 ADJ 3.3V/5V REG1 Voltage Select 3/24 L5953 ELECTRICAL CHARACTERISTCS ( Tamb = 25°C, VDD = 14.4V) Symbol Parameter IQ,STBY Quiescent current with regulators and High-side drivers off Tsd Test Condition Min. Typ. W1, W2, RES, IRQ, not active; REG2, HSD1, HSD2, PWM off; S, C, D fixed at high/low logic level Thermal Shutdown Junction Temperature Max. Unit 100 µA 150 °C SMPS.PWM Tamb = 25°C, VDD = 14.4V, Vo = 5V; unless otherwise specified.) Vo,min Minimum Output Voltage Io = 200mA 2.4 2.5 2.6 V Vo,max Maximum Output Voltage Io = 200mA 9.6 10 10.4 V Vref,PWM Vi Voltage Reference 1.275 Input Voltage Range Vo = 5V; Io = 0.5A ∆Vo Line Regulation ∆Vo Vd 6 18 V Io = 0.5A 100 mV Load Regulation Vo = 5V; Io = 0.2A to 0.5A 50 mV Dropout Voltage between Pin 19 and Pin 23 Io = 0.5A, Vo = 5V 0.5 V 1 V Io = 1A, Vo = 5V ILim η SVR V Current Limit 1.5 A Efficiency f = 260kHz; Io = 0.5A f = 400kHz; Io = 0.5A 90 86 % % Supply Voltage Ripple Rejection ∆Vi = 1Vrms; fripple = 300Hz; Io = 0.4A 50 dB OSCILLATOR f1 Swiching frequency 249 260 271 kHz f2 Swiching frequency 384 400 416 kHz ∆f-------∆V i Voltage Stability of Switching Frequency VDD = 8 to 18V Tbd % ∆f-------∆T j Temperature Stability of Switching Frequency Tj = -40°C to 85°C Tbd % SYNC VIL Low Input Voltage VIH High Input Voltage VOL Low Output Voltage VOH High Output Voltage 4/24 0.8 2 V 0.4 ISOURCE=1.5mA 4 V V V L5953 ELECTRICAL CHARACTERISTCS (continued) ( Tamb = 25°C, VDD = 14.4V) Symbol Parameter Test Condition Min. Typ. Max. Unit ISLAVE Slave Sink Current 100 µA TW Output Pulse Width 300 ns REG1 - 3.3V/5V STBY LINEAR VOLTAGE REGULATOR VSTBY Output Voltage no load; ADJ pin = open no load; ADJ pin = VSTBY pin ∆Vline Line Regulation ∆Vload Vdropout Ilim SVR 4.9 3.20 5 3.3 5.1 3.4 V V no load; 7 < Vdd < 26V 5 50 mV Load Regulation 5mA < Io < 250mA 12 80 mV VSTCAP - VSTBY Io = 100mA, Vo = 5V Io = 100mA, Vo = 3.3V 0.36 0.47 0.5 0.65 V Current Limit Out short to GND Supply Voltage Rejection ∆VDD = 1Vrms: f = 300Hz Io = 250mA 300 mA 55 dB REG2 - LINEAR VOLTAGE REGULATOR 1.5V to 3.3V VLR VIN Linear Regulator Output Voltage Input Voltage no load; 4.75 ≤ VIN ≤ 16V; 1+ (R5/R6) = 2.588 3.2 3.3 3.4 no load; 3.135 ≤ VIN ≤ 16V; 1+ (R5/R6) = 1.176 1.45 1.5 1.55 IO = 150mA 1.5V ≤ VLR ≤ 2V 3.135 16 V IO = 300mA 1.5V ≤ VLR ≤ 3.3V 4.75 16 V V ∆Vload Load Regulation 5mA ≤ IO ≤ 300mA 4.75V ≤ VIN ≤ 16V; 1.5V ≤ VLR ≤ 3.3V 12 mV ∆Vline Line Regulation no load; 4.75V ≤ VIN ≤ 16V; 1.5V ≤ VLR ≤ 3.3V 1 mV 1.275 V Vref,REG2 Voltage Reference ILim Current Limit Out Short to ground 400 mA SVR Supply Voltage Rejection VIN = 5Vdc, 0.5Vacpp, 300Hz IO = 300mA; 1.5V ≤ VLR ≤ 3.3V 55 dB VIN = 3.3Vdc, 0.5Vacpp, 300Hz IO = 150mA; 1.5V ≤ VLR ≤ 2V 55 dB HSD1 Vsat, peak Saturation Voltage Ilim Lload Current Limit Load Inductance IO = 0.5A 250 600 mV mA 100 mH 5/24 L5953 ELECTRICAL CHARACTERISTCS (continued) ( Tamb = 25°C, VDD = 14.4V) Symbol Parameter Test Condition Min. Typ. Max. Unit 250 mV HSD2 Vsat, peak Saturation Voltage Ilim Lload IO = 0.2A Current Limit 300 mA Load Inductance 100 mH VOLTAGE WARNING Vst Sense Low Threshold 1.245 1.275 1.305 V Vsth Sense Threshold Hysteresis 35 45 60 mV VSL Sense Output Low Voltage Io = 1mA 0.4 V ISH Sense Output Leakage VW = 5V; VSI ≥ 1.5V 10 µA ISI Sense Input Current VSI=5V 1 µA RESET VRT Reset Threshold Voltage 0.95 x VSTBY V VRTH Reset Threhold Hysteresis 0.02 x VSTBY V VRL Reset Output Voltage Io = 1mA 0.4 V IRH Reset Output Leakage VRT = VSTBY 10 µA VCTth Delay Comparator Threshold 0.5 x VSTBY VCThy Delay Comparator Threshold Hysteresys 180 mV ICT1 Timing Capacitor Output Source Current 7.5 µA RCT2 Timing Capacitor Output PullDown equivalent Resistor 150 Ω DIAGNOSTIC PARAMETERS Symbol Parameter Test Condition HSD1W1 High Side Driver 1 Overcurrent Warning activation HSD1W2 High Side Driver 1 Open Load Warning activation HSD1 output voltage in test mode HSD1W2 High Side Driver 1 VDD Short TEST Warning activation in test mode HSD1 in test mode Measure VVDD-LIN-VHSD1 HSD2W1 High Side Driver 2 Overcurrent Warning activation 6/24 Min. Typ. Max. Unit 0.95 A 3 V 1.5 V 0.7 A L5953 Symbol Parameter Test Condition HSD2W2 High Side Driver 2 Open Load Warning activation HSD2 output voltage in test mode HSD2W3 High Side Driver 2 VDD Short Warning activation in test mode HSD2 in test mode Measure VVDD-LIN-VHSD1 THW Thermal warning activation Min. Typ. Max. Unit 3 V 1.5 V 145 °C IRQ - Interrupt Request Pin IRQ-L IRQ Low voltage Io = 1mA 0.4 V IRQ-H IRQ Leakage Virq = 5V 1 µA Min. Max. Unit 3 5.5 V SPI INTERFACE Symbol Alt Parameter Test Conditions Recommended DC Operating Voltage Supply Voltage for SPI I/O VSPI Input Parameters (Tamb = 25°C, f = 1MHz) CIN Input Capacitance (D) 8 pF CIN Input Capacitance (others pins) 6 pF tLPF Input Signal Pulse Width 10 ns 2 µA ±2 µA DC Characteristics (Tamb = -40 to 85°C, VSPI = 3V to 5.5V) ILI Input Leakage Current ILO Output Leakage Current VIL Input Low Voltage -0.3 0.3VSPI V VIH Input High Voltage 0.7VSPI VSPI+1 V VOL Output Low Voltage IOL = 2mA 0.2VSPI V VOH Output High Voltage IOH = -2mA 0.8VSPI V AC Characteristics (Tamb = -40 to 85°C, VSPI = 3V to 5.5V tSCLH tSU S Setup Time 50 ns tCLSH tSH S Hold Time 50 ns tCH tWH Clock High Time 200 ns tCL tWL Clock Low Time 300 ns tCLCH tRC Clock Rise Time 1 µs tCHCL tFC Clock Fall Time 1 µs tDVCH tDSU Data In Setup Time 50 ns tCHDX tDH Data In Hold Time 50 ns tDLDH tRI Data In Rise Time 1 µs 7/24 L5953 Symbol Alt Parameter Test Conditions Min. tDHDL tFI Data in Fall Time tSHSL tCS S Deselect Time tSHQZ tDIS Output Disable Time 150 ns tQVCL tV Clock Low to Output Valid 250 ns tCLQX tHO 4.5V < VSPI < 5.5V 3V < VSPI < 4.5V Max. Unit 1 µs 200 250 Output Hold Time ns ns 0 ns tQLQH tRO Output Rise Time 100 ns tQHQL tFO Output Fall Time 100 ns Figure 1. AC Testing Input Output WaveformsI 0.8VSPY 0.7VSPY 0.2VSPY 0.3VSPY D03AU1479 Figure 2. SPI Clocking Scheme S C C D Q 8/24 (MODE 0: CPOL=0,CPHA=0) (MODE 3: CPOL=1,CPHA=1) MSB 6 5 4 3 2 1 0 L5953 Figure 3. Output Timing S tCH C tCL tCLQX tSHQZ tQVCL MSB OUT Q MSB-1 OUT LSB OUT tQLQH tQHQL D ADDR.LSB IN (CPOL=0, CPHA=0) AI01070B Figure 4. Serial Input Timing tSHSL S tSLCH tCLSH C tDVCH tCHCL tCHDX tCLCH MSB IN D LSB IN HIGH IMPEDANCE tDLDH tDHDL Q (CPOL=0, CPHA=0) AI01071 FUNCTIONAL DESCRIPTION REG1 Stand-by Regulator (Figure 5) The stand-by regulator output voltage can be 5V or 3.3V. It is externally selectable by means of the ADJ pin: - leaving the ADJ pin open, the output voltage is 5V; - connecting the ADJ pin to the Vstby pin the output voltage becomes 3.3V. This regulator is supplied by STCAP pin and provide the reset information. It has a current protection which limits the maximum allowable output current. Reset (Figure 6) The RES pin is an open collector that is activated (that is forced to zero) when the stand-by regulator is not in regulation (including thermal shutdown and faults). The indication that REG1 is in regulation is delayed by a time 9/24 L5953 set up by the external capacitor CT. When the RES is switched on, HSD1, HSD2, REG2, PWM are turned off and until the RES is forced to zero only the REG1 and low Voltage Warnings are active. Low Voltage Warning(Figure 7) This circuit is able to sense two different voltages through external resistors to increase the overall flexibility. If S1 pin voltage is higher than Vst, the output mos M1 is off: W1 is floating and can be pulled up by an external resistor. If S1 pin voltage goes down and becomes lower than Vst, the mos M1 is turned on and forces W1 to zero. The same thing happens for S2 - W2. The outputs W1 and W2 can be connected together to get a single output. REG2 Linear Voltage Regulator (Figure 5) REG2 is a linear voltage regulator with a dedicated supply pin VIN. The output voltage (between 1.5V and 3.3V) is fixed by an external divider. It can be turned on/off by SPI. It has a current protection which limits the maximum allowable output current. High Side Drivers (Figure 8) Two high-side driver with charge pump controlled by SPI are available inside L5953. They are protected against short to ground: the short circuit potection limits the maximum output current. A diagnostic procedure is available to detect open load, short to battery and overcurrent. Open load and short to battery can be reveal only in test mode while overcurrent is active only during normal operationof the device. (see OPERATION -page 13 PWM Step Down Voltage Regulator (Figure 9) The switching regulator inside the L5953 is a voltage control mode (also known as "direct duty cycle") Buck regulator: the error signal coming from the error amplifier is compared with a sawtooth to set on and off times of the power switch. The feedforward control is introduced to get a quickly response to input voltage changes: the sawtooh has a fixed frequency and an amplitude variable with the battery voltage. Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the free-wheeling diode. Error amplifier and compensation network The error amplifier (EA) is a voltage amplifier whose non-inverting input is fixed to the reference voltage (1.275V bandgap voltage) and whose inverting input and output are externally available for feedback and frequency compensation. 10/24 L5953 Figure 5. Linear regulators - Internal pin connections STCAP VREF 1.275V POWER MOS VSTBY VSTBY CONTROLLER VSTBY ADJ FGND FBLR LINEAR REGULATOR CONTROLLER VLR POWER MOS VREF 1.275V VIN D03AU1493 Figure 6. Reset Internal pin Connection RES Vref 2.5V/1.65V 7.5µA CT FROM VST-BY Vref 1.275V D03AU1480 Figure 7. Low Voltage Warning Block Diagram. V1 Vref =1.275V S1 W1 + - M1 V2 Vref =1.275V S2 W2 + - M2 D03AU1478 11/24 L5953 Figure 8. HSD - Internal pin connections HSD1 HSD1 CONTROLLER POWER MOS HSD1 HSD2 CONTROLLER POWER MOS HSD2 VDD-LIN HSD2 D01AU1333 Figure 9. PWM - Internal pin connections STRAP COMP ERROR AMPLIFIER FB VDD-SW RS2 DRAINOUT CURRENT SENSING RS1 VREF 1.275V PWM CONTROLLER POWER MOS VSW GATEIN FROM THE OSCILLATOR GATEOUT D03AU1482 Figure 10. SPI & IRQ Internal pin connections IRQ S Q SPI INTERFACE D C DGND D03AU1481 12/24 L5953 SPI INTERFACE Signals Description (Figure 10) The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3. Serial Output (Q). The output pin is used to transfer data serially out of the L5953. Data is shifted out on the falling edge of the serial clock. Serial Input (D). The input pin is used to transfer data serially into the device. It receives instructions, addresses, and data to be written. Input is latched on the rising edge of the serial clock. Serial Clock (C). The serial clock provides the timing of the serial interface. Instructions, addresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after the falling edge of the clock input. Chip Select (S). This input is used to select the L5953. The chip is selected by a high to low transition on the S pin. At any time, the chip is deselected by a low to high transition on the S pin. As soon as the chip is deselected, the Q pin is at high impedance state. The pin allows multiple L5953 to share the same SPI bus. After power up, the chip is at the deselect state. SPI Input/Output are supplied by an external supply voltage VSPI while the core is supplied by the stand-by regulator VSTBY. The SPI is resetted by an internal signal whose buffered version is RES . OPERATIONS All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction code must be entered in the chip. This code is entered in the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S = low). Table 1 shows the instruction set and format for device operation. An invalid instruction (one not contained in table 1) leaves the chip as previously selected. Write Enable (WREN and Write Disable (WRDI) The L5953 contains a write enable latch. This latch must be set prior to every WRITE operation. The WREN instruction will set the latch and the WRDI istruction will reset the latch. The latch is reset under all the following conditions: – Power on – WRDI instruction executed As soon as the WREN or WRDI instruction is received by the L5953, the circuit executes the instruction and enters a wait mode until it is deselected. Table 1. Instruction Set. Instruction Description Instruction Format WREN Set Write Enable Latch 00000110 WRDI Reset Write Enable Latch 00000100 WSTA Write Status Register 00000010 RDIA Read Diagnostic Register 00000101 RSTA Read Status Register 00000011 13/24 L5953 Table 2. Status Register. s15 s14 REG2 HSD1 s13 s12 s11 HSD2 TBD TBD s10 s9 PWM PWM Freq. s8 s7 s6 s5 s4 s3 s2 TBD TBD TBD TBD TBD TBD TBD s1 s0 Test START Mode DIAG Table 3. Status Register Description 0 1 s15 REG2 Linear Voltage Regulator 1.5 to 3.3V Regulator off Regulator on s14 High Side Driver 1 HSD1 off HSD1 on s13 High Side Driver 2 HSD2 off HSD2 on s12 TBD s11 TBD s10 PWM switching frequency 260kHz 400kHz s9 PWM Voltage Regulator PWM1 off PWM1 on s8 TBD s7 TBD s6 TBD s5 TBD s4 TBD s3 TBD s2 TBD Test Mode Test Mode off Test Mode on NOTE: in this case the bits s15 - s2 are internally set to 0 (regulators and high side drivers are in off condition) Diagnostic Diagnostic off Starts the diagnostic procedure: - in Test Mode if s1=1; - during normal operation if s1=0 If s1=0 and s0=1, must be s14 = 1 (HSD1 ON) and s13=1 (HSD2 ON) s1 s0 Table 4. Diagnostic Register. d7 Test mode 14/24 d6 HSD1W1 d5 HSD1W2 d4 HSD1W3 d3 d2 d1 d0 HSD2W1 HSD2W2 HSD2W3 THW L5953 Table 5. Diagnostic Register Description. 0 1 d7 Test mode The Diagnostic Register is referred to a test performed during the normal working of the L5953 The Diagnostic Register is referred to a test performed in Test mode d6 HSD1W1 If d7=0: HSD1 in normal condition; If d7=1: bit value meaningless If d7=0: HSD1 is in overcurrent If d7=1: bit value meaningless d5 HSD1W2 If d7=0: bit value meaningless; If d7=1: HSD1 in normal condition If d7=0: bit value meaningless If d7=1: an open load is present on HSD1 d4 HSD1W3 If d7=0: bit value meaningless; If d7=1: HSD1 in normal condition If d7=0: bit value meaningless If d7=1: HSD1 is shorted to the supply voltage VDD d3 HSD2W1 If d7=0: HSD1 in normal condition; If d7=1: bit value meaningless If d7=0: HSD2 is in overcurrent; If d7=1: bit value meaningless d2 HSD2W2 If d7=0: bit value meaningless If d7=1: HSD2 in normal condition If d7=0: bit value meaningless If d7=1: an open load is present on HSD2 d1 HSD1W3 If d7=0: bit value meaningless If d7=1: HSD2 in normal condition; If d7=0: bit value meaningless If d7=1: HSD1 is shorted to the supply voltage VDD d0 Thermal Warning Normal condition Overtemperature protection activated(Tj>150°C) SUMMARY OF THE MAIN OPERATIONS Operation A ■ Test Mode Diagnostic Procedure Start ■ 1) WREN instruction (Fig.11) ■ 2) WSTA instruction (Fig.12) Operation B ■ Read the Diagnostic Register Case1: after a Test Mode Diagnostic Procedure Start 1) RDIA instruction (Fig.13) 2) Diagnostic Register output (Fig.13) ■ NOTE: an operation B must follow an operation A. The delay between the end of the operations A to the start of the operations B must be longer than 100µS Operation C ■ Write the Status Register 15/24 L5953 1) WREN instruction (Fig.11) 2) WSTA instruction (Fig.16) Operation D ■ Read the Status Register 1) RSTA instruction (Fig.17) 2) Status Register output (Fig.17) Operation E ■ Diagnostic Procedure Start 1) WREN instruction (Fig.11) 2) WSTA instruction (Fig.14) Operation F ■ Read the Diagnostic Register Case 2: after a Diagnostic Procedure Start 1) RDIA instruction (Fig.15) 2) Diagnostic Register output (Fig.15) An operation F must follow an operation E if the pin IRQ is not activated. The delay between the Operation E and an Operation F must be longer than 100µs. To be recognized, the fault must be present without interruptions during all the delay above mentionned . After an Operation F, the bit s0 of the Status Register is resettled (0) Operation G ■ Write operation disabled 1) WRDI instruction (Table 1) Operation H ■ Read the Diagnostic Register case 3: after an IRQ pin activation 1) RDIA instruction (Fig. 15) 2) Diagnostic Register Output (Fig. 15) The delay between the IRQ activation and an Operation F must be longer than 100µs Figure 11. Write Enable Latch Sequence S 00 01 02 03 04 05 06 07 C CPOL=0 CPHA=0 D Q 16/24 HIGH IMPEDANCE D03AU1483 L5953 Figure 12. Test Mode Diagnostic Procedure Start (after a Write Enable Latch Sequence, Fig.11) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 s6 s5 s4 s3 s2 s1 s0 C INSTRUCTION STATUS REGISTER s15 D s14 s13 s12 s11 s10 s9 s8 s7 HIGH IMPEDANCE Q D03AU1484 Figure 13. Read the Diagnostic registerCase1: after a Test Mode diagnostic procedure start (Fig. 12) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 d7 d6 10 11 12 13 14 15 C INSTRUCTION D DIAGNOSTIC REGISTER OUT HIGH IMPEDANCE Q d5 d4 d3 d2 d1 d0 D03AU1485 Figure 14. Diagnostic Procedure Start (after a Write Enable Latch Sequence, operation A) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 s15 s14 s13 s12 s11 s10 14 15 16 17 18 19 20 21 22 23 s6 s5 s4 s3 s2 s1 s0 C INSTRUCTION STATUS REGISTER D s9 s8 s7 HIGH IMPEDANCE Q D03AU1486 Figure 15. Read the Diagnostic RegisterCase2: during the normal working of the L5953 (after a Diagnostic Procedure Start, Fig.14) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 C INSTRUCTION D DIAGNOSTIC REGISTER OUT HIGH IMPEDANCE Q d7 d6 d5 d4 d3 d2 d1 d0 D03AU1487 17/24 L5953 Figure 16. Write the Status Register (after a Write Enable Latch Sequence, operation A) CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 s6 s5 s4 s3 s2 s1 s0 C INSTRUCTION STATUS REGISTER s15 D s14 s13 s12 s11 s10 s9 s8 s7 HIGH IMPEDANCE Q D03AU1488 Figure 17. Read the Status Register CPOL=0, CPHA=0 S 00 01 02 03 04 05 06 07 08 09 10 11 12 13 s15 s14 s13 s12 s11 s10 14 15 16 17 18 19 20 21 22 23 s5 s4 s3 s2 s1 s0 C INSTRUCTION D STATUS REGISTER OUT HIGH IMPEDANCE Q s9 s8 s7 s6 D03AU1489 IRQ - Interrupt Request Pin ■ It is an open drain pin activated (low) every time a variation occurs in the Diagnostic Register. ■ Purpose: to alert the µP that one or more warning bit of the Diagnostic Register has changed from 0 to 1 or from 1 to 0. ■ An activation of this pin puts the bit s0 of the Status Register to 1 (START DIAGNOSTIC) like an Operation E (Diagnostic Procedure Start). Then an Operation F has to be executed without an Operation E before. ■ After an Operation F, the IRQ pin is disactivated, and goes to 1 if connected to a pull-up resistor. L5953 - Application Note 18/24 L5953 Figure 18. Block and Application Diagram C2 C5 S1 W1 S2 D1 C1 VDD W2 VDD-LIN VDD-SW C3 C11 STCAP CT RES FGND VSTBY REG1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA VOLTAGE WARNING C4 ADJ HSD1 HSD1 STRAP PWM STEP DOWN REGULATOR 2.5-10V/1A HSD2 HSD2 C6 DRAINOUT L1 VSW Vo GATEIN D2 GATEOUT R2 FB VSPI REG2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA SPI INTERFACE IRQ COMP OSCILLATOR & SYNC R4 R3 C9 SWGND GND Q D S VLR C FBLR R5 C10 VIN DGND SYNC C7 R1 C8 D01AU1331B R6 Figure 19. Block Diagram And Application With External Power MOS C2 C5 S1 W1 S2 D1 C1 VDD W2 VDD-LIN VDD-SW C3 STCAP CT RES FGND REG1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA VOLTAGE WARNING VSTBY C4 ADJ HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A HSD2 HSD2 STRAP C6 DRAINOUT L1 VSW Vo D2 GATEIN GATEOUT R1 M1 R2 FB VSPI REG2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA SPI INTERFACE IRQ C7 COMP R4 OSCILLATOR & SYNC SWGND C9 R3 GND C8 Q D S C VLR C10 FBLR R5 VIN SYNC DGND D01AU1332B R6 19/24 L5953 PART LIST on Evaluation Board C1 = 470 µF C2 = 220 nF C3 = 470 µF C4 = 10 µF C5 = 1 µF C7 = 470 µF ESR=65 mΩ C8 = 56nF C9 = 2.7 nF C10 = 10 µF C11 = 4.7 nF R1 = 2.2 kΩ R2 = 2 x 1.5 kΩ in parallel R3 = 10 kΩ R4 = 220 kΩ R5 = 3.3 kΩ D1 = 1N4007 or MBR160 D2 = MBR360 L1 = 180 µH C6 = 100 nF R6 = 1 kΩ REG1 OUTPUT VOLTAGE VSTBY = 5V if pin ADJ left floating VSTBY = 3.3V if pin ADJ is conneted to the pin VSTBY Timing Capacitor The value for this capacitor has to be chosen according the wanted power-on delay Td: ICT 1 ⋅ T d C11 = ------------------------------------------------------------( 0.5 ⋅ VS TB Y ) + V CTL Ry where ICT1 is the source current used to charge the timing capacitor and VSTBY is the REG1 output voltage. Feedback resistors for REG2 VLR R5 = R6 ⋅ -------------------------- – 1 V ref, REG 2 where VLR is the required output voltage for REG2. External components for PWM regulator Bootstrap capacitor The suggested value for the bootstrap capacitor is C6 = 100nF Here following you find the criteria for the selection of the inductor L1, the free-wheeling diode D2, the output filter capacitor C7, the feedback resistor R1, R2 and the compensation network R3, C8, R4, C9 to have a Buck regulator working in Continuos mode. Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the free-wheeling diode. Inductor Selection The minimum value of the inductor L7 has to be so that the maximum inductor current ripple ∆IL,max is 20% to 30% of the maximum load current load Io,max.The maximum ripple is present when the switching frequency is minimum ( fsw,min ) and the input voltage is maximum ( Vin,max ) so the minimum value for the inductor Lmin is : VO VO 1 Lmin = -------------------- ⋅ 1 – ----------------- ⋅ -----------------∆IL, max V i, max fs w, min Output Capacitor Selection The criteria for the selection of the capacitor C7 is based on the output voltage ripple requirements. The ripple on the output voltage is due to a capacitive contribute, often negligible, equal to 20/24 L5953 ∆I L, max ∆V c = -------------------------------------8 ⋅ C7 ⋅ f s w, min and a resistive contribute given by the ESR of the capacitor and which is equal to ∆V ESR = ESR ⋅ ∆IL, ma x ∆VC fixes the value for C7 while ∆VESR limits the ESR of the capacitor.Usually the capacitor is chosen so that the total ripple on the output regulated voltage Vo is equal to 1% of the value of Vo. If Vripple is the maximum allowed voltage ripple on Vo then it should result: 2 Vripple ≥ ∆V c + ∆V ES R 2 More often the minimum value of C7 is imposed by other considerations such as to get a good dynamic behaviour of the output voltage in case of large load variations. Free-wheeling diode The diode must withstand an average current Id equal to Id = Ilim ( 1- Dmin ) where Ilim is the current of intervention of the short circuit protection and Dmin is the minimum duty cycle. As Dmin is vey low, the current Id can be assumed equal to Ilim. Compensation Network In continuous mode, the voltage controlled buck converter showes two poles due to the output LC filter and one zero due to the ESR of the output capacitor. The suggested compensation network introduces two zeros and two poles: – the zeros compensate the double poles of the LC filter – one pole compensates the zero due to ESR of the output capacitor – the second pole is nominally located in the origin which means an infinite gain at frequency null. In the reality the DC value of the closed loop gain can not be greater than the DC value of the EA open loop gain and the pole is located at very low frequency. The values for the components of the compensation network can be fixed when the inductor L1 and the output capacitor C7 are chosen. The necessary steps are following: 1.fix the cross-over frequency fC of the overall loop gain. Usually f c = 0.1 ⋅ fs w,min where fsw,min is the minimum switching frequency 2.Calculate the high frequency error amplifier gain L1 G c = 0.25 ⋅ f c ⋅ 2 ⋅ π ⋅ ------------ESR 3.Chose R3 and calculate L1 ⋅ C7 C8 = 2 ⋅ ----------------------R3 The value for R3 has not to be very high (for example 10KΩ) so to limit the error due to an error amplifier input offset current. 21/24 L5953 4.Calculate R3 R p = --------------------------------------------2 L1- ------------- ⋅ ------–1 E SR C7 VO RA = Rp ⋅ -----------------------V ref , PWM Rp R2 = -------------------------------Vref,PWM 1 – ----------------------VO 5.Finally calculate R4 = G C ⋅ R1 and 22/24 L1 ⋅ C7 C9 = 2 ⋅ ----------------------R4 L5953 DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S MIN. mm TYP. 0.10 0 0.22 0.23 15.80 9.40 13.90 MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50 inch TYP. MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547 0.65 11.05 10.90 0.0256 0.435 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10°(max.) 8 °(max.) 5.80 2.90 0 15.50 0.80 OUTLINE AND MECHANICAL DATA MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043 PowerSO36 (1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G". N N a2 e A DETAIL A A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 36 BOTTOM VIEW 19 E3 B E1 E2 D1 DETAIL B 0.35 Gage Plane 1 1 -C- 8 S h x 45˚ b ⊕ 0.12 L SEATING PLANE G M AB PSO36MEC C (COPLANARITY) 23/24 L5953 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 24/24