STMICROELECTRONICS VIPER37HE

VIPER37
VIPerPlus family: fixed frequency offline converter
Features
■
800 V avalanche rugged power section
■
PWM operation with adjustable limiting current
■
30 mW standby power at 265 Vac
■
Operating frequency:
– 60 kHz for L type
– 115 kHz for H type
SDIP10
Description
■
Frequency jittering for low EMC
■
Output overvoltage protection
■
High primary current protection (2nd OCP)
■
Input undervoltage setting (brownout)
■
Onboard soft-start
■
Safe auto-restart after a fault condition
■
Hysteretic thermal shutdown
This device is an offline converter with an 800 V
rugged power section, a PWM control, two levels
of overcurrent protection, overvoltage and
overload protection, hysteretic thermal protection,
soft-start, and safe auto-restart after the removal
of any fault condition. Burst mode operation and
very low device consumption help to meet the
standby energy saving regulations.
Advance frequency jittering reduces EMI filter
costs. Brownout function protects the switch
mode power supply when the rectified input
voltage level is below the normal minimum level
specified for the system. The high voltage startup
circuit is embedded in the device.
Applications
■
SMPS for set-top boxes, DVD players and
recorders, white goods
■
Auxiliary power supply for consumer and home
equipment
■
ATX auxiliary power supply
■
Low / medium power AC-DC adapters
Figure 1.
Typical topology
+
+
DC input high voltage
wide range
DC Output voltage
DRAIN DRAIN DRAIN DRAIN DRAIN
VIPER37
GND
Table 1.
VDD
CONT
FB
BR
Device summary
Order codes
Package
Packaging
SDIP10
Tube
VIPER37LE
VIPER37HE
February 2012
Doc ID 022218 Rev 1
1/35
www.st.com
35
Contents
VIPER37
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Efficiency performances for a typical flyback converter . . . . . . . . . . . 16
8
Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/35
8.1
Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.2
High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.3
Power-up and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.4
Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.5
Auto-restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.6
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.7
Current mode conversion with adjustable current limit set point . . . . . . . 22
8.8
Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.9
About the CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.10
Feedback and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.11
Burst mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 27
8.12
Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.13
2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 30
Doc ID 022218 Rev 1
VIPER37
Contents
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Doc ID 022218 Rev 1
3/35
Block diagram
VIPER37
1
Block diagram
Figure 2.
Block diagram
VDD
VDD
Vcc
BR
DRAIN
+
Vin_OK
VBRth
Internal Supply bus
&
Ref erence Voltages
SUPPLY
& UVLO
HV_ON
Istart-up
15uA
UVLO
SOFT
START
OCP
BLOCK
-
CONT
OTP
OCP
BURST
+
.
OVP
LOGIC
+
THERMAL
SHUTDOWN
OSCILLATOR
PWM
TURN-ON
LOGIC
LEB
S
Q
R1
R2
6uA
+
OVP
2nd OCP
LOGIC
Ref
OLP
OVP
OTP
Rsense
BURST-MODE
LOGIC
BURST
FB
GND
2
Typical power
Table 2.
Typical power
230 VAC
Part number
VIPER37
85-265 VAC
Adapter(1)
Open frame(2)
Adapter(1)
Open frame(2)
23 W
25 W
13 W
15 W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 ° C ambient.
2. Maximum practical continuous power in an open frame design at 50 ° C ambient, with adequate heatsinking.
4/35
Doc ID 022218 Rev 1
VIPER37
3
Pin settings
Pin settings
Figure 3.
Note:
Connection diagram (top view)
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The copper area for heat dissipation must be designed under the DRAIN pins.
Table 3.
Pin description
Pin n.
Name
1
GND
This pin represents the device ground and the source of the power section.
2
VDD
Supply voltage of the control section. This pin also provides the charging current
of the external capacitor during startup time.
3
4
5
6...10
Function
Control pin. The following functions can be selected:
1. current limit set point adjustment. The internal set default value of the cycle-bycycle current limit can be reduced by connecting to ground an external resistor.
CONT
2. output voltage monitoring. A voltage exceeding the VOVP threshold (see
Table 8) shuts the IC down reducing the device consumption. This function is
stropped and digitally filtered for high noise immunity.
FB
Control input for duty cycle control. Internal current generator provides bias
current for loop regulation. A voltage below the threshold VFBbm activates the
burst mode operation. A level close to the threshold VFBlin means that we are
approaching the cycle-by-cycle overcurrent set point.
BR
Brownout protection input with hysteresis. A voltage below the threshold VBRth
shuts down (not latched) the device and lowers the power consumption. Device
operation restarts as the voltage exceeds the threshold VBRth + VBRhyst.
It can be connected to ground when not used.
High voltage drain pin. The built-in high voltage switched startup bias current is
DRAIN drawn from this pin too.
Pins connected to the metal frame to facilitate heat dissipation.
Doc ID 022218 Rev 1
5/35
Electrical data
VIPER37
4
Electrical data
4.1
Maximum ratings
Table 4.
Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min.
Max.
VDRAIN Drain-to-source (ground) voltage
V
EAV
Repetitive avalanche energy
(limited by TJ = 150 °C)
5
mJ
IAR
Repetitive avalanche current
(limited by TJ = 150 °C)
1.5
A
3
A
IDRAIN
Pulse drain current
VCONT
Control input pin voltage
-0.3
6
V
VFB
Feedback voltage
-0.3
5.5
V
VBR
Brownout input pin voltage
-0.3
5
V
VDD
Supply voltage (IDD = 25 mA)
-0.3
Self limited
V
IDD
Input current
25
mA
Power dissipation at TA < 60 °C
1.5
W
PTOT
TJ
TSTG
4.2
800
Operating junction temperature range
-40
150
°C
Storage temperature
-55
150
°C
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Max. value
Unit
RthJP
Thermal resistance junction pin
(Dissipated power = 1 W)
35
° C/W
RthJA
Thermal resistance junction ambient
(Dissipated power = 1 W)
80
° C/W
RthJA
Thermal resistance junction ambient (1)
(Dissipated power = 1 W)
65
° C/W
1. When mounted on a standard single side FR4 board with 150 mm2 (0.155 sq. in.) of Cu (35 µm thick).
6/35
Doc ID 022218 Rev 1
VIPER37
4.3
Electrical data
Electrical characteristics
(TJ = -25 to 125 °C, VDD = 14 V(a); unless otherwise specified).
Table 6.
Power section
Symbol
Parameter
VBVDSS
IOFF
RDS(on)
COSS
Test condition
Min.
Breakdown voltage
IDRAIN = 1 mA, VFB = GND
TJ = 25 °C
800
OFF state drain current
VDRAIN = max. rating,
VFB = GND, TJ = 25 °C
60
µA
IDRAIN = 0.4 A, VFB = 3 V,
VBR = GND, TJ = 25 °C
4.5
Ω
IDRAIN = 0.4 A, VFB = 3 V,
VBR = GND, TJ = 125 °C
9
Ω
Drain-source on state
resistance
Effective (energy related)
output capacitance
VDRAIN = 0 to 640 V,
TJ = 25 °C
Typ.
Max.
Unit
V
17
pF
a. Adjust VDD above VDDon startup threshold before setting to 14 V.
Doc ID 022218 Rev 1
7/35
Electrical data
VIPER37
Table 7.
Symbol
Supply section
Parameter
Test condition
Min.
Typ.
Max.
Unit
60
80
100
V
VDRAIN = 120 V,
VBR = GND, VFB = GND,
VDD = 4 V
-2
-3
-4
mA
VDRAIN = 120 V,
VBR = GND, VFB = GND,
VDD = 4 V after fault.
-0.4
-0.6
-0.8
mA
Operating voltage range
After turn-on
8.5
23.5
V
VDD clamp voltage
IDD = 20 mA
23.5
Voltage
VDRAIN_START
IDDch
VDD
VDDclamp
Drain-source start voltage
Startup charging current
VDDon
VDD startup threshold
VDDoff
VDD undervoltage
shutdown threshold
VDD(RESTART)
V
13
14
15
V
VBR = GND, VFB = GND
7.5
8
8.5
V
VDD restart voltage
threshold
VDRAIN = 120 V,
VBR = GND, VFB = GND
4
4.5
5
V
IDD0
Operating supply current,
not switching
VFB = GND, FSW = 0 kHz,
VBR = GND, VDD = 10 V
0.9
mA
VDRAIN = 120 V,
FSW = 60 kHz
2.5
mA
IDD1
Operating supply current,
switching
VDRAIN = 120 V,
FSW = 115 kHz
3.5
mA
VDRAIN = 120 V,
Current
8/35
IDD_FAULT
Operating supply current,
with protection tripping
VDD = 10 V
400
µA
IDD_OFF
Operating supply current
with VDD < VDD_OFF
VDD = 7 V
270
µA
Doc ID 022218 Rev 1
VIPER37
Electrical data
Table 8.
Controller section
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Feedback pin
VFBolp
Overload shutdown
threshold
4.5
4.8
5.2
V
VFBlin
Linear dynamics upper limit
3.2
3.5
3.7
V
VFBbm
Burst mode threshold
Voltage falling
0.6
V
VFBbmhys
Burst mode hysteresis
Voltage rising
100
mV
IFB
RFB(DYN)
HFB
Feedback sourced current
VFB = 0.3 V
-150
3.3 V < VFB < 4.8 V
Dynamic resistance
VFB < 3.3 V
∆VFB / ∆ID
-200
-280
µA
µA
-3
14
21
kΩ
2
6
V/A
CONT pin
VCONT_l
Low level clamp voltage
ICONT = -100 µA
VCONT_h
High level clamp voltage
ICONT = 1 mA
0.5
V
5
5.5
6
V
0.95
1
1.05
A
Current limitation
IDlim
Max. drain current limitation
tSS
Soft-start time
TON_MIN
td
tLEB
ID_BM
VFB = 4 V,
ICONT = -10 µA
TJ = 25 °C
8.5
Minimum turn-on time
220
400
ms
480
ns
Propagation delay
100
ns
Leading edge blanking
300
ns
160
mA
Peak drain current during
burst mode
VFB = 0.6 V
Oscillator section
VIPER37L
FOSC
FD
VDD = operating
voltage range,
VFB = 1 V
VIPER37H
54
60
66
kHz
103
115
127
kHz
VIPER37L
±4
kHz
VIPER37H
±8
kHz
250
Hz
Modulation depth
FM
Modulation frequency
DMAX
Maximum duty cycle
Doc ID 022218 Rev 1
70
80
%
9/35
Electrical data
VIPER37
Table 8.
Controller section (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Overcurrent protection (2nd OCP)
IDMAX
Second overcurrent
threshold
1.7
A
Overvoltage protection
VOVP
Overvoltage protection
threshold
TSTROBE
Overvoltage protection
strobe time
2.7
3
3.3
2.2
V
us
Brownout protection
VBRth
Brownout threshold
Voltage falling
VBRhyst
Voltage hysteresis above
VBRth
Voltage rising
IBRhyst
Current hysteresis
VBRclamp
VDIS
Clamp voltage
0.41
0.45
50
7
IBR = 250 µA
Brownout disable voltage
0.49
mV
12
3
50
V
µA
V
150
mV
Thermal shutdown
10/35
TSD
Thermal shutdown
temperature
THYST
Thermal shutdown
hysteresis
Doc ID 022218 Rev 1
150
160
°C
30
°C
VIPER37
Electrical data
Figure 4.
Minimum turn-on time test circuit
V(DRAIN)
14 V
GND
DRAIN
VDD
DRAIN
CONT
DRAIN
FB
DRAIN
BR
DRAIN
90 %
TONmin
50 Ω
10 %
Time
I(DRAIN)
IDLIM
30 V
3.5 V
Time
Figure 5.
Brownout threshold test circuits
14 V
IBRhyst
V(BR)
GND
DRAIN
VDD
DRAIN
VBRth+VBRhyst
VBRth
CONT
DRAIN
VDIS
FB
DRAIN
BR
DRAIN
Time
IBRhyst
30 V
2V
I(BR)
10 kΩ
I(DRAIN)
Time
Time
Figure 6.
OVP threshold test circuits
GND
DRAIN
VDD
DRAIN
CONT
DRAIN
FB
DRAIN
BR
DRAIN
14 V
V(CONT)
VOVP
10 kΩ
V(DRAIN)
Time
30 V
2V
Time
Note:
Adjust VDD above VDDon startup threshold before setting to 14 V.
Doc ID 022218 Rev 1
11/35
Typical electrical characteristics
VIPER37
5
Typical electrical characteristics
Figure 7.
Current limit vs. TJ
Figure 8.
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Switching frequency vs. TJ
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Drain start voltage vs. TJ
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Figure 10. HFB vs. TJ
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Figure 9.
Doc ID 022218 Rev 1
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VIPER37
Typical electrical characteristics
Figure 11. Brownout threshold vs. TJ
Figure 12. Brownout hysteresis vs. TJ
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Figure 13. Brownout hysteresis current vs. TJ Figure 14. Operating supply current
(not switching) vs. TJ
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Doc ID 022218 Rev 1
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13/35
Typical electrical characteristics
VIPER37
Figure 15. Operating supply current
(switching) vs. TJ
Figure 16. Current limit vs. RLIM
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Figure 17. Power MOSFET ON resistance vs.
TJ
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Figure 18. Power MOSFET breakdown voltage
vs. TJ
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14/35
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VIPER37
Typical electrical characteristics
Figure 19. Thermal shutdown
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6$$OFF
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Typical circuit
6
VIPER37
Typical circuit
Figure 20. Min-features flyback application
D3
Vout
R1
AC IN
C2
BR
C1
C5
AC IN
D1
GND
D2
R2
R3
VVcc
DD
OPTO
DRAIN
R5
BR
CONTROL
C3
R4
CONT
FB
C6
GND
SOURCE
U2
C4
R6
Figure 21. Full-features flyback application
D3
Rh
AC IN
Vout
R1
C2
BR
C1
C5
Rl
AC IN
D1
GND
Daux
Rov p
R2
D2
R3
VVcc
DD
DRAIN
OPTO
R5
BR
CONTROL
C3
R4
CONT
FB
C6
GND
SOURCE
U2
Rlim
C4
16/35
Doc ID 022218 Rev 1
R6
VIPER37
Efficiency performances for a typical flyback
converter
The efficiency of the converter has been measured in different load and line voltage
conditions. In accordance with the ENERGY STAR® average active mode testing efficiency
method, the efficiency measurements have been performed at 25%, 50% and 75% and
100% of the rated output power, at both 115 VAC and 230 VAC.
Table 9.
Power supply efficiency, VOUT = 5 V, VIN = 115 VAC
%Load
Iout
Vout
Pout
Pin
Efficiency
25%
0.75
5.04
3.78
4.83
78.26%
50%
1.5
5.04
7.56
9.72
77.78%
75%
2.25
5.04
11.34
14.84
76.42%
100%
3
5.04
15.12
20.04
75.45%
Average efficiency
Table 10.
76.97%
Power supply efficiency, VOUT= 5 V, VIN = 230 VAC
%Load
Iout
Vout
Pout
Pin
Efficiency
25%
0.75
5.04
3.78
5.01
75.45%
50%
1.5
5.04
7.56
9.76
77.46%
75%
2.25
5.04
11.34
14.67
77.30%
100%
3
5.03
15.09
19.59
77.03%
Average efficiency
76.81%
Figure 22. Power supply consumption at light output loads, VOUT=5 V
350
200mW
300
250
Input power [mW]
7
Efficiency performances for a typical flyback converter
200
100mW
150
50mW
100
30mW
50
0
50
100
150
200
250
300
Input voltage [Vac]
Doc ID 022218 Rev 1
17/35
Efficiency performances for a typical flyback converter
VIPER37
Figure 23. Power supply consumption at no output load, VOUT=5 V
65
60
No brownout
With brownout
55
Input power [mW]
50
45
40
35
30
25
20
15
10
50
100
150
200
Input voltage [Vac]
18/35
Doc ID 022218 Rev 1
250
300
VIPER37
8
Operation description
Operation description
The device is a high-performance low-voltage PWM controller chip with an 800 V avalanche
rugged power section.
The controller includes: the oscillator with jittering feature, the startup circuits with soft-start
feature, the PWM logic, the current limit circuit with adjustable set point, the second
overcurrent circuit, the burst mode management, the brownout circuit, the UVLO circuit, the
auto-restart circuit, and the thermal protection circuit.
The current limit set-point is set by the CONT pin. The burst mode operation guarantees
high performance in standby mode and helps to accomplish the energy saving norm.
All the fault protections are built in auto-restart mode with very low repetition rate to prevent
the IC overheating.
8.1
Power section and gate driver
The power section is implemented with an avalanche ruggedness N-channel MOSFET,
which guarantees safe operation within the specified energy rating as well as high dv/dt
capability. The power section has a BVDSS of 800 V min. and a typical RDS(on) of 4.5 Ω
at 25 ° C.
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the power section cannot be turned on
accidentally.
8.2
High voltage startup generator
The HV current generator is supplied through the DRAIN pin and is enabled only if the input
bulk capacitor voltage is higher than the VDRAIN_START threshold, 80 VDC (typical). When the
HV current generator is ON, the IDDch current (3 mA typical value) is delivered to the
capacitor on the VDD pin. In the case of auto-restart mode after a fault event, the IDDch
current is reduced to 0.6 mA, in order to have a slow duty cycle during the restart phase.
Doc ID 022218 Rev 1
19/35
Operation description
8.3
VIPER37
Power-up and soft-start
If the input voltage rises up to the device start threshold VDRAIN_START, the VDD voltage
begins to grow due to the IDDch current (see Table 7) coming from the internal high voltage
startup circuit. If the VDD voltage reaches the VDDon threshold (see Table 7), the Power
MOSFET starts switching and the HV current generator is turned off (see Figure 25).
The IC is powered by the energy stored in the capacitor on the VDD pin, CVDD, until the selfsupply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage high enough to sustain the operation.
The CVDD capacitor must be sized correctly in order to avoid fast discharge and keep the
needed voltage value higher than the VDDoff threshold. In fact, a too low capacitance value
could terminate the switching operation before the controller receives any energy from the
auxiliary winding.
The following formula can be used for the VDD capacitor calculation:
Equation 1
I DDch × tSSaux
C VDD = ---------------------------------------V DDon – V DDoff
The tSSaux is the time needed for the steady-state of the auxiliary voltage. This time is
estimated by the applicator according to the output stage configurations (transformer, output
capacitances, etc.).
During the converter startup time, the drain current limitation is progressively increased to
the maximum value. In this way the stress on the secondary diode is considerably reduced.
It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the
feature is implemented for every attempt of the startup converter or after a fault.
20/35
Doc ID 022218 Rev 1
VIPER37
Operation description
Figure 24. IDD current during startup and burst mode
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6$$OFF
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Figure 25. Timing diagram: normal power-up and power-down sequences
6).
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Doc ID 022218 Rev 1
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21/35
Operation description
VIPER37
Figure 26. Timing diagram: soft-start
I DRAIN
tss
IDlim
t
V FB
V FBolp
V FBlin
t
8.4
Power down operation
At converter power down, the system loses regulation as soon as the input voltage is so low
that the peak current limitation is reached. The VDD voltage drops and when it falls below
the VDDoff threshold (see Table 7) the Power MOSFET is switched OFF, the energy transfers
to the IC interrupted and consequently the VDD voltages decrease, Figure 25. Later, if the
VIN is lower than VDRAIN_START (see Table 7), the startup sequence is inhibited and the
power down completed. This feature is useful to prevent the converter’s restart attempts and
ensures monotonic output voltage decay during the system power down.
8.5
Auto-restart operation
If, after a converter power down, the VIN is higher than VDRAIN_START, the startup sequence
is not inhibited and is activated only when the VDD voltage drops below the VDD(RESTART)
threshold (see Table 7). This means that the HV startup current generator restarts the VDD
capacitor charging only when the VDD voltage drops below VDD(RESTART). The scenario
described above is, for instance, a power down because of a fault condition. After a fault
condition, the charging current IDDch is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal
startup converter phase. This feature, together with the low VDD(RESTART) threshold,
ensures that, after a fault, the restart attempts of the IC have a very long repetition rate and
the converter works safely with extremely low power throughput. Figure 27 shows the IC
behavior after a short-circuit event.
22/35
Doc ID 022218 Rev 1
VIPER37
Operation description
Figure 27. Timing diagram: behavior after short-circuit
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8.6
Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both cases the switching
frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz
(115 kHz version) at a 250 Hz (typ.) rate, so that the resulting spread-spectrum action
distributes the energy of each harmonic of the switching frequency over a number of sideband harmonics having the same energy on the whole but smaller amplitudes.
8.7
Current mode conversion with adjustable current limit set
point
This device is a current mode converter: the drain current is sensed and converted into
voltage that is applied to the non-inverting pin of the PWM comparator. This voltage is
compared with the one on the feedback pin through a voltage divider on a cycle-by-cycle
basis.
The device has a default current limit value, IDlim, that the user can adjust according to the
electrical specifications, through the RLIM resistor connected to the CONT pin (see
Figure 16).
The CONT pin has a minimum current sunk, needed to activate the IDlim adjustment: without
RLIM or with high RLIM (i.e. 100 kΩ), the current limit is fixed to the default value (see IDlim,
Table 8).
Doc ID 022218 Rev 1
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Operation description
8.8
VIPER37
Overvoltage protection (OVP)
The device can monitor the converter output voltage. This operation is done by the CONT
pin during Power MOSFET OFF-time, when the voltage generated by the auxiliary winding
tracks the converter's output voltage, through turn ratio N
(see Figure 28).
AUX
-------------N SEC
In order to perform the output voltage monitor, the CONT pin must be connected to the aux.
winding through a resistor divider made up of RLIM and ROVP (see Figure 21 or Figure 29). If
the voltage applied to the CONT pin exceeds the internal reference VOVP (see Table 8) for
four consecutive times, the controller recognizes an overvoltage condition. This special
feature uses an internal counter; that is to reduce sensitivity to noise and prevent the latch
from being erroneously activated (see Figure 28). The counter is reset every time the OVP
signal is not triggered in one oscillator cycle.
Referring to Figure 21, the resistors’ divider ratio kOVP is given by:
Equation 2
V OVP
k OVP = ----------------------------------------------------------------------------------------------------N AUX
-------------- ⋅ ( VOUTOVP + V DSEC ) – VDAUX
N SEC
Equation 3
R LIM
k OVP = --------------------------------R LIM + R OVP
where:
●
VOVP is the OVP threshold (see Table 8)
●
VOUT OVP is the converter output voltage value to activate the OVP set by the user
●
NAUX is the auxiliary winding turns
●
NSEC is the secondary winding turns
●
VDSEC is the secondary diode forward voltage
●
VDAUX is the auxiliary diode forward voltage
●
ROVP together with RLIM make up the output voltage divider.
Then, once the RLIM value is fixed, according to the desired IDlim, the ROVP can be
calculated by:
Equation 4
1 – kOVP
R OVP = R LIM × ----------------------k OVP
24/35
Doc ID 022218 Rev 1
VIPER37
Operation description
The resistor values are such that the current sourced and sunk by the CONT pin are within
the rated capability of the internal clamp.
Figure 28. OVP timing diagram
VDS
t
VAUX
0
CONT
(pin 4)
t
VOVP
t
T
STROBE
sampling time
STROBE
t
OVP
t
COUNTER
RESET
COUNTER
STATUS
t
0
0
0 →1
0
1 →2
2 →0
0 →1
0
1 →2
2 →3
3 →4
FAULT
t
NORMAL OPERATION
t
FEEDBACK LOOP FAILURE
About the CONT pin
Referring to Figure 29, the features below can be implemented through the CONT pin:
1.
Current limit set point
2.
Overvoltage protection on the converter output voltage
Table 11, referring to Figure 29, lists the external resistance combinations needed to
activate one or more of the CONT pin functions.
Figure 29. CONT pin configuration
D AUX
R OVP
CONT
SOFT
START
OCP Comparator
Current Limit
Curr. Lim.
BLOCK
+
8.9
TEMPORARY DISTURBANCE
Auxiliary
winding
R LIM
To PWM Logic
OVP DETECTION
LOGIC
From SenseFET
To OVP Protection
Doc ID 022218 Rev 1
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Operation description
Table 11.
VIPER37
CONT pin configurations
Function / component
RLIM (1)
ROVP
DAUX
IDlim reduction
See Figure 16
No
No
OVP
≥ 80 kΩ
See Equation 4
Yes
IDlim reduction + OVP
See Figure 16
See Equation 4
Yes
1. RLIM must be fixed before ROVP.
8.10
Feedback and overload protection (OLP)
The device is a current mode converter: the feedback pin controls the PWM operation,
controls the burst mode, and actives the overload protection. Figure 30 and Figure 31 show
the internal current mode structure.
With the feedback pin voltage between VFBbm and VFBlin, (see Table 8) the drain current is
sensed and converted into voltage that is applied to the non-inverting pin of the PWM
comparator.
This voltage is compared with the one on the feedback pin through a voltage divider on a
cycle-by-cycle basis. When these two voltages are equal, the PWM logic orders the switchoff of the Power MOSFET. The drain current is always limited to the IDlim value.
In case of overload, the feedback pin increases in reaction to this event and when it goes
higher than VFBlin, the PWM comparator is disabled and the drain current is limited to IDlim by
the OCP comparator, see Figure 2.
When the feedback pin voltage reaches the threshold VFBlin, an internal current generator
starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the
VFBolp threshold, the converter is turned off and the startup phase is activated with a reduced
value of IDDch to 0.6 mA, see Table 7.
During the first startup phase of the converter, after the soft-start time (tSS), the output
voltage may force the feedback pin voltage to rise up to the VFBolp threshold that switches off
the converter itself.
To avoid this event, the appropriate feedback network must be selected according to the
output load. Moreover, the feedback network fixes the compensation loop stability. Figure 30
and Figure 31 show the two different feedback networks.
The time from the overload detection (VFB = VFBlin) to the device shutdown
(VFB = VFBolp) can be set by the CFB value (see Figure 30 and Figure 31), using the formula:
Equation 5
V FBolp – V FBlin
T OLP – delay = C FB × ---------------------------------------I FB
where IFB is the value, reported in Table 8, when the FB voltage is between VFBlin and
VFBolp.
In Figure 30, the capacitor connected to the FB pin (CFB) is part of the compensation circuit
as well as being necessary to activate the overload protection.
26/35
Doc ID 022218 Rev 1
VIPER37
Operation description
After the startup time, tSS, during which the feedback voltage is fixed at VFBlin, the output
capacitor may not be at its nominal value and the controller interprets this situation as an
overload condition. In this case, the OLP delay helps to avoid an incorrect device shutdown
during the startup phase.
Owing to the above considerations, the OLP delay time must be long enough to bypass the
initial output voltage transient and check the overload condition only when the output voltage
is in steady-state. The output transient time depends on the value of the output capacitor
and on the load.
When the value of the CFB capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used, shown in
Figure 31.
Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are
introduced by the capacitors CFB and CFB1 and the resistor RFB1.
The capacitor CFB introduces a pole (fPFB) at a higher frequency than fZB and fPFB1. This
pole is usually used to compensate the high frequency zero due to the ESR (equivalent
series resistor) of the output capacitance of the flyback converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 31, are reported by the equations below:
Equation 6
fZFB =
1
2 ⋅ π ⋅ CFB1 ⋅ RFB1
Equation 7
fPFB =
RFB(DYN) + RFB1
2 ⋅ π ⋅ CFB ⋅ RFB(DYN) ⋅ RFB1
(
)
1
2 ⋅ π ⋅ CFB1 ⋅ RFB1 + RFB(DYN)
)
Equation 8
fPFB1 =
(
RFB(DYN) is the dynamic resistance seen by the FB pin.
The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB.
Equation 5 can still be used to calculate the OLP delay time but CFB1 must be considered
instead of CFB. Using the alternative compensation network, the user can satisfy, in all
cases, the loop stability and the correct OLP delay time alike.
Doc ID 022218 Rev 1
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Operation description
VIPER37
Figure 30. FB pin configuration 1
From sense FET
PWM
To PWM Logic
+
PWM
CONTROL
-
Cfb
BURST
BURST-MODE
LOGIC
BURST-MODE
REFERENCES
OLP comparator
To disable logic
+
-
4.8V
Figure 31. FB pin configuration 2
From sense FET
PWM
To PWM Logic
+
PWM
CONTROL
-
Rfb1
Cfb
BURST
Cfb1
BURST-MODE
REFERENCES
BURST-MODE
LOGIC
OLP comparator
+
4.8V
8.11
To disable logic
-
Burst mode operation at no load or very light load
When the load decreases, the feedback loop reacts by lowering the feedback pin voltage. If
it falls below the burst mode threshold, VFBbm, the Power MOSFET is no longer allowed to
be switched on. After the MOSFET stops, as a result of the feedback reaction to the energy
delivery stop, the feedback pin voltage increases and when it exceeds the level, VFBbm +
VFBbmhys, the power MOSFET starts switching again. The burst mode thresholds are
reported in Table 8 and Figure 32 shows this behavior. Depending on the output load, the
power alternates between periods of time in which the Power MOSFET is switching and is
enabled, with periods of time when the Power MOSFET is not switching; this working mode
is called burst mode. The power delivered to the output during switching periods exceeds
the load power demands; the excess of power is balanced from the non-switching period
where no power is processed. The advantage of burst mode operation is an average
switching frequency much lower then the normal operation working frequency, up to a few
hundred hertz, minimizing all frequency related losses. During burst mode the drain current
peak is clamped to the level, ID_BM, reported in Table 8.
28/35
Doc ID 022218 Rev 1
VIPER37
Operation description
Figure 32. Burst mode timing diagram, light load management
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8.12
Brownout protection
Brownout protection is a not-latched shutdown function activated when a condition of mains
undervoltage is detected.
The brownout comparator is internally referenced to VBRth,Table 8, and disables the PWM if
the voltage applied at the BR pin is below this internal reference. Under this condition the
Power MOSFET is turned off. Until the brownout condition is present, the VDD voltage
continuously oscillates between the VDDon and the UVLO thresholds, as shown in the timing
diagram of Figure 33. A voltage hysteresis is present to improve the noise immunity.
The switching operation is restarted as the voltage on the pin is above the reference plus the
previously mentioned voltage hysteresis, see Figure 5.
The brownout comparator is provided also with a current hysteresis, IBRhyst. The user must
set the rectified input voltage above which the Power MOSFET starts switching after
brownout event, VINon, and the rectified input voltage below which the Power MOSFET is
switched off, VINoff. Thanks to the IBRhyst, see Table 8, these two thresholds can be set
separately.
Doc ID 022218 Rev 1
29/35
Operation description
VIPER37
Figure 33. Brownout protection: BR external setting and timing diagram
6).
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6).OFF
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When the VINon and the VINoff levels are fixed, with reference to Figure 33, the following
relationships can be established for the calculation of the resistors RH and RL:
Equation 9
RL = −
VBRhyst
IBRhyst
+
VINon − VINoff − VBRhyst
VINoff − VBRth
×
VBRth
IBRhyst
Equation 10
RH =
VINon − V INoff − V BRhyst
I BRhyst
×
RL +
RL
V BRhyst
I BRhyst
For a proper operation of this function, VIN on must be less than the peak voltage at
minimum mains and VIN off less than the minimum voltage on the input bulk capacitor at
minimum mains and maximum load.
The BR pin is a high impedance input connected to high value resistors, it is therefore prone
to pick up noise, which might alter the OFF threshold when the converter operates or
creates an undesired switch-off of the device during ESD tests.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent
any malfunctioning of this kind.
If the brownout function is not used, the BR pin must be connected to GND, ensuring that
the voltage is lower than the minimum VDIS threshold (50 mV), see Table 8.
30/35
Doc ID 022218 Rev 1
VIPER37
Operation description
In order to enable the brownout function, the BR pin voltage must be higher than the
maximum VDIS threshold (150 mV), see Table 8.
8.13
2nd level overcurrent protection and hiccup mode
The device is protected against short-circuit of the secondary rectifier, short-circuit on the
secondary winding, or a hard-saturation of the flyback transformer. Such an anomalous
condition is invoked when the drain current exceeds the threshold IDMAX (see Table 8).
To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a
“warning state” is entered after the first signal trip. If, in the subsequent switching cycle, the
signal is not tripped, a temporary disturbance is assumed and the protection logic is reset in
its idle state; otherwise, if the IDMAX threshold is exceeded for two consecutive switching
cycles, a real malfunction is assumed and the Power MOSFET is turned off.
The shutdown condition is latched as long as the device is supplied. While it is disabled, no
energy is transferred from the auxiliary winding; hence the voltage on the VDD capacitor
decays to the VDD undervoltage threshold (VDDoff), which clears the latch.
The startup HV current generator is still off, until the VDD voltage goes below its restart
voltage, VDD(RESTART). After this condition the VDD capacitor is charged again by a 600 µA
current, and the converter switching restarts if the VDDon occurs. If the fault condition is not
removed the device enters auto-restart mode. This behavior results in a low-frequency
intermittent operation (hiccup-mode operation), with very low stress on the power circuit.
See the timing diagram of Figure 34.
Figure 34. Timing diagram: hiccup-mode OCP
Secondary diode
short circuit
VDD
VDDon
VDDoff
VDD(RESTART)
IDRAIN
time
IDMAX
time
VDRAIN
time
Normal operation
Hiccup-mode
Doc ID 022218 Rev 1
31/35
Package mechanical data
9
VIPER37
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 12.
SDIP10 mechanical data
mm
Dim.
Min.
Typ.
A
5.33
A1
0.38
A2
2.92
4.95
b
0.36
0.56
b2
0.51
1.15
c
0.2
0.36
D
9.02
10.16
E
7.62
8.26
E1
6.1
7.11
E2
7.62
E3
10.92
e
L
32/35
Max.
1.77
2.92
Doc ID 022218 Rev 1
3.81
VIPER37
Package mechanical data
Figure 35. SDIP10 mechanical drawing
Doc ID 022218 Rev 1
33/35
Revision history
10
VIPER37
Revision history
Table 13.
34/35
Document revision history
Date
Revision
17-Feb-2012
1
Changes
Initial release
Doc ID 022218 Rev 1
VIPER37
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