L6452 Dual 13x16 Matrix Head Ink Jet Driver Features ■ DRIVES TWO 13X16 MATRIX HEADS ■ HEAD TEMPERATURE SENSING ■ POWER UP SYSTEM ■ ELECTRICAL NOZZLE CHECK ■ 8 BIT A/D ■ 5 BIT D/A ■ ± 4KV ESD PROTECTED OUTPUTS PQFP100 Description L6452 is a device designed to drive two 13x16 matrix ink jet print heads in printer applications. The output stage is able to source simultaneously 400 mA on each of the 16 power lines (columns) with a duty cycle of 33% in normal printing and 66% in head pre-heating. On the address lines (rows), the load is only capacitive (MOS FET driving capability). The driver can control two print heads, but only one is active at a time. The address scanning counter is included and can be disabled to allow a different scanning scheme. In order to avoid output activation during the supply transient, an internal power-up system is implemented. As supporting function, L6452 is capable of sensing the head silicon temperature and to electrically check each nozzle. The device protection. is also integrating a thermal Order codes Part number Op. Temp range, °C Package Packing E-L6452 0 to 70 PQFP100 Tray L6452DIE8 0 to 70 DIE -- February 2006 Rev 2 1/22 www.st.com 22 L6452 Contents Contents 1 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 DC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Counter Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Decoder Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Print Head Temperature Control Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Print Head Block Diagram (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 L6452 1 Block diagrams Block diagrams Figure 1. Block diagram 16 POWER LINES POWER & LOGICAL SUPPLIES PRINT HEAD DRIVER CONTROL LINES 13 ADDRESS LINES CHANNEL A PRINT HEAD A 13 ADDRESS LINES CHANNEL B A/D & PRINT HEAD TEMPERATURE CONTROL LINES Figure 2. PRINT HEAD TEMPERATURE CONTROL PRINT HEAD B ANALOG INPUTS D97IN523 Block Diagram: Power Line Output Stage. Va 1.25mA DATA BIT 0 1 0 OUTPUT0 DATA BIT 1 FROM 16 BIT DATA LATCH OUTPUT1 DATA BIT 15 LONGPULSE OUTPUT15 SHORTPULSE TRIGGER NCOUT NCEN D97IN525B 3/22 L6452 Block diagrams Figure 3. Block Diagram: Nozzle activation part LONGPULSE SHORTPULSE OUTPUT0 OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 OUTPUT6 16 BIT SERIAL INPUT & PARALLEL OUTPUT 16 BIT LATCH 16 POWER OUTPUT STAGES OUTPUT7 OUTPUT8 OUTPUT9 OUTPUT10 OUTPUT11 OUTPUT12 OUTPUT13 OUTPUT14 OUTPUT15 SDI SDC LATCHCLEAR LATCHDATA NCEN NCOUT HSA1 HSA2 HSA3 HSA4 HSA5 13 MOS DRIVERS CHANNEL A 0 to 13 UP/DOWN COUNTER HSA6 HSA7 HSA8 HSA9 HSA10 C0 C1 SELECTOR HSA11 HSA12 4 to 13 LINES DECODER HSA13 C2 HSB1 ENIC HSB2 C3 S3 HSB3 UPC/S2 HSB4 RESC/S1 HSB5 CLKC/S0 13 MOS DRIVERS CHANNEL B HSB6 HSB7 HSB8 HSB9 HSB10 CHSEL HSB11 HSB12 ENCH HSB13 D97IN524A 4/22 L6452 Pin description S3 CHSEL UPC/S2 RESC/S1 ENCH CLKC/S0 STEPUPGND STEPUPBOOST VSTEP-UP Va CSGND VDD REXT RXB RXA VXA VXB ONENABLE CRCLOCK Pin connection (Top view) CRDATA Figure 4. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CRLATCH 1 80 ENIC OUTPUT15 2 79 GND VC 3 78 HSA1 POWGND 4 77 HSA2 OUTPUT14 5 76 HSA3 OUTPUT13 6 75 HSA4 VC 7 74 HSA5 OUTPUT12 8 73 HSA6 OUTPUT11 9 72 HSA7 VC 10 71 HSA8 OUTPUT10 11 70 HSA9 OUTPUT9 12 69 HSA10 HSA11 VC 13 68 OUTPUT8 14 67 HSA12 POWGND 15 66 HSA13 OUTPUT7 16 65 Vr VC 17 64 HSB13 OUTPUT6 18 63 HSB12 OUTPUT5 19 62 HSB11 VC 20 61 HSB10 OUTPUT4 21 60 HSB9 OUTPUT3 22 59 HSB8 VC 23 58 HSB7 OUTPUT2 24 57 HSB6 OUTPUT1 25 56 HSB5 VC 26 55 HSB4 POWGND 27 54 HSB3 OUTPUT0 28 53 HSB2 LATCHCLEAR 29 52 HSB1 NCEN 30 51 GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Table 1. CH1 CH2 CH3 CH4 CH5 VREF Va ADCGND ADDATA ANALOGND CH0BUF NCOUT ADCK CONVSTART RESET SHORTPULSE LONGPULSE SDC SDI D97IN489C LATCHDATA 2 Pin description Pin function Pin # Name 1 CRlatch 2, 5, 6, 8, 9, 11, 12, 14, 16, 18, 19, 21, 22, 24, 25, 28 Output15...0 Function A rising edge transfer the information from CR shift register into the control register latching the data on the falling edge High side DMOS outputs. To be active, ShortPulse and/or LongPulse and NcEn must have a low level 5/22 L6452 Pin description Table 1. Pin # Name 3, 7, 10, 13, 17, 20, 23, 26 Vc Outputs Power Supply 4, 15, 27, 51, 79, 92 GND logic and power ground 29 LatchClear Function A high level resets all bit in the latch 30 NcEn A high level enables the internal current sources and disables all DMOS outputs. To be active, the internal current sources must have their corresponding bit set in the 16 bit latch and LongPulse must be set to low level. This function is called Nozzle Check Enable. 31 LatchData A rising edge latches the 16 bit stored in the shift register in the 16 bit latch 32 SDI Serial data input of the shift register 33 SDC The data bit presented to the SDI pin is stored into the register on the rising edge of this pin 34 LongPulse A low level activates all outputs having their corresponding bit in the 16 bit latch set (this pin has an internal pull-up resistor) 35 ShortPulse A low level activates all outputs having their corresponding bit in the 16 bit latch reset (this pin has an internal pull-up resistor) 36 Reset A low level disables all functions and clears all registers 37 ConvStart A high level enables the A/D to start the new conversion 38 ADCK A/D clock signal; the ADDATA signal are valid on the falling edge of this pin 39 NCOut If NcEn is high this output provides a high level when the open load is detected on the output. If NcEn is low this output provides a high level when a short circuit is detected on HSA/B output 40 CH0buf Analog output signal (CH0 buffered) 41 ADDATA A/D serial data output 42 AnalogGND 43 ADCGND 44, 90 Va 45 Vref 46 to 50 CH5..CH1 52 to 64 HSB1..HSB13 65 Vr 66 to 78 HSA13..HSA1 80 6/22 Pin function - continued EnlC Analog ground connection Ground of internal ADC Power supply Reference voltage generator A/D input signals Head selector address output channel B Head Select Power Supply Head selector address output channel A Enable Internal Counter: A high level enables the counter and the internal decoder will activate of the HSx outputs according to the counter’s outputs. Signal S0 becomes ClkC and S1 becomes ResC L6452 Pin description Table 1. Pin function - continued Pin # Name Function 81 ChSel 82 S3 83 UpC/S2 UpCount/S2: A high level enables the internal counter to up counting. A low level enables down counting depending on EnlC value it becomes S2. 84 ResC/S1 Reset Count/S1: A low level resets the internal counter depending on EnlC value it becomes S1. 85 EnCh Enable Channel: A low level enables the selected channel (this input has an internal pull up resistor) 86 ClkC/S0 A high level clocks the internal counter depending on EnlC value it becomes S0. 87 StepUpGND Ground of step up block 88 StepUpBoost Boost voltage 89 VstepUp 91 VDD 5V logic supply 93 Rext An external resistor connected to ground fixes the internal current source value 94, 95 RxB, RxA Current source outputs 96, 97 VxA, VxB RxA, RxB voltage after an optional external filter 98 OnEnable A low level enables the current source generator according the A/B and ON/OFF control register bit 99 CRclock Data on pin CRdata are stored into the register on the rising edge of this pin 100 CRdata Control register serial data input Channel Select: A low level enables channel A and a high level enables channel B Decoder input signals when EnIC is low Driving voltage of power DMOS stage 7/22 L6452 Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit Vc Power line supply voltage 14 V Vr Address line supply voltage 14 V Va Analog supply voltage 14 V Vdd Logic supply voltage 6 V Driving voltage of power DMOS stage 28 V In accordance with IEC 1000-4-2 (1) ±4 kV Vstep_up ESD Vin Logic input voltage range -0.3 to Vdd + 0.3 V Iout Output continuous current 0.5 A Tj Junction temperature 150 °C 0 to 70 °C -55 to 150 °C Tamb Operating temperature range Tstg Storage temperature range (1) All the pins connected to the pen passed ESD Contact Electrostatic Discharge @ ±4kV (150pF, 330Ohm source). 3.2 DC Electrical characteristics Table 3. Symbol 8/22 DC Electrical characteristics (Tj = 25°C) Parameter Test Condition Min. Typ. Max. Unit (2) 11.5 12.5 V 10.5 Vc Power Line Supply voltage (1) Vr Address line supply voltage (1) 10.5 11.5 12.5 V Va Analog supply voltage (1) 10.5 11.5 12.5 V Vdd Logic supply voltage 4.5 5 5.5 V Ics Vc sleep supply current 1 mA Irs Vr sleep supply current 0.3 mA Ias Va sleep supply current 3 mA Ic Vc supply current 1.5 mA Ir Vr supply current 0.6 mA Ia Va supply current 13 mA OnEnable = 1 Reset = 0 IRext= 3mA L6452 Table 3. Electrical specifications DC Electrical characteristics (Tj = 25°C) - continued Symbol Parameter Test Condition Idd Vdd supply current sleep or normal condition Vref Reference Voltage Tamb= 5 to 55°C Irefext 4.85 Typ. 5 Reference current (external) Programmed constant current V ref I ccs = --------------- ⋅ 4 2R ext ∆Iccs/Iccs Constant current regulation Va=11V Tamb = 5 to 55°C Vampout Output voltage of integrated Iccs Min. 12 Max. Unit 5 mA 5.15 V 7 mA 13.5 mA 0.33 e (3) % Va-1 V 7 V amplifier Vcm Operating input voltage at pins Vref= 5V g1=1.2 g2 = 3 Vxa and Vxb g1 Amp. A1 Voltage gain 1.188 1.2 1.212 g2 Amp.A2 Voltage gain 2.95 3.02 3.10 Vstep-up Driving Voltage of power DMOS Vc +11 V A/D CONVERTER VA/D in A/D input voltage Selected Channel: CH1 to CH5 Selected Ch=CH0 Iexch A/D input current Input CH1 to CH5 selected or not 0 e (3) Vref Vref V V ±1 µA 7.34 V OFFSET VOLTAGE GENERATION / DAC Voffset Offset Voltage Vref = 5V Vstep Voltage increment (1LSB) Vref= 5V Kdac Voffset/Vref Any step N ≥ 4 2.5 + e (3) 156 mV ±3 % A/D CONVERTER TIMINGS Tcscks ConvStart set up time 200 ns Tcsckh ConvStart hold time 200 ns Tckout Falling edge of clock to data out valid delay Cload ≤ 20pF 200 ns Tcsz ConvStart falling edge to output in Hi-Z delay 200 ns Fadck Clock frequency 250 KHz Tcslow Conv. Start low level time 5.6 µs 9/22 L6452 Electrical specifications Table 3. DC Electrical characteristics (Tj = 25°C) - continued Symbol Parameter Test Condition Min. Typ. Max. Unit Tacqth Theoretical acquisition time fadck= 250 kHz 32.4 µs Tacqpr Real acquisition time fadck= 250 kHz 36 µs DIGITAL INTERFACE INPUT Vinp Schmitt Trigger positive-going Threshold Vinm Schmitt Trigger negative-going Threshold Vhys Schmitt Trigger Hysteresis 0.1 0.3 1 V Input Current (Vin=0; Vdd=5) (4) 50 150 300 µA Iin 2/3Vdd 1/3Vdd V V CR LATCH TIMINGS Tls Latch set up time 100 ns Tlhigh Latch high time 100 ns Tlconv Latch data valid to A/D input valid delay 4 7 µs µs tstore Latching data time 200 ns Note: Selected channel: CH1..CH5 CH0 The control register (driving signals CRdata, CRclock) is accessed with the same timing specifications as the data 16 bit shift register (signals SDI, SDC) SHIFT REGISTER AND LATCH TIMING Ta Set up time 35 ns Tb Hold time 35 ns Tc Serial clock low time 35 ns Td Serial clock high time 35 ns Te Serial clock period 125 ns Tf Latch set up time 100 ns Tg Latch data high time 100 ns Tset NcEn setup time with respect to LongPulse (or ShortPulse) Asserted 160 ns Thold NcEn hold time with respect to LongPulse (or ShortPulse) Asserted 0 ns Tlp Set-up time from latch to Pulse (short and long) 125 ns Tpl Time from Pulse deassertion to new data latching 125 ns 10/22 L6452 Table 3. Electrical specifications DC Electrical characteristics (Tj = 25°C) - continued Symbol Parameter Test Condition Min. Typ. Max. Unit OUTPUTS ELECTRICAL CHARACTERISTICS Output Current (outputs 0..15) DC=33%; preheating DC=66% On Resistance Tj= 25°C 1.3 Ω Tpdr Power output Turn on Time From 50% LongPulse to 90% power output rising edge Load = 30 Ohm in parallel with 1.5nF 160 ns Tpd Toff delay time From 50% LongPulse to 90% power output falling edge Load = 30 Ohm in parallel with 1.5nF 100 ns Rpon Open Nozzle Check 2 kΩ Iout Rds(ON) 400 0.5 1 mA HEAD ADDRESS SELECTOR OUTPUT Th UpC/S2, ResC/S1, ChSel, ClkC/S0 and EnIC set-up time with respect to EnCh 150 ns Tk UpC/S2, ResC/S1, ChSel, ClkC/S0 and EnIC hold time with respect to EnCh 50 ns Tj UpC/S2 with respect to hold time ClkC/S0 200 ns Ti UpC/S2 with respect to setup time ClkC/S0 100 ns Tm Enable input to active output delay time 100 ns Tn Clock to active output delay time 150 ns To Disable input to inactive output delay time 100 ns 1 MHz 90 % 325 ns 325 ns fclk-counter Clkdc Counter Clock Frequency Clock duty cycle Ton Address Turn on time Toff Address Turn off time 10 From 50% ClkC/S0 or selector signal to 90% of the address output variation Load: see Figure 11. (1) The three supply voltage are independent inside the specified value; (2) The Min. value for Vc power line has been verified down to 4V in application lab.; nevertheless the parameters are guaranteed within spec limit of the above DC ELECTRICAL CHARACTERISTICS table. (3) e = 2 · Vstep (4) This applies to input pins having an internal pull-up (ENCH, LONGPULSE, SHORTPULSE) 11/22 L6452 Electrical specifications 3.3 Counter Truth Table EnIC = 1 UpC/S2 = 1 ResC/S1 = 1 Clock Counter C3 C2 C1 C0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 Clock Counter C3 C2 C1 C0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 EnIC = 1 UpC/S2 = 0 ResC/S1 = 1 12/22 L6452 3.4 Electrical specifications Decoder Truth Table OUTPUTS (HS) ACTIVE C3* C2* C1* C0* All inactive 0 0 0 0 1 0 0 0 1 2 0 0 1 1 3 0 0 1 0 4 0 1 1 0 5 0 1 1 1 6 0 1 0 1 7 0 1 0 0 8 1 1 0 0 9 1 1 0 1 10 1 1 1 1 11 1 1 1 0 12 1 0 1 0 13 1 0 0 0 All inactive 1 0 0 1 All inactive 1 0 1 1 * C3 = S3, C2 = S2, C1 = S1, C0 = S0, when EnIC = 0 This table is valid for both Channel A and Channel B and when EnCh is set to low level. 13/22 L6452 Print Head Temperature Control Part 4 Print Head Temperature Control Part 4.1 Introduction For quality printing, it is necessary to know and control the temperature of the print head. Thus, the latter has a built - in aluminium resistor, whose value changes slightly with the temperature. The temperature determination is done by injecting a constant current in the resistor, and measuring the voltage drop across it. Since high - end printers have two heads, it must also be possible to switch quickly the measurement process from one to the other. The function is foreseen to be integrated into the head driver, and is described hereafter. 4.2 Print Head Block Diagram (Figure 5.) At first we have a constant current source, which can be disabled by an external pin (OnEnable) or by a control register, described later. The value of the current can be programmed by an external resistor, and is given by: V ref ⋅ 4 I CCS = ------------------2 ⋅ R ext This current is injected either into the resistor of the head A (Ralu. A) or B (Ralu. B), depending of the switch SW3. The resistors are grounded, and the voltage at their << hot >> side (Vx) is re-entered via the pins VxA and VxB. Using separate pins from RxA and RxB permits to be more flexible, and a filter can eventually be added as shown in the drawing. The voltage Vx is amplified by A1 and A2, and then converted in a digital value. To be compatible with the input range of the A/D converter, it is necessary to subtract an offset voltage Voffset from Vx. Moreover, as the initial value of the aluminum resistor is very imprecise. Voffset must be adjustable; this is done by means of a 5 bit - D/A converter, giving 32 different values. Finally, the voltage at the input of the A/D converter is: VCH0 = g1 · g2 · VX - g2 × VOFFSET or VCH0 = g1 · g2 · Ralu · ICCS - g2 · VOFFSET; VOFFSET = VREF/2 + N · VREF/32 N = 0, 1, ...31 The reference voltage generator (VREF) is integrated, and used for the current source and both the A/D and D/A converters. In this way, the system performance is independent from the precision of VREF; this one should, however, be stable. Vref is also available on pin #45, and can be used for low consumption purposes. (The external sinked current has to be a DC current). The system is under control of a 10 bit register, CR. CR is accessed serially and has a transparent latch, which can be used or not (by trying the latch signal CR latch to VCC). 14/22 L6452 Print Head Temperature Control Part Figure 5. Print Head Block Diagram VREF Va VREF OUT HIGH-SIDE CONSTANT CURRENT SOURCE REXT A2 + g2 - g1 VREF ADCK D ADDATA CH0 CH5 CH4 VREF/2 CH3 VOFFSET + VREF Vx A/D INPUTS CH2 CH1 A SW1 ONENABLE CONVSTART A A1 REF VOLT D/A 5 BIT B SW2 CH0BUF D C SW3 LATCH 10 BIT SHIFT REG. 10 BIT A/B RXA, RXB RALU A ON/OFF DA4 DA3 DA2 DA1 DA0 ADDR2 ADDR1 ADDR0 CRLATCH CONTROL REGISTER CRCLOCK CRDATA VXA, VXB ANALOG GND RALU B Note; the analog ground is separated from the digital ground of the remaining part of the driver Figure 6. D97IN533C Control Register details. SHIFT DIRECTION CR9 CR8 CR7 CR6 CR5 CR4 CR3 A/B ON/OFF DA4 DA3 DA2 DA1 DA0 ADDR2 ADDR1 ADDR0 D/A INPUTS FOR OFFSET COMPENSATION SELECTION OF RESISTOR A (A/B = 0) or B (A/B = 0) for TEMPERATURE MEASUREMENT DA0 = LSB DA4 = MSB CR1 CR0 CHANNEL SELECTION A/D INPUT D97IN534B ONE INTERNAL CHANNEL (VX MEASUREMENT) FIVE UNCOMMITTED, GENRAL-PURPOSE EXTERNAL CHANNELS POSITIVE LOGIC SWITCHES THE CURRENT SOURCE ON or OFF; LINKED WITH ONENABLE INPUT PIN CR2 ADDR2 ADDR1 ADDR0 CHANNEL ADDRESS CH0BUF 0 0 0 0 (INTERNAL) A ON/OFF ONENABLE ACTION 0 0 1 1 (EXTERNAL) B 0 1 OFF 0 1 0 2 (EXTERNAL) B 1 1 OFF 0 1 1 3 (EXTERNAL) B 0 0 OFF 1 0 0 4 (EXTERNAL) B 1 0 ON 1 0 1 5 (EXTERNAL) B 1 1 0 6 C 1 1 1 7 D 15/22 L6452 Print Head Temperature Control Part Figure 7. CR Latch Timings CRDATA DA0 ADDR2 ADDR1 ADDR0 CRCLOCK tls tlhigh tstore CRLATCH tlconv CONVSTART D97IN535B Figure 8. A/D Converter Timings CONVSTART ADCK ADDATA 7 HIGH IMPEDANCE tcscks 6 5 4 3 2 1 tcsx Power Output Timing LONGPULSE or SHORTPULSE 50% 50% 90% 90% POWER OUTPUT tpdr tpd (*) D97IN526B (*) tpd does not include the falling edge time because this is strictly dependent on the RC load. Figure 10. Trigger of Nozzle Check Signal VLOGIC VPOWER FROM THE COMMON CONNECTION OF ANALOG MULTIPLEXERS - 1 NOZZLE CHECK OUTPUT + 0 INTERNAL REFERENCE NCEN HSA/B SHORT CIRCUIT DETECTION D97IN527A 16/22 HIGH IMPEDANCE tckout tcsckh Figure 9. 0 D97IN536 L6452 Print Head Temperature Control Part Figure 11. Address load reference 200Ω HS OUTPUT A 250pF Figure 12. Mode Counter UpC/S2 ResC/S1 ChSel EnIC ClkC/S0 ti tj EnCh tk th HSA1 : 13 or HSB1 : 13 tm tn D97IN529B to 17/22 L6452 Print Head Temperature Control Part Figure 13. Mode Selelector Sel 0:3 ChSel EnIC EnCh tk th HSA1 : 13 or HSB1 : 13 tm tn D97IN530A to Figure 14. Sequence of Shift Register Data Loading SDI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDC LATCHDATA LONGPULSE SHORTPULSE D0 OUTPUT * OUTPUT ** * THE CORRESPONDING DATA BIT IS SET ** THE CORRESPONDING DATA BIT IS RESET tpl tlp D97IN531C 18/22 L6452 Print Head Temperature Control Part Figure 15. Latch Timing ta tb SDI SDCK LATCHDATA tf tc D97IN532A tg td te 19/22 L6452 Package information 5 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 16. PQFP100 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. A A1 2.55 B 0.22 C 0.13 D 22.95 D1 19.90 D3 e E1 13.90 E3 20/22 2.80 3.05 0.100 0.38 0.0087 0.23 0.005 23.20 23.45 0.903 20.00 20.10 0.783 OUTLINE AND MECHANICAL DATA 0.120 0.015 0.009 0.913 0.923 0.787 0.791 0.026 17.20 17.45 0.667 14.00 14.10 0.547 0.80 0.110 0.742 12.35 0.65 MAX. 0.134 0.65 16.95 K TYP. 0.010 18.85 E L MIN. 3.40 0.25 A2 L1 inch MAX. 0.677 0.687 0.551 0.555 0.486 0.95 0.026 1.60 0.031 0.063 0°(min.), 7°(max.) 0.037 PQFP100 L6452 6 Revision history Revision history Date Revision 15-Mar-1999 1 06-Feb-2006 2 Changes Initial release. Modified Electrical Specification and any Time Diagrams. Modified pin and signal names through out the spec. Modified Table 1 Pin function pins 83, 84 & 86. Added ESD parameter in the Table 2 Absolute maximum ratings. Modified Table 3: Tset, Thold and Rpon parameters. Modified Figure 14. 21/22 L6452 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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