Product Preview MC13180PP/D Rev. 2, 08/2002 MC13180 2.4 GHz Low Power Wireless Transceiver IC for Bluetooth™ Applications Package Information Plastic Package Case 1314 (QFN-48) Ordering Information Device Marking Package PC13180FC PC13180FC QFN-48 The MC13180 2.4 GHz Low Power Wireless Transceiver for Bluetooth™ is a part of the comprehensive Bluetooth platform from Motorola that provides a complete, low-power Bluetooth Radio System for Bluetooth Class 1 or 2 power systems. The design is based on Motorola's third-generation Bluetooth architecture that has set the industry standard for interoperability, complete functionality, and compliance with the Bluetooth specification. When combined with a specified Motorola baseband controller such as the MC71000 or MC9328MX1, a complete Bluetooth solution can be realized. The MC13180 provides a unique combination of sensitivity, excellent C/I performance, and low power consumption. These performance parameters are extremely important to maintaining a robust link in high RF interference environments such as mobile phones, high density Bluetooth networks, 802.11b networks, microwave ovens, etc. • Power Supply Range: 2.5 to 3.1 V • Low Current Drain in Transmit (27 mA Peak) or Receive (37 mA Peak) Mode • Minimum External Components • Low IF Receiver with On-Chip Filters • Fully Integrated Demodulator with A/D • Direct Launch Transmitter • Multi-Accumulator, Dual-Port, Fractional-N Synthesizer • RSSI with A/D • Bluetooth Class I Compatible • Crystal Independent (12 to 15 MHz) Reference Oscillator or 12 to 26 MHz if supplied externally This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2002. All rights reserved. Antenna T/R Switch LNA 24 MHz External T/R Enable 6-Bit, 4x Oversample A/D Rx/Tx Enable °45 Phase Splitter LPA Printed Balun Limiter Σ Demod PMA °45 Ramp Generator External PA Enable BPF Rx/Tx Data RSSI A/D High/Low Side Image Reject Mixer Programmable GFSK LUT PA Enable 2.5 GHz VCO External PA Control ±°90 Phase Splitter CP/ LPF Integer-N Synthesizer Internal Clocks D/A Reference Oscillator 3 - Acc Dual-Port, Frac-N Synthesizer Dividers 24 MHz CP/ LPF Reset Rx/Tx Control Functions 2 Internal Memory 3 ControlBus Interface Bus Rx/Tx Data Clock LPF LPF VCC This device contains 81,604 active transistors. Xtal Figure 1. Simplified Block Diagram 2 MC13180 Product Preview MOTOROLA VCCLNA GNDMIX VCCMIX VCCMOD GNDMOD GNDVCO VCCVCO GNDPRE VCCPRE MLPF GNDCP VCCCP 48 47 46 45 44 43 42 41 40 39 38 37 VCC GNDLNA VCC VCC VCC VCC High/Low IR Mixer 1 VCC 36 VSS LPF LNA 4 PRE LC VCC 5 PA+ 6 GNDPA 7 PA- 8 GPO 9 EPADAC 10 Frac-N 33 RES LUT 32 CE PA Buff SPI PA Ramp Generator 31 SDATA 30 SCK RSSI Limiter VCCPA 34 VDDINT PMA SPI EPAEN T/R CP SPI A/D 29 CLK Logic Core(LC) 3 35 VDD D/A H/L Select from SPI BPF GNDLNA VDD Main VCO 2 LC D/A SPI Demod RFIN DC PLL/VCO 27 RFDATA LC A/D TIN+ 11 28 FS 26 RTXEN Test MUX VCC 25 VCCDC TIN- 12 VCC VCC 20 21 22 23 24 DCVCO DCCP VCCLIM 19 COLL GNDLIM 18 EMM TOUT- 17 BASE 16 GNDX 15 VCCDEM 14 GNDDEM 13 TOUT+ Ref Osc Figure 2. Device Pinout MOTOROLA MC13180 Product Preview 3 Electrical Characteristics 1 Electrical Characteristics Table 1. Maximum Ratings Ratings Symbol Value Supply Voltage VCCRF VDDINT Unit V 3.2 3.2 TJ 150 °C Tstg -60 to 150 °C Junction Temperature Storage Temperature Range NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Recommended Operating Conditions and Electrical Characteristics tables. 2. Meets Human Body Model (HBM) ≤2.0 kV and Machine Model (MM) ≤200 V except RF & I/O Pins = 50 V MM, RF Pins = 100 V HBM, and I/O Pins <500 V. RF pins have no ESD protection. Additional ESD data available upon request. Table 2. Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit Power Supply Voltage VCCRF 2.5 2.7 3.1 Vdc Power Supply Voltage, Logic Interface (VDDINT ≤ VCCRF) VDDINT 1.65 - VCCRF Vdc Input Frequency fin 2.4 - 2.5 GHz Ambient Temperature Range TA -20 25 85 °C Ref Osc Frequency Range (only integral multiples of 20 kHz may be used) With Crystal External Source fref MHz 12 12 13 - 15 26 Table 3. Digital DC Electrical Specifications (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25°C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults in Figure 4, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Min Typ Max Unit - 0.2 0.5 2.0 3.0 µA mA Supply Current CE, SDATA, SCK, RFDATA, RTXEN, Vin = 0 V or 1.8 V RES, Vin = 0 V (Reset Mode) RES, Vin = 1.8 V (Idle Mode) ICCINT Radio Power Supply Current, Sleep Mode ICCRFsleep - 2.0 10 µA ICCRFidle - 3.4 4.0 mA Radio Power Supply Current, Idle Mode 4 Symbol MC13180 Product Preview MOTOROLA Electrical Characteristics Table 3. Digital DC Electrical Specifications (Continued) (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25°C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults in Figure 4, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Radio Power Supply Current Transmit, 1 Slot Transmit, 3 Slot Transmit, 5 Slot Transmit, Continuous Symbol Min Typ Max ICCRFtx1 ICCRFtx3 ICCRFtx5 ICCRFtxc - 22 25 26 27 33 ICCRFrx1 ICCRFrx3 ICCRFrx5 ICCRFrxc - 30 34 35 37 47.5 - 20 - 0.2 x VDDINT Unit mA Radio Power Supply Current Receive, 1 Slot Receive, 3 Slot Receive, 5 Slot Receive, Continuous mA Output Voltage Low SDATA, CLK, FS, RFDATA ILoad = 0 µA ILoad = 100 µA VOL Output Voltage High SDATA, CLK, FS, RFDATA ILoad = 0 µA ILoad = 100 µA VOH Output Voltage Low EPAEN, GPO ILoad = 0 µA ILoad = 100 µA VOL Output Voltage High EPAEN, GPO ILoad = 0 µA ILoad = 100 µA VOH Input Voltage Low RES, CE, SDATA, SCK, RFDATA, RTXEN mV V V 0.8 x VDDINT 1.78 - - - 20 - 0.2 x VCCRF mV V V 0.8 x VCCRF 2.68 - - VIL - 0 0.3 x VDDINT V Input Voltage High RES, CE, SDATA, SCK, RFDATA, RTXEN VIH 0.7 x VDDINT VDDINT - V Input Current RES, CE, SDATA, SCK, RFDATA, RTXEN, Vin = 0 V or 1.8 V Iin - ±1.0 - µA MOTOROLA MC13180 Product Preview 5 Electrical Characteristics Table 4. EPA DAC Electrical Specifications (VCCRF = 3.1 Vdc, VDDINT = 1.8 Vdc, TA = 25°C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults in Figure 4 except R11/7 = 1, unless otherwise noted.) Characteristic Symbol Output Voltage EPADAC, ILoad = ±100 µA PADAC = 000000 PADAC = 100000 PADAC = 111111 Min Typ Max 2.5 0.02 1.60 3.08 0.4 - Vout Unit V Resolution RESOL - 6 - Bits Linearity INL/DNL - ±1.0 ±2.0 LSB ICCDAC - 197 500 µA Average Supply Current (1-slot packet) Table 5. Digital AC Electrical Specifications (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25°C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults in Figure 4, unless otherwise noted. See Figure 3 Test Circuit and Figure 12 Timing Diagram.) Characteristic Symbol Min Typ Max Unit Propagation Delay, RTXEN to FS, receive mode TpropFS - 168 - µs Receiver Latency, LNA In to RFDATA, receive mode RXLAT - 1.0 - µs Receive Disable Time TRXDIS - 0 - µs Tstb - TXsync + 0.5 - µs TXsync 182 184 192 µs Thold - 4.0 - µs TXLAT - TXsync + 2.5 - µs TBit - 1.0 - µs TTXDIS - 20 - µs 30 40/60 70 % Strobe Delay, RTXEN to RFDATA, transmit mode Transmit Sync Delay (i.e., R8/15-8) Hold Time, RTXEN to RFDATA, transmit mode Transmit Latency, RTXEN to PAout, transmit mode Transmit Data Rate, Bit transfer rate to RFDATA, transmit mode Transmit Disable Time CLK Duty Cycle 6 MC13180 Product Preview MOTOROLA Electrical Characteristics Table 6. Receiver AC Electrical Specifications (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Desired RFin = 2.441 GHz @ fdev = 157.5 kHz, Interferer fdev = 160 kHz, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Modulating data for desired signal = PRBS9, Modulating data for interfering signal = PRBS15, Measured BER < 0.1%, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = 25°C, unless otherwise noted. Measurements made from LNAin to Recovered Data out. See Figure 3 Test Circuit.) Characteristics Typ - -85 -80 -75 - -1.5 - SENSmax -20 >0 - ≥ -20 dBm C/I co - 8.0 11 ≤ 11 dB C/I 1MHz - -8.0 0 ≤0 C/I 2MHz - -33 -30 ≤ -30 C/I ≥3MHz - -46 -40 ≤ -40 Image Frequency Interference @ -67 dBm C/I image - -17 -9.0 ≤ -9.0 dB Adjacent Interference to In-Band Image Frequency @ -67 dBm C/I image ±1 - -33 -20 ≤ -20 dB - 2 5 5 -39 -31 - ≥ -39 - -70 -56 -57 -47 ≤ -57 ≤ -47 SENSmin Receiver Sensitivity degradation in the presence of a dirty transmitter Maximum Usable Signal Level Co-Channel Interference @ -60 dBm Adjacent Channel Interference Adjacent (±1 MHz) Interference @ -60 dBm Adjacent (±2 MHz) Interference @ -60 dBm Adjacent (≥3 MHz) Interference @ -67 dBm Spurious Response Frequencies Intermodulation Performance [Note 1] Receiver Spurious Emissions 30 MHz to 1.0 GHz 1.0 GHz to 12.75 GHz Receiver Blocking Performance (See Figure 29) [Note 2] 30 MHz to 2.0 GHz (1.999 GHz) 2.0 to 2.399 GHz (2.399 GHz) 2.498 to 3.0 GHz (2.498 GHz) 3.0 to 12.75 GHz (3.001 GHz) Max Bluetooth Specs Min Receiver Sensitivity TA = 25°C TA = -20 to 85°C Symbol Unit dBm ≤ -70 dB dB dBm dBm dBm -25 -27 -27 -10 -9.0 -16 -16 2.0 - ≥ -10 ≥ -27 ≥ -27 ≥ -10 NOTE: 1. Measured at f2 - f1 = 5.0 MHz in accordance to Bluetooth specification. 2. As allowed by the Bluetooth Specification, up to 5 exceptions may be taken for spurious response. MOTOROLA MC13180 Product Preview 7 Electrical Characteristics Table 6. Receiver AC Electrical Specifications (Continued) (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Desired RFin = 2.441 GHz @ fdev = 157.5 kHz, Interferer fdev = 160 kHz, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Modulating data for desired signal = PRBS9, Modulating data for interfering signal = PRBS15, Measured BER < 0.1%, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = 25°C, unless otherwise noted. Measurements made from LNAin to Recovered Data out. See Figure 3 Test Circuit.) Characteristics Symbol RSSI Conversion Value, (R4/6 and R9/8 = 1) RF level at LNA input to maintain conversion value of: 1000 1111 RSSI RSSI Resolution (R4/6 and R9/8 = 1) RSSIres RSSI Dynamic Range RSSI Average Supply Current (R4/6 and R9/8 = 1) Min Typ Max Bluetooth Specs Unit dBm -60 - -56 -70 -52 -66 - 1.8 - dB/bit 20 - - dB - 40 - µA Table 7. Transmitter AC Electrical Specifications (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = -20 to 85°C, unless otherwise noted. Measurements made at PAout. See Figure 3 Test Circuit.) Min Typ Max Bluetooth Specs -3.5 -3.5 -3.5 1.9 0.1 2.4 4.0 4.0 4.0 -6.0 to 4.0 -6.0 to 4.0 -6.0 to 4.0 OccBW - 930 1000 ≤1000 In-Band Spurious Emissions Adjacent Channel ±2.0 MHz Offset Adjacent Channel ±3.0 MHz Offset Adjacent Channel ≥3.0 MHz Offset Inb2 Inb3 Inbg3 - -59 -65 -70 -20 -40 -40 ≤ -20 ≤ -40 ≤ -40 In Band Spurious Emission Exceptions Inbex - 0 3 ≤3 Out of Band Spurious Emissions 30 MHz to 1.0 GHz 1.0 to 12.75 GHz (2nd Harmonic) 1.8 to 1.9 GHz 5.15 to 5.3 GHz Outb1 Outb2 Outb3 Outb4 - -57 -19 -58 -56 -36 -5.0 -47 -47 ≤ -36 ≤ -30 ≤ -47 ≤ -47 Dev 140 157.5 175 140 to 175 kHz DevMin 11.5 148 - 115 kHz High vs Low Frequency Modulation Percentage ModIn 80 93 - ≥ 80 % Initial Frequency Accuracy InitFA -75 ±5.0 -75 ±75 kHz Characteristics RF Transmit Output Power TA = 25°C TA = 85°C TA = -20°C -20 dBc Occupied Bandwidth Peak Frequency Deviation Minimum Frequency Deviation 8 Symbol Pout Unit dBm kHz dBm dBm MC13180 Product Preview MOTOROLA Electrical Characteristics Table 7. Transmitter AC Electrical Specifications (Continued) (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = -20 to 85°C, unless otherwise noted. Measurements made at PAout. See Figure 3 Test Circuit.) Characteristics Symbol Min Typ Max Bluetooth Specs d1 d3 d5 -25 -40 -40 ±3.0 ±6.0 ±6.0 25 40 40 ±25 ±40 ±40 Dmax - 3.0 20 20 Transmitter Center Frequency Drift One-slot packet Three-slot packet Five-slot packet Unit kHz Maximum Frequency Drift PA Output Impedance S22 kHz/ 50 µs See Table 23 dB Table 8. Receiver AC Electrical Specifications (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = -20 to 85°C, unless otherwise noted. Measurements made at PAout. See Figure 3 Test Circuit.) Characteristic Symbol Min Typ Max Unit SENSmax - ≥0 - dBm - -14 -13 -13 - C/I co - 8.0 - Adjacent Interference, TA = 25°C Adjacent (±1 MHz) Interference @ -70 dBm Adjacent (±2 MHz) Interference @ -70 dBm Adjacent (≥3 MHz) Interference @ -77 dBm C/I 1MHz C/I 2MHz C/I ≥3MHz - -8.0 -41 -47 - Image Frequency Interference @ -77 dBm, TA = 25°C C/I image - -17 - dB Adjacent Interference to In-Band Image Frequency @ -77 dBm, TA = 25°C C/I image ±1 - -33 - dB Maximum Usable Signal Level, TA = -20 to 85°C Receiver Blocking Performance, TA = 25°C W-CDMA 1.8 GHz W-CDMA 2.2 GHz GSM 1.8 GHz Co-Channel Interference @ -60 dBm, TA = -20 to 85°C LNA Input Impedance MOTOROLA dBm dB dB S11 MC13180 Product Preview See Tables 20 and 21 dB 9 Electrical Characteristics Table 9. MC7100/MC13180 Receive Characteristics (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Reference Crystal = 13 MHz, Register bit settings according to specified defaults, unless otherwise noted, interfering access code at the minimum Hamming distance of 14 according to Bluetooth specifications. See Figure 3 Test Circuit.) Characteristic Symbol False Detection Rate In Presence of Noise In Presence of Interfering Access Code @ Actual Sensitivity @ Actual Sensitivity + 10 dB Min Typ Max - 0 - - 0 0 - - 0 0 100 - Unit % Missed Detection Rate @ Actual Sensitivity @ Actual Sensitivity + 10 dB @ Actual Sensitivity - 16 dB % Table 10. Reference Oscillator Receive Characteristics (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25°C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Symbol Min Typ Max Unit fRefXtal 12 - 15 MHz fRefExternal 12 - 26 MHz 0.2 - 0.8 1.0 - Crystal Load Capacitance (Resonant Parallel) - 13 - pF Maximum Crystal Equivalent Series Resistance (ESR) - - 100 W Typical Crystal Adjustment Range - See Figure 19 Recommended Crystal Tolerance over Temperature (-20 to 85°C) - ±10 - ppm - 0 to 9.3 - pF Electronic Parallel Trim Capacitance Resolution - 0.3 - pF Oscillator Bias Current (R11/0) = 0, (R11/4) = 0 or 1 (R11/0) = 1, (R11/4) = 0 (R11/0) = 1, (R11/4) = 1 - 0 50 200 - - 1.0 + - pF - kΩ Crystal Frequency Range (SeeTable 19 for supported frequencies) External Drive Frequency Range (See Table 19 for supported frequencies) Oscillator Drive Level External Reference Crystal Reference Vpp Electronic Parallel Trim Capacitance Range CPT µA Input Impedance at Base (Reference Frequency = 12 to 26 MHz, R11/0 = 0 or 1) Parallel Capacitance CP Parallel Trim Capacitance Parallel Resistance 10 RP MC13180 Product Preview - 20 MOTOROLA Electrical Characteristics Table 10. Reference Oscillator Receive Characteristics (Continued) (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25°C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Symbol Input Bias Voltage (Base) Start-up Time (using Crystal) TWAIT Min Typ Max Unit - 1.2 - V - 7.5 - ms Table 11. Data Clock Electrical Specifications (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25°C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Symbol Min Typ Max Unit Internal Reference Frequency - 20 4000 kHz Data Clock Output Frequency - 24 - MHz R Counter (R6/9-0) (Base 10) 3 650 1023 N Counter (R7/10-0) (Base 10) 3 1200 2047 Loop Filter Bandwidth - 1.0 200 kHz Kpd - 15.9 - µA/rad KVCO - 15 - MHz/V - 1.0 7.5 - Phase Detector Gain Constant VCO Gain Constant Start-up Time External Reference Crystal Reference ms Table 12. SPI AC Electrical Specifications (VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25°C, unless otherwise noted. See Figure 13 Timing Diagram.) Characteristic Symbol Min Typ Max CE to SCK Setup Time Hold Time TsuCE THCE - 20 20 - SDATA to SCK Setup Time Hold Time TsuD THD - 20 20 - SCK to SDATA Propagation Delay Tprop - 20 - ns SCK Operating Frequency (50% Duty Cycle) fmax - - 20 MHz TSUSPI - 20 - ns ns ns SPI Setup Time to RTXEN (See Figure 12) MOTOROLA Unit MC13180 Product Preview 11 C12 560p VccRF PA Out SMA Johnson 142-0701-881 LNA In SMA Johnson 142-0701-881 R5 TL1 TL2 620 C11 1.5p (±0.1 pF) 620 C4 3.3 p C10 22p MC13180 Product Preview TL3 TL4 L1 3.9n Default Units: Microfarads, Microhenries and Ohms Printed Transmission Lines TL1 = 77 W, 9.9° @ 2.45 GHz TL2 = 77 Ω, 9.9° @ 2.45 GHz TL3 = 77 Ω, 10.5° @ 2.45 GHz TL4 = 77 Ω, 10.5° @ 2.45 GHz TL5 = 50 Ω TL6 = 50 Ω TL7 = 50 Ω TL8 = 50 Ω C13 33p R6 TL5 TL6 VccPA VccVC O GNDLNA RFIN GNDLNA EPAEN VCCPA PA+ GNDPA PAGPO EPADAC TIN+ TIN- VccLIM VccDEMO 13 MHz NDK Y1 W-168-179 1 2 3 4 5 6 7 8 9 10 11 12 U7 270p R4 27k VccCP VccPRE VccMIX VccMOD VccLNA 48 47 46 45 44 43 42 41 40 39 38 37 MC13180 C5 C8 12p 22p C2 33n 36 35 34 33 32 31 30 29 28 27 26 25 VccXTAL SDATA SCK CLK FS RFDATA RTXEN VCCDC VSS VDD VDDINT RES CE VCCLNA GNDMIX VCCMIX VCCMOD GNDMOD GNDVCO VCCVCO GNDPRE VCCPRE MLPF GNDCP VCCCP 13 14 15 16 17 18 19 20 21 22 23 24 12 TOUT+ TOUTGNDLIM VCCLIM GNDDEM VCCDEM GNDX BASE EMM COLL DCVCO DCCP C7 NRES NCEN SPID SPICK CLK FS RFDataIO RTXEN VccRF Vdd C18 6.8p C22 100n C23 2.2n VccLNA VccDC C37 1.0 µ VddINT C26 100n VccCP C24 6.8 p VccPRE VccVCO VccMIX VccMOD Data_IO FS CLK JD/MSLE C29 100n Recovered Data Vdd C31 100n VccPA Recovered Clock VccLIM VccDEMO C28 100n VccDC VccXTAL Clock Data Electrical Characteristics Figure 3. Test Circuit MOTOROLA Register Number MOTOROLA 6 7 8 9 10 11 12 13 14 15 16 17 18 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 5 $05 $06 4 $04 MC13180 Product Preview 0 0 1 MSB 1 MSB 0 MSB 1 MSB 1 MSB 1 0 0 1 MSB 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 0 MSB 0 1 External PA Enable = GPO 1 1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 Xtal Trim 0 1 1 0 1 1 0 1 0 0 1 0 0 0 High/Low Injection Enable Bit 11 1 0 Narrow Bandwidth Enable Bit 12 Byte 1 ROM_r4_c3 ROM_r3_c4 ROM_r3_c2 ROM_r2_c4 ROM_r2_c2 0 0 1 0 0 1 1 1 1 0 0 0 1 M-Dual Port Digital Multiplier Value for Tx PLL 1 1 0 0 0 1 1 1 1 Transmit Synchronization Time Delay Value Dual Port Programmable Delay For Tx PLL 0 1 1 0 1 0 0 1 0 0 2 Rx Test Tx Test 0 Rx Enable Tx Enable Sleep Enable 3 1 0 0 1 0 1 Bit 13 MSB Bit 14 1 MSB Bit 15 Rx Test Tx Test $03 $02 $01 $00 Programmable Reset Register Address MC13180: 0 1 1 1 0 0 1 1 1 1 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 0 MSB MSB 0 0 0 0 0 1 0 Bit 9 LSB 0 0 0 External PA Enable Invert 1 1 1 0 Bit 10 Bit 7 1 1 0 1 0 0 0 0 1 MSB 1 MSB 0 LSB 0 MSB 0 LSB 1 MSB 0 LSB 1 MSB 0 LSB 0 0 1 0 0 1 1 1 0 MSB 1 External PA Enable 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 1 1 DC Pll N Counter 0 1 0 Bit 3 1 0 1 1 0 1 1 0 1 1 1 0 1 1 Frac-N Integer Divide Valu 1 1 Bit 4 PA DAC Setting 0 0 0 1 0 0 0 0 ROM_r4_c4 ROM_r4_c2 ROM_r3_c3 ROM_r3_c1 ROM_r2_c3 ROM_r1_c1 Xtal Boost Enable 1 1 0 0 1 1 1 0 0 0 1 1 1 0 B-Dual Port Digital Multiplier Value For Tx PLL DC Pll R Counter 1 0 MSB General Purpose Output Invert RSSI Read Enable 1 1 1 0 Bit 5 0 0 1 1 Bit 6 External PA DAC Enable LSB 1 0 1 0 0 RSSI Enable MSB 1 1 1 1 LSB 0 0 0 0 1 MSB General Purpose Output 1 1 1 1 1 16 Bit Frac-N Numerator Divide Value - num Bit 8 Byte 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 1 1 1 1 0 0 1 1 PA Bias Adjust 0 0 0 0 1 1 Bit 1 Bit 0 0 1 LSB 0 LSB 0 LSB 1 LSB 1 LSB 0 LSB 1 Xtal Enable 1 1 0 LSB 0 LSB 0 LSB 0 1 0 LSB 1 0 LSB 0 0 LSB LSB Electrical Characteristics Figure 4. Register Map 13 14 21 $15 23 24 25 26 27 28 Read Only 29 Read Only 30 Read Only 31 Read Only $17 $18 $19 $1A $1B $1C $1D $1E $1F 22 20 $14 $16 19 $13 MC13180 Product Preview 0 MSB 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 Version Number Bit 3:0 of Part Number 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 Manuf. ID (continuation code) 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 MSB 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 MSB 0 0 1 0 1 0 0 0 0 0 1 1 0 1 Manuf. ID (non-continuation code) Bit 15:4 of Part Number 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 LSB 0 RSSI Conversion 0 0 1 0 1 0 0 0 0 0 1 1 1 0 LSB 0 1 1 1 1 0 0 0 0 0 Electrical Characteristics Figure 4 Register Map (continued) MOTOROLA Pin Connections 2 Pin Connections Table 13. Pin Function Description Pin Symbol/ Type 1 GNDLNA 2 RFIN Equivalent Internal Circuit Description GNDLNA, Negative supply GNDLNA is the ground for the LNA. 1 Bias LNA output to balun 2 RF in T/R 3 3 GNDLNA 48 VCCLNA 1.7 mA 4 6.8 pF EPAEN VCC 4 NOTE: GNDLNA, Negative supply GNDLNA is the ground for the LNA. VCCLNA, Positive supply VCCLNA is taken to the incoming positive battery or regulated dc voltage through a low impedance trace on the PCB. It is decoupled to GNDLNA at the pin of the IC. 48 VCC RFIN RFIN is the RF input to the LNA. The LNA is a bipolar cascode design. The input is the base of the common emitter transistor. Minimum external matching is required to optimize the input return loss and gain. The cascode output drives the primary of an on-chip balun single-ended. VCC Sequence Manager Control or SPI Control EPAEN External PA enable is a digital output which can be used to enable an external PA. It can be controlled via SPI or placed under sequence manager control. This output can also be used to control an external T/R switch requiring complementary drive. VCC = VCCRF MOTOROLA MC13180 Product Preview 15 Pin Connections Table 13. Pin Function Description (Continued) Pin Symbol/ Type 5 VCCPA 7 GNDPA GNDPA, Negative Supply GNDPA pin is taken to an ample dc ground plane through a low impedance path. The path should be kept as short as possible. A multi-sided PCB is implemented so that ground returns can be easily made through via holes. 6 PA+ PA + Positive differential PA output. An external differential-to-single-ended matching network is desired. 8 PA - PA Negative differential PA output. An external differential-to-single-ended matching network is desired. 9 GPO Equivalent Internal Circuit See Figure 5. VCCPA, Positive Supply VCCPA pin is taken to the incoming positive battery or regulated dc voltage through a low impedance trace on the PCB. It is decoupled to GNDPA at the pin of the IC. VCC VCC 9 10 SPI Control EPADAC VCC 10 NOTE: 16 Description VCC SPI Control GPO The General Purpose Output is a digital output. GPO can be controlled by the SPI. This signal can also be used to control an external T/R Switch. EPADAC External PA driver. Analog output ranges from 0.02 to VCCRF - 0.02. The EPADAC is linearly scaled to a maximum VCC of 3.1 V. VCC = VCCRF MC13180 Product Preview MOTOROLA Pin Connections Table 13. Pin Function Description (Continued) Pin Symbol/ Type 11 TIN + Equivalent Internal Circuit Inject/Monitor Decoder 12 VCC TIN - TOUT + SPI RX/TX Chain 11 13 Description TIN This pin is for factory use only. It can be grounded or left open. TOUT + This pin is for factory use only. It must be left open. VCC 12 14 TIN + This pin is for factory use only. It can be grounded or left open. TOUT - TOUT This pin is for factory use only. It must be left open. VCC 13 VCC 14 15 GNDLIM 15 VCC 16 VCCLIM 17 GNDDEM 100 nF 16 17 VCC 18 NOTE: VCCDEM GNDLIM, Negative supply GNDLIM is the ground for limiter. VCCLIM, Positive supply VCCLIM is decoupled to GNDLIM at the pin of the IC. GNDDEM, Negative supply GNDDEM is the ground for demodulator. 100 nF 18 VCCDEM, Positive supply VCCDEM is decoupled to GNDDEM at the pin of the IC. VCC = VCCRF MOTOROLA MC13180 Product Preview 17 Pin Connections Table 13. Pin Function Description (Continued) Pin Symbol/ Type 19 GNDX 20 BASE Equivalent Internal Circuit Description GNDX Reference oscillator ground. 19 100 nF VCC 22 1.6 V 13 MHz 21 EMM 20 22 pF 50 kΩ 21 COLL 23 DCVCO Trim Bias Current 12 pF 22 10 mA CPT DC VCO Control Voltage 23 VCC 24 33 nF 9.0 kΩ DCCP 25 VCCDC 26 RTXEN Charge Pump 25 100 nF VCCDC Data clock VCC. The pin of the IC is bypassed to gnd. VDDINT VDDINT 26 NOTE: 18 DCVCO Data Clock Loop Filter VCO control voltage. This pin can be used to raise/lower the loop corner frequency in conjunction with the DCCP pin and external components. DCCP Data Clock Loop Filter charge pump. VCC VCC EMM Reference oscillator emitter. A bias current of 50 µA is supplied internally to the emitter. COLL Reference oscillator collector. The collector is tied to VCC. The pin of the IC is bypassed to gnd. Shown for 13 MHz reference oscillator. VCC 24 BASE Reference oscillator base. The base is the reference oscillator input. An on-chip capacitor trim network is also included to allow the user to use relatively inexpensive crystals. RTXEN When RTXEN is asserted (high), it controls the start of the Rx or Tx cycle. Digital input. The logic level is internally shifted to the VDD supply. VCC = VCCRF MC13180 Product Preview MOTOROLA Pin Connections Table 13. Pin Function Description (Continued) Pin Symbol/ Type 27 RFDATA Equivalent Internal Circuit Description VDDINT VDDINT 27 28 VDDINT FS VDDINT FS Frame-sync digital output (used for Rx only). In Receive mode, this signal brackets a 6-bit sample frame. VDDINT 28 29 CLK VDDINT VDDINT 29 30 SCK VDDINT RFDATA This digital I/O is used for Transmit Data (input) and Received Data (output). When in transmit mode, the logic level is internally shifted to the VDD supply. VDDINT CLK Clock associated with RF data path. The Clock Frequency must always be programmed to 24 MHz. Digital output. SCK SPI clock. 30 NOTE: VCC = VCCRF MOTOROLA MC13180 Product Preview 19 Pin Connections Table 13. Pin Function Description (Continued) Pin Symbol/ Type 31 SDATA Equivalent Internal Circuit Description VDDINT VDDINT 31 32 VDDINT CE VDDINT VDDINT VDDINT VDDINT 32 33 RES 33 34 VDDINT I.0 mF VDD 35 VCC 1 µF 36 NOTE: 20 CE Chip enable is active low enable to facilitate SPI transfers. Digital input. The logic level is internally shifted to the VDD supply. RES Asynchronous Digital Reset (Active Low). Resets MC13180 register settings to a default value. Digital Input. The logic level is internally shifted to the VDD supply. VDDINT Digital interface supply voltage. 1.65 V ≤ VDDINT ≤ 3.1 V. VDDINT must, at all times, be ≤ VCC. 34 35 SDATA SPI data. Digital input or output. As an input, the logic level is internally shifted to VDD. 36 VSS VDD Digital core supply. The pin of the IC is bypassed to gnd. Logic Levels are internally shifted from VDDINT to/from VDD. VSS Digital ground. VCC = VCCRF MC13180 Product Preview MOTOROLA Pin Connections Table 13. Pin Function Description (Continued) Pin Symbol/ Type 38 GNDCP Equivalent Internal Circuit Description GNDCP Main frac-N charge pump ground. 38 37 VCCCP V CC 39 MLPF VCCCP Main frac-N charge pump VCC. It is decoupled to GNDCP at the pin of the IC. 100 nF 37 27 kΩ* V CC 270 pF* 10 pF 39 30 kΩ * values shown for 13 MHz reference 41 50 kΩ GNDPRE 41 VCCPRE 42 VCCVCO 40 42 6.8 pF 100 nF 43 GNDVCO 44 GNDMOD VCC VCCMOD 47 GNDMIX 45 VCC NOTE: VCCMIX GNDMOD Modulation DAC ground. 100 nF 47 46 VCCPRE Prescaler VCC. The pin of the IC is bypassed to GNDPRE. GNDVCO VCO ground. 44 45 GNDPRE Prescaler ground. VCCVCO VCCVCO is decoupled to GNDVCO at the pin of the IC. Extreme caution should be used when decoupling/routing to this pin. VCC 43 To VCO MLPF Main frac-N loop filter (Charge Pump). The filter is referenced to VCC. 100 nF VCC 40 3.5 pF VCCMOD Modulation DAC VCC. The pin of the IC is bypassed to GNDMOD. GNDMIX Mixer ground. 100 nF 46 VCCMIX Mixer VCC. The pin of the IC is bypassed to GNDMIX. VCC = VCCRF MOTOROLA MC13180 Product Preview 21 Pin Connections VCC 5 100 nF 7 3.3 pF TL5 VCC 620 Ω 560 pF 33 pF TL4 6 TL2 PAin- 1.5 pF (±0.1 pF) TL1 620 Ω TL3 8 PAin+ (Adjustable Current Source) Vref Figure 5. Equivalent Internal Circuit for Pins 5, 6, 7, and 8 22 MC13180 Product Preview MOTOROLA Typical DC Performance Characteristics 28.5 900 ICCRFtxc, CONTINUOUS TRANSMIT CURRENT (mA) ICCINT, LOGIC INTERFACE CURRENT (µA) 3 Typical DC Performance Characteristics 850 800 750 TA = 25°C 700 650 600 550 500 1.8 2.0 2.2 2.4 2.6 2.8 VDDINT, LOGIC INTERFACE VOLTAGE (V) ICCRFrxc, CONTINUOUS RECEIVE CURRENT (mA) ICCRFtxc,CONTINUOUS TRANSMIT CURRENT (mA) 27 26 10 25 40 55 26.5 TA = 25°C 26 25.5 2.5 2.6 2.8 2.9 3.0 3.1 70 85 39 38.5 38 37.5 37 36.5 36 TA = 25°C 35.5 35 34.5 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 VCCRF, POWER SUPPLY (V) TEMPERATURE (°C) Figure 8. Continuous Transmit Current versus Temperature ICCRFrxc, CONTINUOUS RECEIVE CURRENT (mA) 2.7 Figure 7. Continuous Transmit Current versus Power Supply VCCRF = 2.7 V -5.0 27 VCCRF, POWER SUPPLY (V) 29 25 -20 27.5 25 2.4 3.0 Figure 6. Logic Interface Current versus Logic Interface Voltage (Idle Mode) 28 28 Figure 9. Continuous Receive Current versus Power Supply 39 38 VCCRF = 2.7 V 37 36 35 -20 -5.0 10 25 40 55 70 85 TEMPERATURE (°C) Figure 10. Continuous Receive Current versus Temperature MOTOROLA MC13180 Product Preview 23 Functional Description 4 Functional Description Note: In the following description, control bits contained in the MC13180 register map for various functions will be identified by register number and bit number(s). For example, bit R4/8 references bit 8 of register 4 while R5/9-3 identifies bits 9 through 3, inclusive, of register 5 (decimal notation). Unless otherwise noted, a default register map configuration as listed in Figure 4 is assumed. 4.1 Overview The MC13180 is a complete RF transceiver for Bluetooth applications. The device, when coupled with an MC71000 controller or any controller containing an integrated Joint Detection/Minimum Length Sequence Estimator (JD/MLSE) digital decoder, exhibits superior RF performance with small size and low cost. Only minimal external components are required to complete the RF link of a Bluetooth system. 4.2 MC13180 States Figure 11 illustrates the various states which the MC13180 can assume. A description of each state follows. 4.3 OFF State In the OFF state, no power is being applied to the VCCRF or VDDINT of the device. During this state, all digital inputs should be held at ground to avoid forward biasing internal ESD diodes. 4.4 POWER UP State During this state, power is applied to the device in an orderly fashion. All digital inputs should continue to be held at ground. Since VDDINT of the device must always be less than or equal to the VCCRF supplied to the device, it is generally desired to first allow the VCCRF to rise and stabilize, then follow with applying the VDDINT supply. This prevents internal protection diodes from forward biasing. SPI operations are not allowed during this state. 4.5 RESET State The RESET state can be entered at any time from any state with the exception of the OFF and POWER UP states. During the RESET state, SPI operations are forbidden. The RESET state places the entire contents of the internal register map into a known condition. All digital outputs are active and driven to a logic low. The SDATA I/O pin is configured as an input, and the RFDATA I/O pin is configured as an output. The crystal oscillator is inactive and therefore the CLK output remains at a static low level. 4.6 CONFIG State Once the RES pin is de-asserted, the crystal oscillator and data clock PLL of the device become active. The CLK output will attempt to synthesize a clock frequency based upon the crystal oscillator frequency and values loaded into the data clock N and R registers. These values assume an initial reference frequency of 13 MHz and the data clock values are initialized from reset to synthesize 24 MHz from this reference. 24 MC13180 Product Preview MOTOROLA Functional Description During the Config state, any address location can be read or written. The Sleep Enable, Tx Enable, and Rx Enable bits of the register map must remain at a logic zero, otherwise the register map is typically loaded with user defined default values. 4.7 WAIT XTAL State During this state, the crystal oscillator and data clock PLL are stabilizing. If an external reference oscillator is being used, the data clock PLL must still be allowed to settle. Stability will be achieved after TWAIT, at which time the Idle state is entered. 4.8 IDLE State In the Idle state, the CLK output supplies a synthesized 24 MHz output. Any SPI operation is allowed during this state. RSSI information is typically read during the Idle state. 4.9 TX CONFIG State During this state, the contents of the register map are set for any desired transmit information, including the transmit channel setting. The Tx Enable (R2/14) bit of the register map is also asserted which places the RFDATA pin into the input state at the completion of the SPI write cycle. 4.10 TX WARM UP The MC13180 begins a series of internal warm up sequences once the RTXEN pin is asserted. SPI operations are forbidden during this state. 4.11 TX MODE Data presented to the RFDATA pin is transmitted to the PA output of the device. SPI operations are forbidden during this state. The TX mode is ended by de-asserting the RTXEN pin or by going into the RESET state. SPI operations are not permitted until TTXDIS µs after the RTXEN pin is de-asserted. 4.12 RX CONFIG State During this state, the contents of the register map are set for any desired receive information, including the receive channel setting. The Rx Enable (R2/13) bit of the register map is also asserted which places the RFDATA pin into the output state at the completion of the SPI write cycle. 4.13 RX WARM UP The MC13180 begins a series of internal warm up sequences once the RTXEN pin is asserted. SPI operations are forbidden during this state. 4.14 RX MODE Digitized and oversampled data from the desired receive channel is presented to the RFDATA pin and framed by the FS signal. Data is aligned to the rising edge of the CLK output. SPI operations are forbidden during this state. The RX mode is ended by de-asserting the RTXEN pin or by going into the RESET state. SPI operations are not permitted until TRXDIS µs after the RTXEN pin is de-asserted. MOTOROLA MC13180 Product Preview 25 Functional Description 4.15 SLEEP State The Sleep state is entered by asserting the Sleep Enable (R2/15) bit of the address map. During this mode, the CLK pin is driven to a static logic low level, and the crystal oscillator is disabled. All digital outputs are driven to a logic low level. SPI operations are permitted during this state. The Idle state is entered by de-asserting the Sleep Enable bit of the address map. OFF VCCRF = 0 V VDDINT = 0 V Power Up 2.5 V ≤ VCCRF ≤ 3.1 V 1.65 V ≤ VDDINT ≤ VCCRF RES = 0 * Can be entered from any State Reset RES = 1 Configure “SPI Load” Sleep Sleep EN (R2/15) = 0 Wait XTAL Sleep EN (R2/15) = 1 Wait XTAL Idle RX Enable (R2/13) = 0 TX Enable (R2/14) = 0 TX Enable (R2/14) = 1 RX Enable (R2/13) = 1 TX Configure RX Configure RTXEN = 1 RTXEN = 0 RTXEN = 1 TX Warm Up RX Warm Up TX Mode RX Mode RTXEN = 0 Figure 11. State Diagram 26 MC13180 Product Preview MOTOROLA Functional Description 4.16 Receive Data Path The MC13180 is placed into the receive mode from the idle mode by asserting the RTXEN pin after setting the Receive Enable bit (R2/13), clearing the Transmit Enable bit (R2/14), and clearing the Narrow Bandwidth Enable bit (R2/12) (See Figure 12). The RFDATA pin of the device is configured as an output as soon as these bit conditions are loaded into the register map. The baseband interface signals used in the receive mode are shown in Table 14. The interface signal levels are internally translated to/from VDDINT to VDD. To initiate a receive cycle, the user will set the local oscillator frequency of the device in conjunction with the High/Low Injection Enable bit. Optionally, other address map values may be written or read. During this “SPI” cycle, the device's RTXEN must be de-asserted. After time TSUSPI, the RTXEN pin can be asserted. This initiates a sequence internal to the MC13180 which places it into the receive mode. Serialized, A/D data will appear at the RFDATA pin, framed by the FS pin, after TpropFS. The data represents a 6-Bit, 2’s-complement digital value and is sampled four times for every data bit. Once the receive cycle is complete, the RTXEN pin is de-asserted and the MC13180 begins an internal power down sequence. 4.17 Transmit Data Path The MC13180 is placed into the transmit mode from the idle mode by setting the Transmit Enable bit (R2/ 14), setting the Narrow Bandwidth Enable bit (R2/12), and clearing the Receive Enable bit (R2/13) of the address map, then asserting the RTXEN pin of the device (see Figure 12). The RFDATA pin of the device is configured as an input as soon as these bit conditions are loaded into the register map. The baseband interface signals used in the transmit mode are shown in Table 14. The interface signal levels are internally translated to/from VDDINT to VDD. To initiate a transmit cycle, the user will normally set the desired channel frequency and mode bits mentioned above. Optionally, other address map values may be written or read. During this “SPI” cycle, the device's RTXEN must be de-asserted, ensuring that the device remains in idle mode. After time TSUSPI, the RTXEN pin can be asserted. This initiates a sequence internal to the MC13180 which places it into the transmit mode. Data to be transmitted must be set and stable no later than Tstb after the assertion of RTXEN. The RF data will be present at the PA output after RTXEN time, TXLAT. Subsequent serial data can then continue to be presented to the MC13180 via the RFDATA pin, and the CLK of the device (divided by 24) can be used as the system clock to synchronize the data transfer. Once the data stream has been transmitted and the time Thold is met, the RTXEN pin is de-asserted and the MC13180 begins an internal power down sequence. Since RF power is still present at the PA output, no SPI operations or additional cycles can be performed for at least TTXDIS µs. At this time, RF power is at a substantially low enough level as to not produce undesired emissions. 4.18 Transmit Synchronization Delay A programmable delay exists between the rising edge of RTXEN and the first available bit of data. This delay range is TXsync and is set via SPI bits of Transmit Synchronization Time Delay Value (R8/15-8) where the value represents the delay in microseconds. Packet data is seen at the antenna approximately 2.5 µs after this delay. Refer to Figure 12 for the corresponding timing diagram. All Bluetooth packets require a minimum of four preamble bits of pattern 0101 or 1010. For minimum power consumption, set the delay to TXsync minimum. If additional settling time or preamble bits are required, manipulate the delay as necessary, up to TXsync maximum. MOTOROLA MC13180 Product Preview 27 Functional Description 4.19 Main Loop Bandwidth During a transmit cycle, Narrow Bandwidth Enable (R2/12) must be set to a logic one. During a receive cycle this bit must be set to a logic zero. Changing the loop bandwidth of the Main Loop Filter in this manner maximizes radio performance. Note that this bit is externally gated by the sequence manager. Table 14. Data Direction and Signal Description for the MC13180 Baseband Interface 28 Pin Name RX Direction RX Mode Description RFDATA MC13180 → Baseband RX data FS MC13180 → Baseband Start of each 6-bit sample RTXEN MC13180 ← Baseband Receive mode enable CLK MC13180 → Baseband Data sample clock Pin Name TX Direction TX Mode Description RFDATA MC13180 ← Baseband TX data FS MC13180 → Baseband Signal is unused and remains low RTXEN MC13180 ← Baseband Transmit mode enable CLK MC13180 → Baseband Data sample clock MC13180 Product Preview MOTOROLA MOTOROLA MC13180 Product Preview LNA IN RFDATA FS CLK RTXEN SPI PA OUT RFDATA CLK RTXEN SPI TpropFS TSUSPI Tstb TSUSPI … … 2 2 3 TXLAT 3 4 5 6 12 D0 TBIT … 1 … 23 2 3 RX Cycle 22 4 24 5 1 6 D1 2 … 1 2 Valid RF 3 RXLAT Valid RF D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 D5 D4 1 1 TX Cycle 12 Dn 22 … … … … THOLD … 23 24 TRXDIS TTXDIS …… …… GND VDDINT GND GND VDDINT VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT Functional Description Figure 12. TX and RX Cycle Timing 29 Functional Description 4.20 Serial Peripheral Interface (SPI) Basic functionality of the MC13180 is controlled by configuring the internal address map of the device (see Figure 4). The address map is completely read/writable and is organized as 32 addresses of 2-bytes (16-bits) each. The serial interface to this map is controlled by the CE, SDATA, and SCK pins. In addition, the entire address map can be placed into a known state by either asserting the RES pin or by writing to address zero of the device. Logic interface levels are controlled by the VDDINT pin. The interface signal levels are internally translated to/from VDDINT to VDD. The non-standard SPI uses a bi-directional SDATA pin to transfer information to/from the MC13180. Data is clocked into and out of the device on the rising edge of SCK (SCK is of RZ format). The CE pin enables the device SPI and transfers the contents of the SPI shift register to the decoded address when de-asserted. The MC13180 device address is defined to be 01 (binary). This scheme allows for up to three additional SPI devices to be cascaded together without requiring an additional chip enable line. Figure 13 shows a SPI write operation. SPI transfers begin with the assertion of the CE pin when RES is de-asserted. The first bit clocked into the SPI is the R/W bit which equals a logic zero to indicate a SPI write operation. The next two bits are the MC13180 device address (i.e., 01). The remaining five bits of the address field represent the target address to which information will be transferred. The data field proceeds the address field. Data is clocked into the SPI from MSB to LSB. Once the LSB has been entered, the CE pin is de-asserted and the data field contents are transferred to the MC13180's target address. A SPI write to address zero resets all register map values to their initial (reset) condition. Figure 13 also shows a SPI read operation. The first bit clocked into the SPI is now a logic one, indicating a read operation is desired. Again, the next two bits clocked into the SPI are 01, the MC13180 device address. The next five bits of the address field will be the target address to be read. On the falling edge of the SCK, the SDATA line becomes high impedance. This condition remains until the next rising edge of SCK, where data is driven onto the SDATA pin. Data should be sampled for reading on the falling edge of SCK. Once all data has been shifted out of the SPI, the CE pin is de-asserted and the SDATA line becomes an input to the MC13180. Again, reading from address zero will reset the entire register map values to their initial condition. Important Note: All SPI signals (CE, SCK, and SDATA) should remain completely static during an active receive or transmit cycle to prevent digital feedthrough to the RF portions of the chip. Failure to follow this condition can cause severe performance degradation. SPI Write Operation RES CE T suCE THCE THD R/W 0 SDATA 1 A5 A4 A3 A2 A1 A0 D15 D14 D1 0 SCK D0 0 VDDINT 0V VDDINT 0V VDDINT 0V VDDINT 0V TsuD SPI Read Operation RES CE SDATA R/W 0 1 A5 A4 A3 A2 A1 A0 Hi Z D15 D14 … … SCK fmax D1 D0 Hi Z VDDINT 0V VDDINT 0V VDDINT 0V VDDINT 0V Tprop Figure 13. SPI Register Map 30 MC13180 Product Preview MOTOROLA Functional Description 4.21 Crystal Oscillator The crystal oscillator provides the reference for the data clock PLL and main PLL. It can be configured as a Colpitts type (negative resistance) oscillator and utilize an external parallel resonant crystal or may be driven from an external source. The oscillator circuit has an on-chip capacitor trim network that provides the capability to compensate for crystal and/or load capacitor tolerances. This allows the use of relatively inexpensive crystals with as much as 50 ppm tolerance. The oscillator also provides three bias current modes. Xtal Enable (R11/0) enables/disables the bias current and Xtal Boost Enable (R11/4) enables/ disables a high current mode. Refer to the Reference Oscillator Electrical Characteristics for the available current modes. Table 15 gives examples of parallel trim capacitances that can be programmed to register map location Xtal Trim (R6/14-10). Typical stray capacitance is on the order of 1.0 pF. To drive the oscillator with an external source, program the Xtal Enable (R11/0) to zero and ac-couple the external signal into the oscillator base with a 15 to 100 pF capacitor. It is also recommended to set Xtal Trim (R6/14-10) to zero to reduce the load on the external source. Additional characteristic data is shown in Figures 14 through 19. Table 15. Examples of Programmable XTAL Trim Capacitances XTAL Trim (R6/14-10) Setting (MSB to left) Electronic Parallel Crystal Trim Capacitance (CPT) 00000 0 pF 00100 1.2 pF 10000 4.8 pF 10101 6.3 pF 11111 9.3 pF OSCILLATOR NEGATIVE RESISTANCE (Ω) OSCILLATOR OPEN LOOP GAIN (dB) 16 14 12 10 See Figure 42, TA = 25°C Open Loop Gain Measurements @ -10 dBm Crystal Load Capacitance = 13 pF Electronic Trim (R6/14-10) = 16 (decimal) 8.0 6.0 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 CRYSTAL CAPACITOR RATIO (C5/C8) Figure 14. Oscillator Open Loop Gain versus Capacitor Ratio MOTOROLA 0 -50 TA = -20°C -100 85°C -150 -200 -250 25°C -300 See Figure 42, TA = 25°C Curve Measured with 13 MHz Crystal Reference Crystal Load Capacitance Ratio = 1.8 (C5/C6) -350 0 4.0 8.0 12 16 20 24 28 32 ELECTRONIC PARALLEL CRYSTAL TRIM (R6/14-10) Figure 15. Oscillator Negative Resistance versus Electronic Parallel Crystal Trim (CPT) (Crystal Boost Enable R11/4) = 0 MC13180 Product Preview 31 Functional Description OSCILLATOR NEGATIVE RESISTANCE (Ω) OSCILLATOR NEGATIVE RESISTANCE (Ω) 0 -200 TA = -20°C -400 -600 See Figure 42, TA = 25°C Curve Measured with 13 MHz Crystal Reference Crystal Load Capacitance Ratio = 1.8 (C5/C6) -800 -1000 -1200 -1400 85°C 0 25°C 4.0 8.0 12 16 20 24 28 32 -40 -50 See Figure 42, TA = 25°C Curve Measured with 13 MHz Crystal Reference Parallel Crystal Trim (R6/14-10) = 16 (decimal) -60 -70 -80 -90 -100 -110 -120 -130 0 0.5 1.0 ELECTRONIC PARALLEL CRYSTAL TRIM (R6/14-10) Figure 16. Oscillator Negative Resistance versus Electronic Parallel Crystal Trim (CPT) (Crystal Boost Enable R11/4) = 1 2.5 3.0 See Figure 42, TA = 25°C 13 MHz Crystal Reference 10 9.0 8.0 7.0 0 1.0 2.0 3.0 4.0 5.0 See Figure 42, TA = 25°C Crystal Frequency Delta measured relative to intial frequency for R/14-10 = 12 (decimal). 400 200 0 -200 -400 -600 0 4.0 CAPACITOR RATIO (C5/C8) 8.0 12 16 20 24 28 ELECTRONIC PARALLEL TRIM VALUE (R6/14-10) Figure 18. Crystal Start-up Time versus Capacitor Ratio Figure 19. Crystal Frequency Pulling versus Electronic Parallel Trim Value 4.22 Data Clock Operation The data clock phase lock loop is responsible for providing a constant 24 MHz reference for use throughout the device. The MC13180 uses a simple integer-N synthesizer to derive a 24 MHz clock (CLK) from the reference frequency. The counter values must always be set to the appropriate values to generate this 24 MHz clock frequency. The general model for the Phase Lock Loop (PLL) is illustrated in Figure 20. For the circuit in Figure 42, the external low pass filter has a loop filter bandwidth (LBW) of 1.0 kHz. This proves to be adequate for any value of external reference frequency that is an integral multiple of 20 kHz. More details about PLL loop filters can be obtained from Motorola application note AN1253/D. The R-counter of the synthesizer (R6/9-0) is set to a value which will set the internal reference frequency frefInternal to 20 kHz; thus R = frefExternal / 20 kHz. The N-counter of the synthesizer (R7/10-0) is set to multiply frefInternal to 24 MHz; thus N = 24 MHz / frefInternal. For the case of a 13 MHz external reference, R = 65010 and N =120010. 32 3.5 600 CRYSTAL FREQUENCY PULLING (Hz) CRYSTAL START-UP TIME (ms) 2.0 Figure 17. Oscillator Negative Resistance versus Crystal Capacitor Ratio (Crystal Boost Enable R11/4) = 0 11 6.0 1.5 CAPACITOR RATIO (C5/C8) MC13180 Product Preview MOTOROLA 32 Functional Description For applications utilizing frefExternal > 20 MHz, the external low pass filter with a 1.0 kHz corner frequency is still usable. However, due to the R counter limitations, the R counter is programmed to generate the frefInternal to 40 kHz (recommended). For the case of a 26 MHz external reference, R = 65010 and N = 60010. The N and R counters can only divide by integer values and the greatest common divider must be found to represent frefInternal and achieve CLK. Table 16 provides the appropriate values for various frefExternals. For applications that require a faster data clock PLL response time, refer to the data clock electrical characteristics and Motorola application note AN1253/D. Additional data clock characteristic data is shown in Figures 21 and 22. Table 16. Data Clock R and N Counter Values for 20 kHz frefInternal with 1.0 kHz LBW frefExternal (MHz) frefInternal (kHz) R Counter (Decimal) N Counter (Decimal) LBW (kHz) 12 20 600 1200 1.0 13 20 650 1200 1.0 14.4 20 720 1200 1.0 16.8 20 840 1200 1.0 19.22 20 961 1200 1.0 19.68 20 984 1200 1.0 19.88 20 994 1200 1.0 26 40 650 600 1.4 frefExternal frefInternal ÷R Phase Detector (Kpd) Filter (Kf) VCO (KVCO) fo Divider (Kn) Figure 20. General Model for the PLL Where: Kpd = Phase Detector Gain Constant Kf = Loop filter transfer function KVCO = VCO Gain Constant Kn = Divide Ratio (1/N) frefInternal = Input Frequency fo = Output frequency fo/N = Feedback frequency divided by N MOTOROLA MC13180 Product Preview 33 Functional Description 12 DATA CLOCK START-UP TIME (ms) DATA CLOCK START-UP TIME (ms) 1.2 Externally Driven frefExternal = 12 to 26 MHz TA = 25°C 1.0 0.8 0.6 0.4 0.2 0 10 9.0 8.0 7.0 6.0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 See Figure 42, TA = 25°C frefExternal = 13 MHz Crystal frefInternal = 20 kHz 11 0 1.0 2.0 3.0 4.0 5.0 CAPACITOR RATIO (C5/C8) frefInternal (MHz) Figure 21. Data Clock Start-up Time versus frefInternal Figure 22. Data Clock Start-up Time versus Capacitor Ratio for Crystal Reference 4.23 Main Synthesizer Operation The internal local oscillator (LO) of the MC13180 is derived from the external reference frequency by means of a 3-accumulator, fractional-N synthesizer. The external low pass filter (C7/R4 of Figure 3) has a corner frequency of approximately 140 kHz. fdev is the nominal transmit ROM frequency deviation (typically 157500 Hz). I is the integer portion of the fractional synthesizer R is the numerator portion of the fractional synthesizer frefExternal is the external reference frequency LO is the desired local oscillator frequency then, I = INT (LO/frefExternal - fdev/frefExternal) - 3 R = REM(LO/frefExternal - fdev/frefExternal) x 216 where the INT function is the integer portion of the result and REM is the remainder portion of the result. For Example: fdev = 157500 Hz LO = 2.441 GHz frefExternal = 13 MHz then, I = INT(2.441 GHz/13 MHz - 157.5 kHz/13 MHz) - 3 = 18410 R = REM(2.441GHz/13 MHz - 157.5 kHz/13 MHz) x 216 = 4961810 Accuracy to at least 10 decimal places is suggested. 34 MC13180 Product Preview MOTOROLA Functional Description 4.24 Transmit ROM Operation The MC13180 uses a look-up table (LUT or Transmit ROM) to shape incoming transmit data bits and produce a Gaussian filtered mask with BT=0.5. The value of the current data bit, along with knowledge of the previous two bits, determines a unique trajectory for shaping. Only four unique trajectories are required to implement this filter and due to the symmetrical nature of the Gaussian response, these trajectories can be reduced to a single quadrant. Furthermore, without compromising accuracy, this table can be reduced to only 11 values. The output of the LUT is fed to the accumulators of the fractional synthesizer. The seven MSBs are eventually fed to the second port of the main VCO during transmit operation (see Figure 23). For receive operation, the output of the LUT is constantly held to the value contained in R1C1. These 11 trajectory constants are listed in Table 17 (see also Figure 4, Register Map). The actual value to place in the LUT is calculated as: LUT RxCxb10 = (fdev/frefExternal) x 216 x (RxCx constant) This number is then rounded and converted to binary: LUT RxCxb2 = INT((LUT RxCxb10+2)/4) where the INT function is the integer portion of the result. As an example for calculating the LUT value for R4C2 and frefExternal = 13 MHz: LUT R4C2b10 = (157.5kHz/13.0MHz) x 216 x 0.5229292198 = 415.2 LUT R4C2b2 = INT((415.2+2)/4) b10 = INT(104.3) b10 = 104 b10 or 011010000 b2 or 68b16 Table 19 lists all values of RxCx for supported reference frequencies. Table 17. LUT RxCx Constants R1C1 0.9999739537 R2C2 0.9980246857 R2C3 0.9911665663 R2C4 0.9678427310 R3C1 0.1881990082 R3C2 0.5249014674 R3C3 0.7660791186 R3C4 0.9043672052 R4C2 0.5229292198 R4C3 0.7572459756 R4C4 0.8722099597 4.25 M-Dual Port Multiplier and B-Dual Port Multiplier For proper operation of the dual-port synthesizer, it is necessary to maintain a constant deviation injection at the input of Port 2 of the VCO. As can be seen from the Transmit ROM operation and Figure 23, the output of the LUT is fed to a digital multiplier prior to being presented to the input of the modulation DAC. Since the LUT values decrease proportionately with input reference frequency, the multiplier must scale MOTOROLA MC13180 Product Preview 35 Functional Description these values to achieve a constant deviation. This scaling is linear. Two programmable constants are used to form the equation of a line, the M & B dual-port multipliers. M-Dual Port Digital Multiplier Value (R17/ 15-8), determines the slope, and B-Dual Port Digital Multiplier Value (R8/7-0), determines the intercept. M-Dual Port Digital Multiplier = (frefExternal) /13MHz * 10810 B-Dual Port Digital Multiplier = (frefExternal) /13MHz * 10010 Table 19 contains slope and intercept point values across all supported input reference frequencies. 4.26 Dual-Port Programmable Delay (R7/15-11) Just as it is necessary to maintain a constant deviation at Port2 of the VCO, it is also necessary to maintain a constant phase at the FV and FR inputs of the main charge pump. The total delay from the output of the LUT to the FV input of the charge pump is given as: LUT → FV delay = 10.5 / (frefExternal) Likewise, the total delay from the LUT to the FR input of the charge pump is: LUT → FR delay = 28 ns + Delay where delay is the programmed delay value shown in Table 18. Therefore, for a given external reference frequency: Delay = 10.5 / (frefExternal) - 28 ns. Consult Table 18 for the closest available value. Table 19 lists all values of the programmable delay for supported reference frequencies. Table 18. Dual-Port Programmable Delay Values 36 R7/15-11 (decimal) Delayb10 (ns) R7/15-11 (decimal) Delayb10 (ns) 4 167 13 542 5 208 14 583 6 250 15 625 7 292 16 667 8 333 17 708 9 375 18 750 10 417 19 792 11 458 20 833 12 500 21 875 MC13180 Product Preview MOTOROLA 37 MC13180 Product Preview MOTOROLA D7 D7 D5 D0 28 71 A5 C2 70 A3 BC 64 56 R1C1 (R12/7-0) R2C2 (R12/15-8) R2C3 (R13/7-0) R2C4 (R13/15-8) R3C1 (R14/7-0) R3C2 (R14/15-8) R3C3 (R15/7-0) R3C4 (R15/15-8) R4C2 (R16/7-0) R4C3 (R16/15-8) R4C4 (R17/7-0) M-Dual Port Multiplier (R17/15-8) B-Dual Port Multiplier (R8/7-0) 14 4B0 Data Clk N (R7/10-0) Dual Port Programmable Delay (R7/15-11) 258 Fref= 12MHz Data Clk R (R6/9-0) Register 13 64 6C AD 96 68 B4 98 68 25 C0 C5 C6 C6 4B0 28A Fref= 13MHz 11 6E 78 9C 88 5E A2 89 5E 22 AD B2 B3 B3 4B0 2D0 Fref= 14.40MHz 10 75 7F 93 80 58 99 82 59 20 A4 A8 A9 A9 4B0 2FB Fref= 15.26MHz E 81 8C 86 74 50 8B 76 51 1D 95 98 99 9A 4B0 348 Fref= 16.80MHz C 94 A0 75 66 46 79 67 46 19 82 85 86 86 4B0 3C1 Fref= 19.22MHz C 96 A2 74 65 45 78 66 46 19 80 84 84 85 4B0 3CC Fref= 19.44MHz C 97 A3 72 63 45 77 64 45 19 7F 82 83 83 4B0 3D8 Fref= 19.68MHz Table 19. Register Settings and Component Values versus Reference Frequency (all register setting values in hex notation) C 99 A5 71 62 44 75 63 44 18 7E 81 82 82 4B0 3E2 Fref= 19.88MHz 9 C8 D8 56 4B 34 5A 4C 34 12 60 62 63 63 258 28A Fref= 26MHz 38 MC13180 Product Preview MOTOROLA 27 270 0 R4 (kΩ) C7 (pF) C6 (pF) 0 270 27 0 270 24 0 330 22 0 330 20 4.7 390 18 4.7 390 18 4.7 390 18 Table 19. Register Settings and Component Values versus Reference Frequency (Continued) (all register setting values in hex notation) 4.7 390 18 10 560 13 39 MC13180 Product Preview MOTOROLA CLK TX ROM VCO Trim[0..5] Transmit R[0..15] N[0..7] FRef 8MHz TXData[0..7] MULData[0..7] ROMData[0..7] CLK MULData[0..7] Delay N[0..7] R[0..15] SUMRData[2..9] LOIn DELData[1..7] FOut CPOut En D[0..6] MOD DAC FR FV Charge Pump Figure 23. Main PLL Synthesizer Block Diagram Compensation[0..5] TXData[0..7] CLK Multiplier CLK1 CLK2 TXData[0..7] Metastability Frac-N R4 C7 Vout VCC Vin Vout LPF Trim[0..5] Port1 Port2 VCO External Low Pass Filter Internal Low Pass Filter C6 Flo Flo Functional Description 4.27 Receiver The MC13180 receiver is intended to be used in Time Division Duplex (TDD), Frequency Hopping Spread Spectrum (FHSS) applications such as Bluetooth. The receiver uses a low intermediate frequency (IF) of 6.0 MHz, and is capable of receiving up to 1.0 Mbit/s Gaussian Frequency Shift Keyed (GFSK) serial data through the entire 2.4 GHz Industrial, Scientific and Medical (ISM) band. The output of the receiver is a demodulated, serial bit stream of 24 Mbit/s data. This data represents a 4X over sample by a 6-bit D/A of the actual demodulated analog data recovered from the desired channel. A detailed discussion of each of the functional blocks within the receiver follows. 4.28 LNA The first portion of the receiver chain is the Low Noise Amplifier (LNA). The LNA is a bipolar cascode design and provides gain with low noise at RF frequencies. The LNA is designed with a single-ended (unbalanced) input and is converted to a differential (balanced) output by means of an on chip, integrated balun. For optimum performance, the LNA input impedance must be matched to the complex conjugate of the source impedance (usually 50 Ω). The LNA of the MC13180 exhibits two distinctly different impedances depending upon whether the LNA is active or disabled. During a receive cycle, the S11 of the LNA is shown in Table 20. Table 20. S11 for LNA During Receive Frequency MAG (dB) Angle (degree) 2.45 GHz -4.3 -138 The LNA can be matched to 50 Ω by a simple capacitor/inductor network as shown in Figure 24. Lmatch CBlock Cmatch LNA Figure 24. When the LNA is disabled or the device is in the Idle or Transmit mode, the impedance of the LNA becomes the value shown in Table 21. Table 21. S11 for LNA Disabled Frequency MAG (dB) Angle (degree) 2.45 GHz -8.9 42 The use of an antenna switch to interface the LNA with an antenna is the preferred circuit configuration as illustrated in Figure 42. In this implementation, a true RF Single-Pole, Double-Throw (SPDT) switch is used to isolate the PA output from the LNA input during receive and transmit modes. A 1/4 wavelength trace is not required. As a result, this implementation has the highest performance (due to the lowest loss) and smallest size at the 40 MC13180 Product Preview MOTOROLA Functional Description penalty of increased system cost. An external switch must be used for Class 1 Bluetooth devices as the LNA input will become overloaded if not sufficiently isolated from the external PA output. The LNA provides a nominal 6.7 dB of power gain when properly matched. The LNA is enabled approximately 150 µs after the assertion of the RTXEN pin when programmed for Receive mode. It is disabled immediately after the de-assertion of the RTXEN pin or during any Idle or Transmit mode. 4.29 High/Low Image Reject Mixer (I/R Mixer) The mixer is used to convert the desired RF channel to a 6.0 MHz Intermediate Frequency (IF). The mixer is completely balanced on all ports, and the local oscillator (LO) is derived from the buffered output of the on-chip Voltage Controlled Oscillator (VCO). In general, it is desired to keep all image frequencies in-band. Therefore, when receiving the 6 lowest channels, the mixer can be programmed for high-side injection and the LO will be programmed to be 6.0 MHz above the desired channel frequency. When receiving the 6 highest channels, the mixer can be programmed for low-side injection and the LO will be programmed to be 6.0 MHz below the desired channel frequency. This is illustrated in Figure 25. Selection of high or low side injection is accomplished by bit R2/11 of the register map. For all other in-band channels, the choice of high or low side injection is arbitrary, although it is recommended to use high-side injection for frequencies to 2.440 GHz and low-side injection thereafter. LO RF Image High-side LO injection (R2/11=1) LO Image RF Low-side LO injection (R2/11 = 0) Figure 25. High-Side and Low-Side Mixer Injection The mixer delivers approximately 15.8 dB of voltage gain and 22 dB of image rejection. The mixer is enabled approximately 150 µs after the assertion of the RTXEN pin when programmed for Receive mode. It is disabled immediately after the de-assertion of the RTXEN pin or during any Idle or Transmit mode. 4.30 Post Mixer Amplifier (PMA) Once the desired RF channel has been down converted to the IF frequency, the PMA is used to deliver 12 dB of additional gain prior to feeding the signal into the bandpass filter. The PMA is enabled approximately 10 µs after the assertion of the RTXEN pin when programmed for Receive mode. It is disabled immediately after the de-assertion of the RTXEN pin or during any Idle or Transmit mode. MOTOROLA MC13180 Product Preview 41 Functional Description 4.31 Bandpass Filter (BPF) The 6.0 MHz bandpass filter is used to block undesired channels. The filter is self-adjusting and is calibrated during each receive cycle, based on an internally generated 6.0 MHz signal. The gain of the filter is fixed at 4.0 dB. The nominal pass band for the filter is 720 kHz. This deliberately low pass band can cause significant intersymbol interference (ISI) issues for a GFSK modulated signal with a 1Mbit/s data rate. The advantages are increased sensitivity, adjacent channel interference performance and ease of manufacture. Due to this low pass band, a digitally implemented decoder scheme is utilized to eliminate ISI. This is referenced as the JD/MLSE, and is incorporated into all Motorola Bluetooth basebands. The BPF is enabled approximately 10 µs after the assertion of the RTXEN pin while programmed for Receive mode and automatic tuning is complete after approximately 140 µs. It is disabled immediately after the de-assertion of the RTXEN pin or during any Idle or Transmit mode. 4.32 Limiter with Received Signal Strength Indicator (RSSI) The RSSI (received signal strength indicator) is integrated into the limiter. The RSSI ADC converts the RSSI current into a 4-bit digital signal. When the RSSI enable (R4/6) and RSSI Read Enable (R9/8) are both set, the 4-bit RSSI conversion value can be read from the MC13180 register map (R29/3-0) while in Idle mode. The RSSI is updated approximately 40 µs after TpropFS during a receive cycle (see Figure 12). Enabling RSSI will result in additional current consumption as noted in the Receiver AC Electrical Specifications. Figure 26 shows the RSSI conversion value versus the RF level input to the LNA at various temperatures. Figure 27 shows the RSSI conversion versus the RF level at different power supplies. -40 -40 TA = 85°C 2.5 and 2.7 V 55°C -45 25°C -50 RF LEVEL @ RFIN (dB) RF LEVEL @ RFIN (dB) -45 -55 -20°C -60 0°C -65 -40°C -70 -75 1.0 3.0 5.0 7.0 9.0 11 TA = 25°C -50 3.1 V -55 -60 -65 -70 13 15 -75 1.0 3.0 RSSI CONVERSION VALUE 5.0 7.0 9.0 11 13 RSSI CONVERSION VALUE Figure 26. RF Level versus RSSI at Temperature Figure 27. RF Level versus RSSI at VCCRF 4.33 Demodulator The receiver in the MC13180 downconverts the RF signal and demodulates it. The demodulator takes the IF signal from the limiter and delivers a baseband signal to an A/D converter (ADC). The 6-bit ADC uses the Redundant Sign Digit (RSD) Cyclic architecture that samples the analog input at 4.0 Msamples/s. The resulting demodulated data out of the MC13180 is a 24 Mbit/s, 2’s-complement serial bit stream. The start of each 6-bit data stream is indicated by a frame sync (FS) signal. A 24 MHz clock output accompanies the demodulated data. 42 MC13180 Product Preview MOTOROLA 15 Functional Description 4.34 Receiver Characteristics For optimum intermodulation and C/I performance, the MC13180 ground flag requires good conduction to the PCB ground layer. Refer to Figure 48 for additional information. Figures 28 through 34 show typical performance of the receiver for various conditions. -78 80 CONTINUOUS WAVE INTERFERING SIGNAL POWER LEVEL (dBm) -79 SENSITIVITY (dBm) -80 -81 -82 -83 -84 -85 -86 -87 -88 -20 -5.0 10 25 40 55 70 Application Circuit , See Figure 42 60 40 20 0 -20 -40 -60 -80 85 TA = 25°C Power Level Measured for BER < 0.1% Received Frequency = 2.460 GHz Test Circuit , See Figure 3 0 1.0 2.0 TEMPERATURE (°C) 3.0 4.0 5.0 6.0 7.0 CONTINUOUS WAVE INTERFERING SIGNAL FREQUENCY (GHz) Figure 28. Receive Sensitivity versus Temperature Figure 29. Blocking Performance versus Continuous Wave Interfering Signal INTERFERER LEVEL (dBc) 10 0 -10 TA = 25°C -20 -30 -40 -50 -60 -4.0 6.0 16 26 36 46 56 66 76 INTERFERER FREQUENCY DELTA (MHz) Figure 30. C/I Performance for Channel 3 (2.405 GHz, High-Side Injection) INTERFERER LEVEL (dBc) 10 0 -10 -20 TA = 25°C -30 -40 -50 -60 -76 -66 -56 -46 -36 -26 -16 -6.0 4.0 INTERFERER FREQUENCY DELTA (MHz) Figure 31. C/I Performance for Channel 75 (2.477 GHz, Low-Side Injection) MOTOROLA MC13180 Product Preview 43 Functional Description INTERFERER LEVEL (dBc) 10 0 -10 -20 TA = 25°C -30 -40 -50 -60 -40 -30 -20 -10 0 10 20 30 40 INTERFERER FREQUENCY DELTA (MHz) Figure 32. C/I Performance for Channel 39 (2.441 GHz, High-Side Injection) INTERFERER LEVEL (dBc) 10 0 TA = 25°C -10 -20 -30 -40 -50 -60 -15 -5.0 -10 0 5.0 10 15 INTERFERER FREQUENCY DELTA (MHz) Figure 33. C/I Performance for Channel 39 (2.441 GHz, High-Side Injection) 10 INTERFERER LEVEL (dBc) 0 -10 -20 TA = 85°C -30 -40 -50 -60 -3.0 -20°C -1.0 1.0 3.0 5.0 7.0 9.0 11 13 15 INTERFERER FREQUENCY DELTA (MHz) Figure 34. C/I Performance versus Temperature 4.35 Transmitter The MC13180 uses a direct launch transmitter, taken from the output of the local oscillator (LO). During a transmit cycle the VCO of the LO is automatically trimmed. Following the LO are the output power stages, sequenced in the proper order. To minimize splattering, the output of the programmable low power 44 MC13180 Product Preview MOTOROLA Functional Description amplifier (LPA) drives a balanced ramp up/ramp down generator, which is fed to a “Balun” to provide a single-ended output for the external antenna switch. The transmit start up/warm down sequences are shown in Figure 38. 4.36 Programmable LPA The output power of the LPA can be varied by programming PA Bias Adjust (R5/2-0) in the register map. Table 22 displays the response of RF output power, current consumption and 2nd Harmonic power level with respect to the programmable bit settings. Class 1 operations are supported through the use of an external power amplifier not shown here. Refer to Applications Information Class 1 Operation for more detail. Figures 35 and 36 provide additional LPA characteristic data. 4.37 Ramp Generator The ramp generator has an exponential ramp up/ramp down function with a maximum settling time of 20 µs. Increasing the output power exponentially is useful to avoid splattering and minimize load pulling. 4.38 External Balun The LPA provides a differential output that is converted to a single ended signal through the use of an inexpensive printed circuit board balun. Optionally, an external discrete balun may be used. Figures 37 and 42 show the physical dimensions and characteristics of this network. Table 23 shows the output impedance, S22 of the PA during active and inactive cycles. Table 22. RF Power Out versus PA Bias Adjust PA Bias Adjust Output Power (dBm) Current Consumption (Continuous Transmit)(mA) 2nd Harmonic (dBc) R5/2 R5/1 R5/0 0 0 0 -0.9 23 -21 0 0 1 -10.8 20 -29 0 1 0 1.9 27 -19 0 1 1 -7.6 22 -24 1 0 0 5.3 33 -18 1 0 1 -3.5 27 -18 1 1 0 6.1 40 -20 1 1 1 3.5 35 -14 MOTOROLA MC13180 Product Preview 45 Functional Description 2.5 2.5 Pout, OUTPUT POWER (dB) Pout, OUTPUT POWER (dB) 3.0 2.0 1.5 1.0 TA = 25°C 0.5 0 2400 2420 2440 2460 2.0 1.5 1.0 VCCRF = 2.7 V 0.5 0 -40 2480 -15 10 35 60 Figure 35. RF Output Power versus Carrier Frequency Figure 36. RF Output Power versus Temperature 22 81 gnd 86 C13 33 pF PAPin 8 TL3 TL1 8 C11 1.5 pF TL2 32 TL4 PA+ Pin 6 44 R5 620 Ω Via to Power Plane R6 12 620 Ω C4 C12 560 pF 3.3 pF gnd 34 Center of QFN Pads MC13180 Balun Substrate εr = 3.9 Finished Metal Thickness = 1.7 mils Substrate thickness to ground = 10 mils Units are in mils See Figure 42 19.8 Figure 37. Balun Physical Dimensions Table 23. S22 for PA During Transmit (R5/2-0 = 010)(Measured Differential-Ended) 46 85 TEMPERATURE (°C) f, FREQUENCY (MHz) Operation Mode Frequency (GHz) MAG (dB) Angle (degree) Active 2.45 -5.5 -120 Inactive 2.45 0.2 -111 MC13180 Product Preview MOTOROLA Functional Description 4.39 External Antenna Switch An external antenna switch, shown in Figure 42, provides isolation between the PA output and the LNA input, and subsequently enables transmit and receive cycles. The controls to the switch are GPO and EPAEN, Pins 9 and 4, respectively, of the MC13180 device. When GPO is high, the switch is set to transmit mode. EPAEN serves as a complementary driver in this configuration. See Applications Information General Purpose Output and External Power Amplifier for further discussion. 4.40 General Purpose Output (GPO) Pin The MC13180 General Purpose Output (GPO) is located at Pin 9 of the device. Its output is programmed for general use by setting bit R2/8 in the register map. The GPO can serve as a control line for an external antenna switch. 4.41 External Power Amplifier Enable (EPAEN) Pin The External Power Amplifier Enable (EPAEN) output of MC13180 is located at Pin 4 of the device. EPAEN may be used in two applications. It may assist in Class 1 Operation by driving an external power amplifier; or it may serve as a complementary driver to a dual port antenna switch as seen in Figure 42. If EPAEN is not required for the desired application, it may be disabled by setting R11/6 to zero. 1.0 µs RTXEN 106 µ s 15 µs EPADAC (R9/7 = 1) 44 µs GPO (Antenna Switch) 15 µs 1.0 µs EPAEN (R11/6 = 1) 4.0 µ s Internal PA Enable 20 µs 20 µ s 5.0 µ s Power Ramp Transmit Sync Delay (R8/15-8 = 18410) 18410 Figure 38. Ramp Generator (Transmit Cycle) Timing Diagram MOTOROLA MC13180 Product Preview 47 Applications Information 5 Applications Information 5.1 General Purpose Output (GPO) The GPO must be set to a logic one during a transmit cycle and set to a logic zero during a receive cycle via a SPI write operation, when driving an external antenna switch as shown in Figure 42. When the GPO is not actively used to drive a peripheral, R2/8 in the address register map is considered a don't care. 5.2 General Purpose Output Invert (GPO Invert) The MC13180 General Purpose Output (GPO) Invert bit (R3/6) can be used to invert the output value of GPO located at Pin 9 of the device. The default setting for GPO Invert is zero (i.e., no inversion). When it is set to one, the GPO output pin assumes the inverted value of GPO in the register map location R2/8. This is a useful feature when an inverter is not available. It can serve as a complement to GPO Invert. 5.3 External Power Amplifier Enable (EPAEN) The External Power Amplifier Enable (EPAEN) bit, R6/15, can be used in two applications. It may serve as a complementary driver to a dual-port antenna. This is accomplished when External PA Enable Invert, R3/10, is set to a logic one. In this configuration, EPAEN assumes the inverted value of GPO, which is the second driver for the antenna switch. EPAEN may also assist in Class 1 operation by setting bit R11/6 to a logic high. This setting allows the MC13180 to drive an external power amplifer. Setting bits R11/6 and R3/10 to zero disables EPAEN. 5.4 External Power Amplifier DAC (EPADAC) The Bluetooth specification for Class 1 Power implementation requires power control from 4.0 dBm (or less) to 20 dBm (max) power. The MC13180 external power amplifier digital to analog converter (EPADAC) output (Pin 10) provides a voltage reference for power control of an external power amplifier (PA), if desired. The EPADAC output is enabled when External PA DAC Enable (R11/7) is set to one. Setting R11/7 to zero pulls the EPADAC output to ground. When enabled, the EPADAC output voltage is controlled by the PA DAC setting (R3/5-0). The minimum EPADAC output voltage is 0 Vdc and the maximum output voltage is 3.2 Vdc. The 6-bit resolution of the PA DAC setting corresponds to approximately 50 mV/bit. When using a VCCRF < 3.2 Vdc, the maximum EPADAC output voltage is reduced to VCCRF (i.e., the full-scale output of the PA DAC is referenced to 3.2 V). To obtain optimum functionality of EPADAC with an external PA, this feature should be utilized with the External PA Enable. Refer to the Applications Information section for additional usage information. The output of the EPADAC, when enabled, is gated by the MC13180 sequence manager. During a Sleep, Idle, or RX cycle, the output is set to zero volts. The programmed value of the output voltage is only achieved during an active TX cycle as shown in Figure 38. 5.5 PIN Implementation of Antenna Switch An alternative approach to using an RF switch is to utilize a PIN diode technique as shown in Figure 39. When both PIN diodes are in the high resistance (i.e., un-biased) state, the transmitter is isolated from the antenna and LNA input. Conversely, when both PIN diodes are in the low resistance (i.e., forward-biased) 48 MC13180 Product Preview MOTOROLA Applications Information state, the λ/4 section appears as an open circuit from the transmitter output to the LNA input, and the transmitter output is coupled directly to the antenna through the bandpass filter. For receive mode, GPO is set low. For transmit mode, GPO is set high. Some advantages to this implementation would be very low current consumption while in receive or idle mode, moderate current consumption while in transmit mode, high receiver isolation, and low cost. λ/4 LNA Pin 1 Antenna GPO Pin 9 Band Pass Filter Pin 6 Balun PA Pin 8 Figure 39. PIN Implementation of Antenna Switch 5.6 Class 1 Operation Class 1 Operation can be realized by the MC13180 with the use of an external power amplifier (PA) such as the MRFIC2408 as shown in Figure 40. During a transmit cycle EPAEN drives the external PA Bias Enable. Figure 38 shows the transmitter warm up sequence for this mode of operation. The external PA is required to be fully powered within 5 µs. It is recommended that the antenna switch be set to the TX position before the internal PA is enabled. This option minimizes frequency pulling of the VCO, which may appear as splatter. The power level of the external PA can be digitally controlled through the use of a digital-to-analog converter (EPADAC) internal to the MC13180. To access the DAC capability, External PA DAC Enable (R11/7), must be set to one.This line is generally decoupled with a small capacitor value (≈ 0.1 µF). Approximately 44 µs is available to fully charge this capacitor (see Figure 38). 5.7 Manufacturer Code The format of the device identification code is shown in Figure 41. The 32-bit value is defined in the IEEE 1149.1 specification. MOTOROLA MC13180 Product Preview 49 Applications Information System Supply 3.0 V VCC1 VCC2 MRFIC2408 RFin RFout Bias EN Switch EPAEN VPC EPADAC RFin (LNA) Printed Balun PA+ PA- RTXEN MC13180 NOTE: MC13180 is used at 2.7 V, therefore EPAEN and EPADAC are 2.7 V lines that feed into the MRFIC2408. The MRFIC2408 is specified to operate at 3.0 V or above but is functional at 2.7 V with a slight degradation in performance. Figure 40. R31/15-12 Manufacturer Version Number MSB 4 Bits R31/11-0 R30/15-12 Manufacturer Part Number R30/11-8 # of continuation code bytes R30/7-1 R30/0 Most significant byte (as noncontinuation) code 1 LSB 16 Bits 4 Bits =0 7 Bits Figure 41. Manufacturer Identification Code 50 MC13180 Product Preview MOTOROLA SMA Johnson 142-0701-881 TL8 TL7 MC13180 Product Preview J3 GND J2 C44 N/C N/C R6 R5 TL1 TL2 TL5 TL6 620 C11 1.5 p (±0.1 pF) 620 C10 22p N/C C16 TL3 TL4 3.3p C4 L1 3.9n C9 N/C VccPA TP2 TP1 TP4 2 1 C43 NDK Y1 N/C VccDEMO VccLIM N/C 13 MHz C42 TIN- TIN+ EPADAC GPO PA- GNDPA PA+ VCCPA EPAEN GNDLNA RFIN GNDLNA U7 W-168-179 12 11 10 9 8 7 6 5 4 3 Figure 42. Application Evaluation Schematic (Continued on Page 52) 33p 560p 1 2 3 C13 AS179-92 Alpha Industries V2 J1 V1 U6 C12 VccRF 6 5 4 C45 6.8p C41 Default Units: Microfarads, Microhenries and Ohms N/C = No Component Printed Transmission Lines TL1 = 77 W, 9.9° @ 2.45 GHz TL2 = 77 Ω, 9.9° @ 2.45 GHz TL3 = 77 Ω, 10.5° @ 2.45 GHz TL4 = 77 Ω, 10.5° @ 2.45 GHz TL5 = 50 Ω TL6 = 50 Ω TL7 = 50 Ω TL8 = 50 Ω 2.4 GHz BPF LFSN25N19C2450B FL1 Murata VccVCO C7 27k VccMOD R4 MC13180 VccMIX C5 SPICK CLK FS RFDataIO RTXEN 30 29 28 27 26 C2 33 n C3 0 R1 SPID 31 25 NCEN 32 N/C N/C VccXTAL VCCDC RTXEN RFDATA FS CLK SCK SDATA CE RES NRES 33 34 35 36 C8 R2 VSS VDD VDDINT TP3 12p 22p 39 N/C VccCP C6 VccPRE 40 270p VccLNA 48 14 TOUT+ 13 VCCLNA 47 GNDMIX GNDLIM 15 TOUT- 46 VCCMIX 45 VCCMOD GNDDEM 17 VCCDEM 18 GNDX 19 BASE 20 VCCLIM 16 43 GNDVCO 44 GNDMOD 42 VCCVCO 41 GNDPRE EMM 21 VCCPRE 23 COLL 22 MLPF DCVCO 37 VCCCP 38 GNDCP DCCP 24 51 MOTOROLA C37 1.0 µ VccDC VddINT Vdd 52 MC13180 Product Preview MOTOROLA 4 3 2 1 NOTE: RF DC Pwr J2 1µ F Vcc 3 2 1 R10 R11 N/C For TC1071VCT Only VccRF TC1073-2.7VCT713 MicroChip SHDN GND VIN U3 VOUT N/C N/C R12 ERROR BYPASS 4 5 6 N/C C25 470p C40 J1 12 14 16 18 20 13 15 17 19 NCEN SPICK VddINT 10 9 11 RTXEN SPID FS NRES RFDataIO 8 N/C R14 N/C VddINT C29 100n VccDEMO VccLIM C26 6 3 VccDC 100n C28 100n R13 VccCP VccMOD VccXTAL C18 6.8p C24 VccMIX VccVCO VccPRE 6.8p 4 2 1 I/O Conn. VccLNA 2.2n 100n 7 C39 1.0 µ C23 C22 5 CLK VccRF Figure 42 Application Evaluation Schematic (Continued) R10 can be utilized as a regulator bypass. R11, R12, and C25 can be utilized for alternative regulator configurations. C38 100n Vdd VccPA C31 Application Evaluation Printed Circuit Boards 6 Application Evaluation Printed Circuit Boards Figure 43. Application Evaluation PCB Assembly Diagram (Not to Scale) Table 24. Application Evaluation PCB Bill of Materials REF Size Value R1 0402 0 R2, 10, 11, 12, 13, 14 0402 N/C R4 0402 R5, R6 Part Number Source CR0402-16W-000 VENKEL 27 k P27kjct-nd Digikey 0402 620 P620kjct-nd Digikey C2 0402 33 n PCC2140CT-ND Digikey C3, 6, 9, 16, 25, 42, 43, 44, 45 0402 N/C C4 0402 3.3 p EVK105CH3R3JW TAIYO YUDEN C5, 10 0402 22 p C0402COG500220JNE VENKEL C7 0402 270 p PCC1714CT-ND Digikey N/C = No Component MOTOROLA MC13180 Product Preview 53 Application Evaluation Printed Circuit Boards Table 24. Application Evaluation PCB Bill of Materials (Continued) REF Size Value C8 0402 12 p PCC120CQCT-ND Digikey C11 0402 1.5 p (±0.1 pF) EVK105CH1R5BW TAIYO YUDEN C12 0402 560 p C0402X7R500561JNE VENKEL C13 0402 33 p C0402COG500330JNE VENKEL C18, 24, 41 0402 6.8 p C0402COG5006R8JNE VENKEL C22, 26, 28, 29, 31 0402 100 n C0402X7R500104JNE VENKEL C23 0402 2.2 n PCC222BQCT-ND Digikey C37, 38, 39 0603 1.0 µ LMK107F105ZA TAIYO YUDEN C40 0402 470 p PCC471BQCT-ND Digikey L1 0402 3.9 n HK1005-3N9S TAIYO YUDEN U7 QFN-48 Transceiver MC13180 Motorola U6 SC-706 RF Switch AS179-92 Alpha Indust. Y1 2.5 x 4 mm 13 MHz W-168-179 NDK FL1 2.5 X 3.2 mm 2.4 GHz LFSN25N19C2450BAHA504 Murata U3 (standard) SOT-23-6 2.7 V TC1073-2.7VCH713 Microchip U3 (optional) SOT-23-5 Adjustable TC1071VCT Microchip J1 10 X 2 Socket 66956-010 Newark J2 2X1 Connector 22-05-3021 Newark SMA SMA Connector 142-0701-881 Johnson 54 Part Number MC13180 Product Preview Source MOTOROLA 1.175 in Application Evaluation Printed Circuit Boards 1.120 in Figure 44. Top Side Figure 45. Ground Plane Figure 46. VCC Plane Figure 47. Bottom Plane MOTOROLA MC13180 Product Preview 55 Application Evaluation Printed Circuit Boards NOTE: Solder Paste: SMQ92J, Indium Corp Solder Stencil Thickness: 5 mils screen Solder Stencil QFN Ground Flag Area: 80% of sodlerable area Solder Stencil QFN Lead Pad Area: 100% of solderable area The ground flag requires good condition for optimum intermodulation and C/I performance. Figure 48. Recommended QFN Ground Flag Configuration 56 MC13180 Product Preview MOTOROLA Packaging 7 Packaging PIN 1 INDEX AREA 0.1 C 7 A 2X M 0.1 C 0.1 C G 2X 1.0 0.8 1.00 0.75 0.05 C 6 7 (0.24) 0.05 0.00 (0.5) C SEATING PLANE DETAIL G VIEW ROTATED 90° CLOCKWISE M B 0.1 C A B DETAIL M PIN 1 IDENTIFIER 5.25 4.95 37 EXPOSED DIE ATTACH PAD 48 36 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. CORNER LEADS CAN BE USED FOR THERMAL OR GROUND AND ARE TIED TO THE DIE ATTACH PAD. THESE LEADS ARE NOT INCLUDED IN THE LEAD COUNT. 6. COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND DIE ATTACH PAD. 7. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12°. 0.25 1 5.25 4.95 0.1 C A B N 0.5 25 24 48X 44X 12 13 0.5 0.3 48X VIEW M-M 0.30 0.18 0.1 M C A B 0.05 M C (45°) (90°) DETAIL T (0.25) 48X 2X 0.39 0.31 0.065 0.015 (2.73) 2X DETAIL N PREFERRED CORNER CONFIGURATION 0.1 0.0 DETAIL M DETAIL T PREFERRED PIN 1 BACKSIDE IDENTIFIER PREFERRED PIN 1 BACKSIDE IDENTIFIER 4 (45°) (90°) DETAIL S 0.60 0.24 2X (0.4) (0.18) 0.60 0.24 0.39 0.31 0.1 MIN DETAIL N DETAIL M DETAIL S CORNER CONFIGURATION OPTION PIN 1 BACKSIDE IDENTIFIER OPTION PIN 1 BACKSIDE IDENTIFIER OPTION 4 5 Figure 49. Outline Dimensions for QFN-48 (Case 1314-02, Issue C) MOTOROLA MC13180 Product Preview 57 HOW TO REACH US: Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to USA/EUROPE/LOCATIONS NOT LISTED: design or fabricate any integrated circuits or integrated circuits based on the information in this Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 document. JAPAN: for any particular purpose, nor does Motorola assume any liability arising out of the application or Motorola reserves the right to make changes without further notice to any products herein. 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